GB2195208A - Mounting electrical components - Google Patents

Mounting electrical components Download PDF

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Publication number
GB2195208A
GB2195208A GB08622528A GB8622528A GB2195208A GB 2195208 A GB2195208 A GB 2195208A GB 08622528 A GB08622528 A GB 08622528A GB 8622528 A GB8622528 A GB 8622528A GB 2195208 A GB2195208 A GB 2195208A
Authority
GB
United Kingdom
Prior art keywords
sheet
component
mounting
mounting arrangement
electrical component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08622528A
Other versions
GB8622528D0 (en
Inventor
Ian Robins
Alastair Sibbald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thorn EMI PLC
Original Assignee
Thorn EMI PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thorn EMI PLC filed Critical Thorn EMI PLC
Priority to GB08622528A priority Critical patent/GB2195208A/en
Publication of GB8622528D0 publication Critical patent/GB8622528D0/en
Publication of GB2195208A publication Critical patent/GB2195208A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N33/00—Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
    • G01N33/0004—Gaseous mixtures, e.g. polluted air
    • G01N33/0009—General constructional details of gas analysers, e.g. portable test equipment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4141—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS specially adapted for gases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Abstract

A mounting arrangement for an electrical component (1) comprises a sheet (2) of a thermally insulating polyimide overlying a hole (3) in a header (4). The component (1) is mounted on an unsupported part of the sheet. <IMAGE>

Description

SPECIFICATION Mounting electrical components This invention relates to an arrangement for mounting an electrical component and it relates also to a method of mounting an electrical component. The invention has particular, though not exclusive, application in mounting a component which is intended to operate at an elevated temperature, significially above ambient temperature.
It is often desirable to thermally isolate an electrical component from its support thereby to promote satisfactory operation of the component and or to protect neighbouring circuitry from overheating. This can be especially important in the case of a gas-sensitive device (e.g. a gassensitive field effect transistor) which is designed to operate normally at an elevated temperature (typically about 150 C) and which is often provided with a dedicated "on-chip" heater. The relatively high operating temperature tends to enhance both the speed of response and recovery of the device.
Hitherto, it has been customary to provide a thermally insulative barrier or break between the component and its support. Typically, the barrier may comprise a glass spacer mounted directly on the support, as shown in Fig. 1 of the accompanying drawings. Although some improvement can be achieved with an arrangement of this kind, heat loss to the support may still be appreciable thereby increasing significantly the power consumption of the component and or adversely affecting operation of the component and any neighbouring circuitry that may be present.
It is an object of the present invention, therefore, to provide a different mounting arrangement which at least alleviates the above-described problem.
According to a first aspect of the invention there is provided a mounting arrangement for an electrical component, the arrangement including a sheet of a thermally insulative material and means to directly support a part only of the sheet, the electrical component being mounted on a remaining part of the sheet which is not directly supported.
The support means may comprise a header or alternatively the support means may comprise a substrate carrying a number of other electrical components and or electrical connectors.
The sheet may overlie a hole in the support means so that, in effect, the component mounted on the sheet is suspended over the hole.
The inventors have found that, as compared with hithertoknown arrangements, a mounting arranged in accordance with this invention achieves a substantial reduction in the amount of heat lost to the support means. The invention is particularly advantageous if the electrical component (e.g. a gas-sensitive MIS field effect transistor), mounted on the sheet, is intended to operate at an elevated temperature substantially above ambient temperature. A substantially reduced heat loss may give rise to lower power consumption and more stable operating conditions. Moreover, there is reduced heating of the other components which may be carried by the support means and whose operation and reliability could be impaired by overheating.
According to a further aspect of the invention there is provided a method of mounting an electrical component, the method including the steps of mounting the component on a sheet of a thermally insulative material and directly supporting a part only of the sheet, so that said component is mounted on a remaining part of the sheet which is not directly supported.
In order that the invention may be carried readily into effect specified embodiments thereof are now described, by way of example only, by reference to the accompanying drawings of which Fig. 1 shows a cross-sectional view through a known mounting arrangement, Figure 2 shows a cross-sectional view through a mounting arrangement in accordance with the present invention and Fig. 3 shows a cross-sectional view through another mounting arrangement in accordance with the invention.
Referring now to Fig. 2 of the drawings a gas-sensitive MIS field effect transistor 1 is mounted on a sheet 2 of a polyimide, a thermally insulative material. The sheet is typically between 1 and 100#m thick. As is conventional, the transistor is designed to operate at an elevated temperature, typically around 150 C, and is often provided with a dedicated "on-chip" heater.
The sheet overlies a hole 3 in a header 4, the sheet being attached, by glueing, for example at its periphery only so that, in effect, the transistor is suspended over the hole.
If the transistor comprises part of a hybrid circuit then the sheet may be attached to a substrate, made of a ceramic for examole, carrying other circuit components.
Alternatively, a somewhat different mounting arrangement, shown in Fig. 3, could be used. In this case, sheet 2 is mounted on an intermediate substrate 6, this substrate being attached to a further substrate 7 carrying the other circuit components. As will be apparent from the drawing, the transistor 1 is suspended over a hole 8 in substrate 6 which is in register with a hole 9 in substrate 7. Holes 8 and 9 may be formed while the ceramic is in its "green state" (i.e. unfired, and so soft), though alternatively the holes could be formed when the substrates are moulded.
The inventors have found that the heat loss experienced by a component mounted in accordance with the present invention is significantly less than that experienced by the same, or an equivalent, component mounted using a hithertoknown arrangement, of the kind described by reference to Fig. 1 for example. Referring to Fig. 1 it will be apparent that the glass spacer, mounting the component, presents a heat leakage path having a relatively short length 1, the thickness of the spacer, and a relatively large cross-sectional area A, related to the dimensions of the component. The rate of heat loss will, in general, be related to the ratio A/1, and so the heat loss sustained by the component could be appreciable.In contrast, the arrangements shown in Figs. 2 and 3 of the drawings present a much longer heat leakage path having a comparatively small cross-sectional area, related to the thickness of insulating sheet 2, and so a component mounted on the sheet suffers a relatively small heat loss.
In the case of a component, such as a gas-sensitive MIS field effect transistor, which is intended to operate at an elevated temperature, a reduced heat loss gives rise to more stable operating conditions and a reduced power consumption.
Table 1, below, illustrates, by way of example, how the power consumption of a gas-sensitive MIS field effect transistor operating at 2000C depends critically on the mounting arrangement used.
TABLE 1 MOUNTING ARRANGEMENT POWER CONSUMPTION 1. Transistor mounted on 1.6W header directly 2. Transistor mounted 0.9W on glass spacer (Fig. 1) 3. Transistor mounted 0.15W on polyimide sheet (Fig. 2) The values listed in Table 1 demonstrate the striking reduction in power consumption which can be achieved using a mounting arrangement in accordance with the present invention. Moreover, the present mounting arrangement is effective to significantly reduce undesirable heating of other, associated components which might be present.
It will be understood that sheet 2 need not necessarily be made of a polyimide; other thermally insulative materials, typically polymers, having a sufficient mechanical strength and thermal stability could be used.
Furthermore; although the invention has been described in detail by reference to a mounting arrangement for an electrical component operating at an elevated temperature, the invention can also be used to mount other electrical components which it is desirable to isolate thermally so as to promote satisfactory operation of the component and or to protect neighbouring components from overheating.

Claims (7)

1. A mounting arrangement for an electrical component, the arrangement including a sheet of a thermally insulative material and means to directly support a part only of the sheet, the electrical component being mounted on a remaining part of the sheet which is not directly supported.
2. A mounting arrangement according to Claim 1 wherein said thermally insulative material is a polyimide.
3. A mounting arrangement according to Claim 1 or Claim 2 wherein said sheet overlies a hole in the support means.
4. A mounting arrangement according to any one of Claims 1 to 3 wherein the support means is mounted on a substrate carrying a number of other electrical components.
5. A method of mounting an electrical component, the method including the steps of mounting the component on a sheet of a thermally insulative material and directly supporting a part only of the sheet so that the component is mounted on a remaining part of the sheet which is not directly supported.
6. A mounting arrangement substantially as hereinbefore described by reference to Figs. 2 and 3 of the accompanying drawings.
7. A method of mounting an electrical component substantially as herein described by reference to Figs. 2 and 3 of the accompanying drawings.
GB08622528A 1986-09-18 1986-09-18 Mounting electrical components Withdrawn GB2195208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08622528A GB2195208A (en) 1986-09-18 1986-09-18 Mounting electrical components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08622528A GB2195208A (en) 1986-09-18 1986-09-18 Mounting electrical components

Publications (2)

Publication Number Publication Date
GB8622528D0 GB8622528D0 (en) 1986-10-22
GB2195208A true GB2195208A (en) 1988-03-30

Family

ID=10604410

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08622528A Withdrawn GB2195208A (en) 1986-09-18 1986-09-18 Mounting electrical components

Country Status (1)

Country Link
GB (1) GB2195208A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998032009A1 (en) * 1997-01-15 1998-07-23 University Of Warwick Gas-sensing semiconductor devices
CN106961783A (en) * 2015-12-02 2017-07-18 三星显示有限公司 Circuit board and the display device with the circuit board

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1137907A (en) * 1964-12-09 1968-12-27 Signetics Corp Improvements in or relating to multiple-chip integrated circuit assembly with interconnection structure
GB1576589A (en) * 1977-03-28 1980-10-08 All States Plastic Mfg Co Anchor base fastener
GB2082397A (en) * 1980-08-18 1982-03-03 Ebauchesfabrik Eta Ag Process for producing a casing for an electronic component
GB2098398A (en) * 1981-05-13 1982-11-17 Honeywell Ltd Electronic packaging system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1137907A (en) * 1964-12-09 1968-12-27 Signetics Corp Improvements in or relating to multiple-chip integrated circuit assembly with interconnection structure
GB1576589A (en) * 1977-03-28 1980-10-08 All States Plastic Mfg Co Anchor base fastener
GB2082397A (en) * 1980-08-18 1982-03-03 Ebauchesfabrik Eta Ag Process for producing a casing for an electronic component
GB2098398A (en) * 1981-05-13 1982-11-17 Honeywell Ltd Electronic packaging system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998032009A1 (en) * 1997-01-15 1998-07-23 University Of Warwick Gas-sensing semiconductor devices
US6111280A (en) * 1997-01-15 2000-08-29 University Of Warwick Gas-sensing semiconductor devices
CN106961783A (en) * 2015-12-02 2017-07-18 三星显示有限公司 Circuit board and the display device with the circuit board
CN106961783B (en) * 2015-12-02 2021-10-08 三星显示有限公司 Circuit board and display device having the same

Also Published As

Publication number Publication date
GB8622528D0 (en) 1986-10-22

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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)