GB2194365A - Digital word comparison - Google Patents
Digital word comparison Download PDFInfo
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- GB2194365A GB2194365A GB08620446A GB8620446A GB2194365A GB 2194365 A GB2194365 A GB 2194365A GB 08620446 A GB08620446 A GB 08620446A GB 8620446 A GB8620446 A GB 8620446A GB 2194365 A GB2194365 A GB 2194365A
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- digital word
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- logic device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
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- Logic Circuits (AREA)
Abstract
A method of comparing the value A of an input digital word, the value of which may vary, with the value B of a fixed digital word, comprises programming a programmable array logic device in dependence on the fixed digital word so that, on supplying the input digital word to the device, the first most significant bit at which the input digital word and the fixed digital word differ is effectively checked, and in dependence on the result deriving an output signal which indicates whether or not the value of the input digital word exceeds the value of the fixed digital word. Fig. 2 shows the logic device arrangement for B=100 (binary) as an example. In general, for an N-bit input word a maximum of only N/2 product terms need be generated by the logic device for summation. <IMAGE>
Description
SPECIFICATION
Digital word comparison
This invention relates to digital word comparison.
The need to compare the relative values of two binary numbers expressed as digital words, or to determine whether the value of a binary word falls within a given range, arises quite often in the processing of binary data. For example, when processing a digital television signal to effect expansion of the corresponding image to be displayed on a television screen, it is necessary to be able to identify pixel addresses which, due to the image expansion, no longer fall within the confines of the image to be displayed.
Currently there are a number of specialized semiconductor integrated circuit chips available for effecting such a comparison, but in applications where one of the digital words used in the comparison is fixed, these specialized chips are somewhat uneconomical to use, because in such cases half of the pins on the chip are not used. An alternative is to use a programmable read only memory (PROM), but this is only possible for short words, because to compare N-bit digital words, a PROM of size 2N is required.
According to the present invention there is provided a method of comparing the value of an input digital word, the value of which may vary, with the value of a fixed digital word, comprising the steps of: programming a programmable array logic device in dependence on said fixed digital word so that, on supplying said input digital word to said programmable array logic device, the first most significant bit at which said input digital word and said fixed digital word differ are compared; and in dependence on said comparison deriving an output signal which indicates whether or not the value of said input digital word exceeds the value of said fixed digital word.
According to the present invention there is also provided a digital word comparator for comparing the value of an input digital word, the value of which may vary, with the value of a fixed digital word, the comparator comprising:
a programmable array logic device programmed in dependence on said fixed digital word so that, on supplying said input digital word to said programmable array logic device, the first most significant bit at which said input digital word and said fixed digital word differ are compared;
said device supplying an output signal in dependence on said comparison which output signal indicates whether or not the value of said input digital word exceeds the value of said fixed digital word.
In order to perform a logic function in a programmable array logic (PAL) device, it is necessary to express the required operation as the sum of products. In preferred embodiments of the invention, it is possible to compare a variable input N-bit digital word with a fixed digital word using a maximum of N/2 sum terms, so enabling digital words with relatively large numbers of bits to be compared in relatively small PAL devices.
The invention will now be described by way of example with reference to the accompanying drawing, in which:
Figure 1 shows diagrammatically a simple digital word comparator; and
Figure 2 shows in block diagrammatic form the equivalent in discrete logic gate form of an embodiment of digital word comparator according to the present invention.
Before describing an embodiment of the invention, the mathematical basis of the invention will be explained. For a number A expressed as a digital word to be greater than a number B, also expressed as a digital word, it is only necessary to examine the first most significant bit at which the two digital words differ. If this bit in A is '1' then A is greater than B, whereas if this bit in A is '0' then A is less than B. An exclusive-OR function can be used to mask out bits at which the two digital words are the same.
This will now be considered in more detail for two 3-bit digital words A and B, it being required to determine whether A is greater than B. The words A and B when written as sums of powers of 2 are as follows:
A = A2 22 + A1 21 + A0 20 and
B = B2 22 + Bl 21 + Bo 20 Then A is greater than B if all the higher order bits of A and B are equal, and on the first bit on which they differ (assumed to be the rth bit) An= 1 and Bn=O.This may be written as:
A > B = A2B2 + A2B2A1B1 + A2B2A1B1 + A2B2A1B1A0B0
LLJII L-l + A2B2A1B1A0B0 + A2B2A1B1A0B% + A2B2A1B1A0B0
the right-hand side of the expression (3) sets out each of the conditions which, if satisfied, results in A being greater than B. The first term signifies that A2=1 1and B2=O. If this is true then A is greater than B, whatever the values of the remaining bits. The second and third terms
relate to the cases where the most significant bits are the same in A and B; 'O' in the case of the second term and '1' in the case of the third term.In that case, it is necessary to go to the
second bit to ascertain whether A is greater than B, the requirement in each case being that A1=1 and B1=O. The third to sixth terms refer to the cases where the two most significant bits
are the same in both A and B;'00','01', '10' and '11' respectively. In that case it is necessary to go to the least significant bit to ascertain whether A is greater than B, the requirement in each case being that Ao=1 1and B0=0. Any other combination of bits, not covered by any of these six terms, means that A is not greater than B.
The expression (3) can be simplified to: A > B = A2B2 + A1B1 (A2B2 + A2B2) + AoBo (A2B2 +A2B2) (Ali31 + A1B1)
Since, for example, the expression in the bracket in the second line of the expression (4) is
the 'exclusive-OR' of A2 and B2 negated, the expression (4) can be re-written as follows:
A > B = A2B2 + A181 (A2 # B2) +A0B0 (A2 + B2) (A1 t B1)
It can be shown that the expression (5) is a particular example of a general expression which
can be written as follows: :
where C is a shorthand notation for 'ORing' a sequence of terms, # is a shorthand notation for 'ANDing' a sequence of terms, and k and m are integers indicating the subscripts of A and
B, corresponding to the powers of two, in the expressions (1) and (2).
For example, as indicated in Figure 1, suppose that A is a 3-bit digital word, and it is required to ascertain whether A is greater than 4. Substituting in the expression (6):
= A2B2 (k=2)
(k=l) +A1 B
1 (A2 # B2) + Aoeo (A2 + B2) (Al t B1) (k=O)
This is seen to be the same as the expression (5) above.Since for B=4, B2=1, B,=O and Bo=O; A > B = A1A2 + AOA2 l (7) This result can be checked by reference to the following table:
A A2 A1 A0 AB 0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 0
4 1 Q 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1
Figure 2 shows the equivalent in discrete logic gate form of an embodiment for evaluating the expression (7). The circuit comprises two AND gates 1 and 2, an inverter 3 and an OR gate 4.
When inputs A0, A1 and A2 are supplied to the three inputs as shown, the output of the AND gate 1 corresponds to the first term on the right-hand side of the expression (7), and the output of the AND gate 2 corresponds to the second term on the right-hand side of the expression (7).
A combination of the outputs of the AND gates 1 and 2 in the OR gate 4 will be seen to result in an output '1' when A is greater than B, and an output '0' when A is not greater than B, thus giving the required result.
Returning now to the expression (6), which is true when neither A nor B is fixed in value, it will be seen that if B has a fixed value, then the expression (6) reduces to:
for Bk = 0
The number of sum terms to be handled is usually the limiting factor when implementing logic
equations in a PAL device. From the expression (8) it can be seen that the number of sum
terms is equal to the number of 'O's in the fixed word B, which for large values of B gives a
compact realization of the A is greater than B function. However, it will be seen that as B gets
smaller, the number of sum terms tends towards N.
It is possible to reduce the number of sum terms to be handled by noting that: A > B = A # B (A=B) + (Ae B)
By similar reasoning to that above:
for Bk = 1
The number of sum terms in the expression (9) is equal to the number of '1 's in B, so the expression (9) is more efficient than the expression (8) for small values of B. The calculation of
A=B adds one extra sum term to the calculation of A is greater than B, where B contains more '1's than 'O's.
Thus:
N-l (A=B) = # Am + Bm
m=O
N-1 m=0
Am if Bm = 1 Am if Bm = 0
for fixed B ...(1O) hence A > B may also be written:
for Bk = 1 ...(11)
If the expression (9) is used, the number of sum terms is equal to the number of 'O's in B, whereas if the expression (11) is used, the number of sum terms is equal to one plus the number of '1's in B. Thus, depending on the value of the fixed word B, the expression (9) or (11) is used, so ensuring a maximum of N/2 sum terms to be handled in the PAL device.
The expressions (9) and (11) are valid for all unipolar binary numbers, but their use can be extended to bipolar binary numbers by inverting the most significant bits of A and B. This inversion can of course readily be effected in the PAL device.
An embodiment of digital word comparator in accordance with the present invention will now be described. In this embodiment the variable input word A has twenty bits, the fixed word B is 50,000, and the comparison carried out therefore is whether A is greater than 50,000. Firstly, B is expressed in binary form such that:
where N is the number of bits (20) in the variable input word A to be compared: m 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bm O 0 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 From this it is seen that the number of 'O's in B is fourteen and the number of '1's in B is six. It will therefore be more efficient to use the expression (11) which in this case will generate seven sum terms which will be designated P1 to P7, respectively.
Evaluation of the first term on the right-hand side of the expression (11) gives:
P1 = A0.A1.A2.A3.A4.A5.A6.A7.A8.A9.A10.A11.A12.A13 .A14.A15.A16.A17.A18.A19. ...(12)
The second term on the right-hand side of the expression (11) is then evaluated for all values of k in B for which Bk=1, that is 4, 6, 8, 9, 14 and 15: k =4 P2 = A4 .A5.A6.A7.A8.A9.A10.A11.A12.A13.A14.A15.A16.A17.A18.A19.
...(13) .A5.A6.A7.A8.A9.A10.A11.A12.A13.A14.A15.A16.A17.A18.A19.
k = 6 P3 = A6 .A7.A8.A9.A10.A11.A12.A13.A14.A15.A16.A17.A18.A19.
...(14) k = 8 P4 = A8~A9~A10~A11~A12. A13.A14. A15.A16.A17.A18.A19.
...(15) ...(15) k =9 P5 = A9.A10.A11.A12.A13.A14.A15.A16.A17.A18.A19 ...(16)
k = 14
P6 = A14.A15.A16.A17.A18.A19. ...(17)
k = 15 ~~~ P7 = A15.A16.A17.A18.A19. ...(18)
The seven expressions (12) to (18) are then 'ORed' together and inverted to derive the required answer:
A # 50,000 = P1 + P2 + P3 + P4 + P5 + P6 + P7 (19)
The inversion is achieved by using the complementary output of the PAL device.
The above expressions (12) to (19) are all that are required to enable the PAL device to be programmed by blowing fuses in the manner well known to those skilled in the art.
A suitable PAL device which may be used in this embodiment is the 20C1 supplied by
Monolithic Memories Incorporated, and in this case the input bits Ao to A20 of the variable input word A are supplied to the pins 1 to 11, 13 to 17 and 20 to 23 respectively. The output at the pin 18 is high, that is '1', if A is greater than B, but otherwise is low, that is 'O'.
If the number of bits in the variable input word exceeds the number of input pins on available
PAL devices, then two or more PAL devices can be cascaded. In this case respective groups of bits of the variable input word are supplied to respective PAL devices, and the outputs of the
PAL devices are combined to give the required result. Alternatively, where the PAL device is required to evaluate more sum terms than is possible with a single pass through the PAL device, then the output of the PAL device can be fed back to the input for a second pass through the
PAL device.
In cases where it is required to determine whether a variable input number lies within a given range, then the expressions (8) and (9) can be used to evaluate in a single PAL device, or cascaded PAL devices, whether the input number is both greater than one fixed number and less than another fixed number, and hence lies within the required range.
Claims (6)
1. A method of comparing the value of an. input digital word, the value of which may vary, with the value of a fixed digital word, comprising the steps of:
programming a programmable array logic device in dependence on said fixed digital word so that, on supplying said input digital word to said programmable array logic device, the first most significant bit at which said input digital word and said fixed digital word differ are compared; and
in dependence on said comparison deriving an output signal which indicates whether or not the value of said input digital word exceeds the value of said fixed digital word.
2. A method according to claim 1 comprising the step of programming said programmable array logic device to evaluate either the expression:
for Bk = 0 or the expression:
for Bk = 1
where X signifies 'ANDing' of a sequence of terms and E; signifies 'ORing' of a sequence of terms, the expression used being selected in dependence on the number of 'O's in said fixed digital word.
3. A digital word comparator for comparing the value of an input digital word, the value of which may vary, with the value of a fixed digital word, the comparator comprising:
a programmable array logic device programmed in dependence on said fixed digital word so that, on supplying said input digital word to said programmable array logic device, the first most significant bit at which said input digital word and said fixed digital word differ are compared;
said device supplying an output signal in dependence on said comparison which output signal indicates whether or not the value of said input digital word exceeds the value of said fixed digital word.
4. A comparator according to claim 3 wherein said programmable array logic device is programmed to evaluate the expression:
for Bk = 0
where n signifies 'ANDing' of a sequence of terms and C signifies 'ORing' of a sequence of terms.
5. A comparator according to claim 3 wherein said programmable array logic device is programmed to evaluate the expression:
for Bk = 1 where K signifies 'ANDing' of a sequence of terms and Z signifies 'ORing' of a sequence of terms.
6. A comparator according to claim 3, claim 4 or claim 5 wherein said programmable array logic device is further programmed in dependence on a second fixed digital word and said output signal indicates whether or not the value of said input digital word lies within the range defined by said fixed digital word and said second fixed digital word.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8620446A GB2194365B (en) | 1986-08-22 | 1986-08-22 | Digital word comparison |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8620446A GB2194365B (en) | 1986-08-22 | 1986-08-22 | Digital word comparison |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8620446D0 GB8620446D0 (en) | 1986-10-01 |
| GB2194365A true GB2194365A (en) | 1988-03-02 |
| GB2194365B GB2194365B (en) | 1990-10-31 |
Family
ID=10603101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8620446A Expired - Lifetime GB2194365B (en) | 1986-08-22 | 1986-08-22 | Digital word comparison |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2194365B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1262866A1 (en) * | 2001-06-01 | 2002-12-04 | STMicroelectronics Limited | A method and circuitry for determining the validity of information |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB921725A (en) * | 1960-10-04 | 1963-03-20 | Atomic Energy Authority Uk | Improvements in or relating to comparison circuits for binary numbers |
| GB1108036A (en) * | 1964-04-22 | 1968-03-27 | Eastman Kodak Co | Comparator apparatus |
-
1986
- 1986-08-22 GB GB8620446A patent/GB2194365B/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB921725A (en) * | 1960-10-04 | 1963-03-20 | Atomic Energy Authority Uk | Improvements in or relating to comparison circuits for binary numbers |
| GB1108036A (en) * | 1964-04-22 | 1968-03-27 | Eastman Kodak Co | Comparator apparatus |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1262866A1 (en) * | 2001-06-01 | 2002-12-04 | STMicroelectronics Limited | A method and circuitry for determining the validity of information |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8620446D0 (en) | 1986-10-01 |
| GB2194365B (en) | 1990-10-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Effective date: 20060821 |