GB2193402A - Video decoder apparatus - Google Patents

Description

GB2193402A 1

SPECIFICATION of R,G,B, and 1, without loss of bandwidth.

The decoder may also provide an R,G,B,l TTL Color decoder apparatus type of video drive signal from a conventional type of black and white video signal. The de The present invention related to color decoder 70 coder includes means for receiving the grey apparatus and particularly to a color decoder scale digitally encoded color video input signal capable of providing an R,G,B,l TTL type of and restoring it into separate DC restored video drive signal from a grey scale encoded sync and grey scale encoded color video dis composite video signal, such as one play information. In the case of a digitally en transmitted over a single coaxial cable, irre- 75 coded color video signal input, white reference spective of whether the signal is a conven- level signals are dynamically provided from the tional black and white or digitally encoded co- sampled video information and are used in lor video signal. In the instance of reception of converting the grey scale digitally encoded co a digitally encoded color video signal over the lor video information to the TTL format cable, a dynamically sampled white reference 80 R,G,B,l type of video signal. Thus, the deco signal derived from the received video inforder converts the multilevel grey scale digitally mation is employed in the conversion process, encoded color video signal into a TTL format with this signal being replaced by a fixed type of R,G,B,l video drive signal by mapping white reference signal in the instance of re- the grey scale digitally encoded color video ception of a conventional black and white vi- 85 signal based on the reference level signal. In deo signal over the cable. this manner, a multilevel grey scale digitally Systems which convert between color encoded color video signal may be decoded video signals and grey scale video signals are to provide a TTL format R, G,B,l type of video known in the art, as are systems employing drive signal without loss of bandwidth.

digitally encoded video information, such as 90 In the instance when the received video sig disclosed, by way of example, in U.S. Patent nal is a conventional black and white signal, Nos. 4,233,601; 4,345,276; 4,437,093; then a fixed white reference level signal is 4,373,156; 4,232,311; 4,368,484; used in the conversion process in place of the 4,481,509; 4,481,594; 4,425,581 and dynamically sampled white reference signal 4,270,125. However, none of these prior art 95 level. In this instance, the two most sig systems known to applicants is readily nificant bits of a four bit grey scale encoded capable of use in systems where it is desired signal are used to determine the make-up of to inexpensively transmit color video informa- the TTL format for the resultant RGB type of tion great distances over single coaxial cables video drive signal since the two least signifi- to RGB type of monitors such as normally 100 cant bits provide too fine of a resolution to employed with computer displays, such as an have an impact on the coarse mapping used, IBM PC. Moreover, no such systems are with the most significant bit representing the known to applicants which also readily permit half point in the analog domain, for the refer received conventional black and white video ence signal and the next significant bit repre information to be displayed on the same RGB 105 senting the quarter point in the analog domain monitor as received digitally encoded color vi- for the reference signal, In defining the TTL deo information. Furthermore, in this regard, format for the R,G,B,l type of video drive sig applicants are not aware of any prior art color nal, four levels are preferably employed, full decoders or systems which employ a 16 level intensity white, which occurs when the en- grey scale code, i.e. 16 levels of grey to en- 110 coded pair of bits represents 75% of the ref code the video signal into 16 possible R,G,B,l erence signal level or a 1- 1 code, grey which color combinations, to provide the four R,G,B,l results when the encoded pair of bits repre color bits over a single coaxial cable with no sents a signal level within 50%-75% of the loss of bandwidth in an efficient and cost ef- reference signal level or a code of 1-0, low fective manner. These disadvantages of the 115 intensity white, which is a different shade of prior art are overcome by the present invengrey, which results when the encoded pair of tion. bits represents a signal level within 25% - The invention is broadly defined in claim 1 50% of the reference signal level or a code of of the claims of this specification. 0-1 and black, representing no R,G,B, which

The present invention relates to a decoder 120 occurs when the encoded pair of bits repre for providing an R, G, B, I TTL type of video sents a signal level within 0% - 25% of the drive signal from a grey scale encoded com- reference signal level or a code of 0-0. Thus, posite video input signal comprising sync in- the decoder converts the conventional black formation and digitally encoded displaya- and white video signal input into a TTL format ble information, in which the TTL format 125 type of R,G,B,l video drive signal by mapping R,G,B,l type of video signal may be provided the received reference level signal to bits from the grey scale encoded composite video representing the four previously defined inten signal, such as one comprising a code com- sity levels. In this manner, a conventional prising sixteen levels or shades of grey for black and white video signal may be decoded providing sixteen possible color combinations 130 to provide a TTL format R,G,B,l type of video 2 GB2193402A 2 drive signal without loss of bandwidth, with ventional black and white or color grey scale the conventional black and white video signal digitally encoded color video signal which is thus being displayable on the same RGB received by the decoder 200 via coaxial cable monitor as the aforementioned digitally en- 202 is provided to a differential line receiver coded color video signal. 70 and cable compensation and equalization net FIG. 1 is a functional block diagram of the work 10, shown in greater detail in the sche presently preferred embodiment of a color de- matic of FIG. 2, which DC restores the re coder apparatus in accordance with the pre- ceived video signal and preferably makes the sent invention; and frequency response of the cable flat. The out- FIG. 2, which comprises FIGS. 2A - 2C 75 put of this differential line receiver and cable taken together, is a logic schematic diagram compensation and equalization network 10 is corresponding to the functional block diagram preferably fed to a conventional sync stripper of FIGA. 20a to be described in greater detail herein FIGA shows a functional block diagram of after with reference to FIG. 2, which is prefer- the presently preferred embodiment of a color 80 ably clamped to do DC restoration, and there decoder, generally referred to by the reference after to a conventional horizontal and vertical numeral 200 which is capable of receiving sync separator 20b to provide the vertical, standard digitally encoded composite video Vs, and Hs, horizontal, sync signals. As will signals, containing either digitally encoded co- be explained with reference to FIG. 2, the lor or conventional black and white video insync stripper 20a and the sync separator 20b formation, transmitted over a single conven- preferably comprise a conventional type of tional coaxial cable, and converting these sig- adaptive sync stripper 20a, 20b, with the de nals into a TTL type of format such as for rived horizontal sync or Hs signal preferably use with a conventional RGB monitor so as to being used to create a clamp pulse, via a provide a display on the RGB monitor 107 90 differentiator network 30, as well as to drive irrespective of whether the input video infor- a white pulse gate 60, to be described in mation contained in the received signal was greater detail hereinafter, and to provide the color or black and white. As will be explained horizontal sync input to the RGB monitor 107.

in greater detail hereinafter, the decoder The derived vertical sync or Vs signal is also 200 requires only a single coaxial cable 95 fed to the white pulse gate 60 and provides for reception of the digitally encoded color or the vertical sync input to the RGB moni conventional black and whit ' e signals which it tor 107. As will be explained in greater detail receives and decodes for provision to a con- hereinafter with reference to FIG. 2, Vs is ventional RGB monitor 107 for display ther- slightly offset from Hs, such as by about 10 eon. In those instances when only a single 100 usec. due to integrator function, which factor coaxial cable is desired or available, such as is preferably used in the decoder 200 of the at installations employed at brokerage houses present invention to locate the full scale sam or stock exchanges using RGB monitors, the ple which is preferably found at the next Hs savings realized by the present invention can or next line after the falling edge of Vs is become significant such as through the elimi- 105 detected.

nation of cross point switching at a video The clamp pulse which is derived from Hs switch. via differentiator 30 is preferably fed to a The present decoder receives a color video clamp network 40 which provides DC restora signal which contains the video information in tion of the video signal to be recovered from a code comprising sixteen levels of grey, 110 the received composite video signal provided termed a grey scale code herein, which is to network 40 from network 10.

used to transmit four RGB colour bits, and The output of clamp network 40 is prefera with a seventeenth level or additional bit bly fed to a buffer 50 which preferably con representing sync information. It is this verts the high impedance output of network transmitted color digitally encoded input sig- 115 40 into a low impedance DC restored signal nal, or conventional black and white video sig- input to an analog to digital flash converter nal, which the presently preferred color de- 100, which is preferably a discrete flash con coder 200 receives over the single coaxial verter, such as illustrated in FIG. 2C, employ cable 202 and deco - des into the four color ing comparators and conventional universal bits, R, G, B and 1, required to drive the con- 120 priority encoders, such as a Fairchild ventional RGB monitor 107. Thus, sixteen F100165, and which, as previously men shades or levels of grey are preferably used tioned, receives the black and white adjust to transmit the four RGB color bits, effectively signal, such as from white adjust 90, to ad enabling the required TTL format type of just the linearity of the converter 100. Flash information required for an RGB monitor 107 125 converter 100, as shown and preferred in FIG.

to be transmitted over great distances over a 2C, also preferably includes black level adjust single coaxial cable 202 without the need for network 109 which provides black level adjust cross point switching, as will be explained in which, as will be described in greater detail greater detail hereinafter. hereinafter, preferably adjusts the window for As shown and preferred in FIG. 1, the con- 130 the resultant analog video signal in the analog 3 GB2193402A 3 to digital flash converter 100 by preferably signal is not sync. Comparator 43, on the moving the black reference 1/2 LSB up other hand, strips sync from the video signal while white level adjust preferably moves the to provide sync to integrator 47-53, with the white reference 1/2 LSB down, thereby allow- stripping preferably occurring at blanking and ing adjustment for maximum linearity in the 70 with a DC value such as D volts output across converter 100. The buffered DC restored sig- resistor 67 being equivalent to blanking. Feed nal output of buffer 50 is also preferably fed back loop 41 also preferably includes a charge to a white sample and hold 70 which is con- pump diode 69 to charge capacitor 49.

trolled by the output of the white pulse gate As shown and preferred in FIG. 2, the sync 60. The output of the white sample and hold 75 tip is preferably DC restored to 0 volts essen network 70 is a white reference signal which tially by diodes 71, 73, with R-C network 75 is preferably fed to a color/black and white 77 acting as a low pass filter to remove detect network 80a, 80b as well as to a noise from the received video signal, and buffer switch 82, which also receives a fixed it is this signal, with the sync tip DC restored black and white reference voltage 84. The 80 to 0 volts, which is applied to input 79 of white reference output of the buffer switch 82 comparator 43. A divide-by- two voltage di is fed to white adjust network 90 which, in vider network comprising resistors 67 and 81 turn, provides the white adjust signal to the is preferably provided and ensures that the flash converter 100 which takes the two ref- voltage at point 83 is always 50% of sync erence signals Vref and + Vref and pro- 85 regardless of the signal amplitude. Another vides the aforementioned four bit linear code voltage comparator 85 is preferably provided output to a level translator 104. The four bit which, like comparator 43, strips sync from linear output of the level translator is fed to a the video signal. As shown and preferred in black and white color switch 106 whose out- FIG. 2, one input to comparator 85 is the put is, in turn, fed to the RGB monitor 107 as 90 voltage at point 83 while the other input is the R,G,B and I signals, by way of example. from low pass filter 75-77. The resultant sync Referring now to FIG. 2 as a whole, the stripped by comparator 85 is the broadcast schematic diagram shown therein is essentially composite sync used by the decoder 200, self explanatory; however, various aspects with an integrator comprising resistors 87 and thereof shall be described in greater detail to 95 89 and capacitors 91 and 93 conventionally enhance the understanding of the invention separating vertical sync Vs from the compo herein. site sync output of comparator 85. The verti The differential line receiver and cable com- cal sync Vs, however, is normally serated pensation and equalization network 10 is con- and, therefore, the serations are preferably re ventional and can be readily understood by 100 moved from the Vs output of comparator 65 reference to FIG, 2 without further explanation, by means of OR gate 95, whose other input with exemplary values for the various compo- is the broadcast composite sync output of nents of the network 10 being indicated in comparator 85, with the OR gate 95 prefera FIG. 2. Suffice it to say that cable compensa- bly removing the serations during the vertical tion and equalization is conventionally ob- 105 interval. The horizontal sync signal Hs is pro tained via the R-C ladder network 11. With vided through OR gate 95. Thus, the adaptive respect to the conventional type of adaptive sync stripper 20a, 20b preferably tracks the sync stripper 20a, 20b preferably employed in signal level.

the color decoder 200 of the present inven- Before discussing clamp network 40 in tion, a self-correcting feedback loop 41 com- 110 greater detail, it should be noted that prefera prising conventional voltage comparators 43 bly differentiator 30 provides a predetermined and 45, such as LM 339 comparators, capack pulse, such as 1.5 psec on the back porch, tors 47 and 48 and-resistors 51, 53, and 55 which is used to create the clamp pulse for is preferably employed. Resistor 53 and capa- network 40, with differentiator 30 preferably citor 47 comprise an integrator which inte- 115 comprising resistors 97, 98 and capacitor grates the sync signal to provide the duty cy- 101. The clamping network 40 prefera cle to comparator 45 which compares the bly includes a pair of FET's 105, 107 clamped duty cycle from the sync signal against the to ground. FET 105 is a level shifter which reference voltage which is applied to input 57 preferably swings between a predetermined from a voltage divider network comprising re- 120 value, such as + 12v and ground. When the sistors 59, 61 and 63, which is also con- gate 105g of FET 105 goes negative during nected to one input of another voltage com- the back porch, FET 105 is turned off and parator 65 whose output is Vs. Resistor 55 is FET 107 is turned on, putting the DC restora the charge resistor for capacitor 49 in feed- tion voltage into capacitor 113 and clamping it back loop 41. In comparing the duty cycle 125 at that value. Alternatively, when the gate from sync with the reference voltage at the 105g of FET 105 goes positive, FET 105 is input 57, comparator 45 is preferably looking turned on to ground which turns FET 107 off.

for the duty cycle to be greater than 20% The black level for the flash converter 100 which indicates that it is greater than the duty is provided by black adjust potentiometer 109 cycle of sync and, therefore, indicates that the 130 which is located at the - Vref input to flash 4 GB2193402A 4 converter 100 and adjusts the reference for black and white reference voltage network 84 the flash converter 100 by setting the black preferably comprises, by way of example, a level. With respect to the determination of diode 131 and a pair of resistors 133-135.

white level, this occurs as follows. As shown, The operation of the decoder 200 in black and preferred in FIG. 2, the white pulse gate 70 and white or color detection is as follows. By preferably comprises a pair of flip flops way of example, a white sample is set at and 117 and a pair of one shots 119 detecting a voltage value of approximately 1.5 and 121, with flip-flops 115 and 117 prefera- volts, 0.5 volts is set as the black color de bly being JK flip flops, by way of example. On tect level and below about 0.5 volts is set as the falling edge of Vs, which is supplied as 75 the black detect level. Thus, if the voltage at the clock pulse to flip flop 115, flip flop 115 input 137 to detector 80b is 1.5 volts in the is clocked. This preferably releases the clear above example, then color is detected and if it on flip-flop 117 allowing it to be clocked at is less than 0.5 volts, black and white is de the next Hs which is the clock pulse to flip- tected. In this regard, buffer 80a works as a flop 117. As was previously mentioned, Vs is 80 voltage follower from sample and hold net slightly offset from Hs, such as by about 10,u work 70 to feed input 137 of detector 80b see, due to the integrator function, The next which is preferably a straight voltage compara Hs to flip-flop 117 is the next line which, tor which compares the voltage produced by therefore, indicates that you are in the second resistor voltage divider pair 139-141, con horizontal scan line, which is where a full 85 nected to the other input 143, with the output scale sample is located, When flip-flop 117 is of the sample and hold network 70.

on, this triggers one-shot 119 which provides If black and white is the level detected by a trigger pulse, such as preferably 1.5 comparator 80b, then the white reference pro usec. by way of example, which puts it past vided via path 76 preferably feeds the flash the back porch. It should be noted that no 90 converter 100 upper reference from switch sample and hold function is possible during 82b-82c. If no color flag is detected, the sam the back porch since it is at 0 volts. One shot ple on capacitor 145 is at 0 volts and the 119, in turn, triggers one shot 121 which switch 82b-82c is at 0 volts. This being the generates a sample pulse for a predetermined case, the signal on path 74 is low creating a sample interval, such as 28 psec. by way 95 voltage at point 78, to the base of transistor of example, which sample pulse is preferably 82c of switch 82b-82c, which is the black low during the sample time with the sample and white reference. Transistor 82c then pulse preferably releasing & clear on flip-flop acts as a voltage follower for the white refer and resetting the flip-flop 115. ence. When transistor 82b is on, transistor The white sample and hold network 70, as 100 82c preferably blocks the signal from going shown and preferred in FIG. 2, preferably through it, with the reverse being true when comprises a pair of FETs 123-125 and a transistor 82c is on.

capacitor 127 which charges to provide a Vol- If, on the other hand, color is the level de tage which represents the white reference tected by comparator 80b, then diode 147 level for converter 100. When the gate 123g 105 goes high which turns off transistor 82c. Vol of FET 123 is positive, FET 123 is preferably tage follower 82a and emitter follower 82b turned on and FET 123 conducts to ground now represent the white reference voltage.

thereby turning FET 125 off. Alternatively, Transistor 82c preferably blocks this voltage when the gate 123g- of FET 123 goes nega- and the output of voltage follower 82a-emit tive, FET 123 is turned off and FET 125 turns 110 ter follower 82b is applied to path 76 as the on allowing capacitor 127 to charge, thereby white reference which is applied to the upper creating a sample and hold which is current reference of flash converter 100 instead of buffered by a conventional voltage follower the fixed voltage black and white reference 82a, with the sample voltage then present at output from network 84. It should be noted point 129 representing the white reference 115 that if a color flag were present, then there level. As shown and preferred, the reference would be approximately 1.5 volts in capacitor voltage is applied during the sample and hold 145 and color would be detected. Thus, in time. The white reference, as was previously the instance of reception of a multilevel grey mentioned, is provided through a switch 82b, scale digitally encoded color video signal over 82c which is preferably formed from an emitcable 202, a dynamically sampled white refer ter follower transistor 82b and another tran- ence signal derived from the received sync sistor 82c, and the white adjust potentiometer information is passed to converter 100, while 90, to the flash converter 100. in the instance of reception of a conventional With respect to the black and white and black and white video signal over cable 202, color detect network 80a, 80b, this 125 this dynamically sampled white reference sig preferably includes buffer 80a, and detector nal is replaced by the fixed black and white 80b, with the conventional level translator 104 reference signal from source 84.

which preferably translates ECL to TTL, also The black and white/color switch 106, technically being part of the detection function which preferably provides the standard TTL as will be described hereinafter. The fixed 130 R,G,B,l signals employed in the conventional GB2193402A 5 RGB monitor 107, operates as follows. The black. Thus 1-1 preferably represents full switch 106 is preferably a conventional tris- white and translates to an output of 1-1-1-1, tate buffer with two enable inputs 151, 1-0 preferably represents one shade of grey 153, such as an ILS 244, in which when one and translates an output of 1- 0-0-0, 0-1 pre enable is on the other is off and vice versa. 70 ferably represents a second shade of grey, or Assuming for purposes of explanation, that- low intensity white and translates to an output Vref. is always equal to 0, when enable input of 0-1-1-1, and 0-0 preferably represents 151 is on, preferably the four conventional black and translates to an output of 0-0-0-0.

RGB color bits, R,G,B, and 1, are passed di- The operation of the presently preferred dis- z 10 rectly through switch 106, and when enable 75 crete A/D flash converter 100 is described input 153 is on, preferably a mapping of the with reference to FIG. 2C. As shown transmitted conventional black and white video and preferred in FIG. 2C, eight conventional signal occurs. In mapping the transmitted con- dual comparators 300, 302, 304, 306, 308, ventional black and white video signal, prefer- 310, 312 and 314, respectively, such as AM ably the most significant bit or MSB repre- 80 6687 dual comparators, are provided for the sents the half point in the analog domain, the 16 level grey scale code, with each one of next bit or NSB represents the quarter point in the 16 comparator stages preferably being the analog domain, and the two least signifi- provided with an input voltage 1/16 higher cant bits are ignored since these bits provide than the input voltage of the immediately pretoo fine a resolution to have an impact on the 85 ceding comparator stage through a ladder net coarse mapping used for black and white. work 319. The comparators 300- 314, inclu When black and white switch 106 is in the sive respectively, preferably feed a pair of color mode, the bits flow straight through conventional universal priority encoders 316, switch 106, with I being the most significant 318 such as the aforementioned Fairchild bit and B or blue being the least significant 90 F100165 Universal Priority Encoders, which bit. In this regard, it should be noted that B or provide a 4 bit linear code output to the level blue has the lowest perceived luminance level, translator 104. In the example of FIG. 2C, the R or red is the next highest, then G or green, highest order in the ladder network 319 is and I or intensity is the brightest of all three. preferably comparator 300 and the lowest or When black and white is detected by switch 95 der is comparator 314. As the analog input 106, the bits are preferably shifted to build voltage +Vref and -Vref through the ladder windows that will result in four levels com- network 319 goes above the ladder network prising two shades of grey, black, and white, 319 input to the comparators 302-314, inclu with the most significant bit coming on at the sive, Q preferably goes high, thereby creating 50% level, halfway up the scale, and the other 100 a 16 level thermometer code which is fed to bits come on at various other points as will the priority encoder network 316, 318. As be explained hereinafter. The most significant shown and preferred in FIG. 2C, the priority bit coming on maps to the I bit going out encoders 316, 318 only provide three of the from switch 106; i.e., when the 50% level is four bits of the 4 bit linear code output with achieved, you get an intensity out. In 105 the fourth bit preferably coming from the this regard, a code R,G,B, with 1, that is with eighth comparator stage, which, in the above all four of the output bits of switch 106 on, example, is the lower half of comparator 306.

preferably represents full intensity white which This stage determines which priority encoder is achieved whenever 75% of +Vref is ex- 316 or 318 is active, with an output enable ceeded. When in the range of 50%-75% of 110 preferably being provided to encoder 318 if Vref., an RGB code is preferably put out you are in the lower half of the 16 level ther which represents one of the two shades of mometer code and with an output enable, in grey, with just the I output bit of switch 106 stead, preferably being provided to encoder on. When in the rar1ge of 25%-50% of Vref, 316 if you are in the upper half of the an RGS code is preferably put out which 115 16 level thermometer code. Of course, if de represents the other of the two shades of sired, a clocked A/D flash converter, such as grey, with just the R,G,B, output bits on and a Siemens SDA8018 driven by a conventional the I output bit off of switch 106. Finally, two phase clock could be substituted for the -w hen in the range o f 0-25%, no R,G,B, or I presently preferred discrete flash converter output bit of switch 106 is put out and it 120 100 without departing from the spirit and represents black. Thus, the two most signifi- scope of the present invention.

cant bits provided to switch 106 from level Consequently, by employing the decoder translator 104, and flash converter 100 are 200, a video signal transmitted over a single the control bits for switch 106 for providing a coaxial cable in the form of a conventional four level signal. When these two bits are on, 125 black and white video signal or a digitally en- then 75% of the analog voltage or full scale coded 16 level grey code color video signal white is preferably provided; when either one may be converted to the four conventional of these bits is on and the other off,it is RGB bits, without loss of bandwidth, and used preferably one of two shades of grey, and to drive a conventional RGB monitor irrespec- when both of these bits are off it is preferably 130 tive of whether the input is a digitally encoded 6 GB2193402A 6 color video signal or a conventional black and teen level code for providing sixteen possible white video signal. This is accomplished while color combinations of R, G, B, and 1.

enabling conventional composite video signals 5. A decoder as claimed in any one of to be converted to TTL format to drive a claims 1 to 4 wherein said mapping means standard RGB monitor, such as normally em- 70 comprises means for mapping said Con ployed with an IBM PC. ventional black and white video signal as a 1 1 logic condition of said pair of bits and pro

Claims (4)

CLAIMS viding a R, G, B, I TTL type of video drive

1. A decoder apparatus for providing an signal code corresponding to said full intensity R,G,B,l video drive signal from a conventional 75 white based thereon, a 0-0 logic condition of black and white video signal or a digitally en- said pair of bits and providing a, R, G, B, I coded multilevel grey scale color video input TTL type of video drive signal corresponding signal comprising sync information and displa- to said black based thereon, a 1-0 logic Con yable information, said decoder comprising dition of said pair of bits and providing a, R, means for receiving said black and white 80 G, B, I TTL type of video drive signal corre and digitally encoded multilevel grey scale co- sponding to said grey, or a 0-1 logic condition lor video input signal and restoring it into se- of said pair of bits and providing an R, G, B, I parate DC restored sync and black and white TTL type of video drive signal corresponding or color video display information; to said low intensity white based thereon.

means for providing separate white refer- 85 6. A decoder as claimed in any one of ence level signals; and claims 1 to 5 wherein said pair of bits repre- means operatively connected to said white sent the two most significant bits of a four bit reference level signal providing means and to code.

said signal restoring means for converting said 7. A decoder as claimed in any one of video display information into an R,G,B,l TTL 90 claims 1 to 6 wherein the most significant bit type of video drive signal, said converting of said pair of bits represents the half point in means comprising means for detecting the analog domain for said white reference whether said received video display informa- signal and said next most significant bit repre tion is digitally encoded color or conventional sents the quarter point in the analog domain black and white based on a predetermined 95 for said white reference signal.

signal level decoded from said received video 8. A decoder as claimed in any one of input signal, and means for mapping said re- claims 1 to 7 wherein said R, G, B, I TTL stored video display information based on said type of video drive signal providing means white reference level signal, said mapping comprises means for providing said R, G, means comprising means for mapping said de- 100 B, I TTL type of video drive signal corre tected conventional black and white video sig- sponding to said full intensity white when said nal for providing said R,G,B,l TTL type of viencoded pair of bits represents 75% of said deo drive signal based thereon, said mapped white reference signal level, corresponding to black and white video signal comprising a pair said grey when said encoded pair of bits of bits logically representing full intensity 105 represents a signal level within 50%-75% of white, grey, low intensity white or black said white reference signal level, correspond based on a predetermined percentage of said ing to said low intensity white when said en white reference level signal; whereby a com- coded pair of bits represents a signal level posite video signal may be decoded to pro- within 25%-50% of said white reference signal vide a TTL format R, G, B, I type of video 110 level, and corresponding to black and repre drive signal without loss of bandwidth. senting no R, G, B, I when said encoded pair

2. A decoder as claimed is claim 1 wherein of bits represents a signal level within 0% said means for providing said white reference 25% of said white reference signal level.

level signal comprises means for sampling said 9. A decoder as claimed in any one of restored sync information for dynamically pro- 115 claims 1 to 8 further comprising means for viding said white reference level signal there- providing a fixed white reference signal to said from. converting means as said reference voltage

3. A decoder as cl ' aimed in claim 1 wherein when said black and white'display information saia multilevel digitally encoded color video is detected as having been received, said Con- ' signal is obtained from an initial R, G, B, 1 120 verting means providing said R, G, B, I TTL color video signal, said multilevel digitally en- type of video drive signals from said black coded color video signal being based on per- and white video display information.

ceived luminance levels in said initial R, G, B, 1 10. Decoder apparatus substantially as color video signal, said converting means herein described with reference to and as illus comprising means for recovering said initial R, 125 trated in the accompanying drawings.

G, B, I color video signal from said multilevel Published 1988 at The Patent Office, State House, 66/71 HighHolborn, digitally encoded color video signal. London WC 1 R 4TP. Further copies may be obtained from

4. A decoder as claimed in any one of The Patent Office, Sales Branch, St Mary Cray, Orpington, Kent BF15 3RD.

claims 1 to 3 wherein said digitally encoded Printed by Burgess & Son (Abingdon) Ltd. Con. 1/87.

grey scale color video signal comprises a six-