GB2191920A

GB2191920A - Memory address system

Info

Publication number: GB2191920A
Application number: GB08615206A
Authority: GB
Inventors: Michael Alan Williams
Original assignee: GEC Avionics Ltd
Current assignee: Allard Way Holdings Ltd
Priority date: 1986-06-21
Filing date: 1986-06-21
Publication date: 1987-12-23
Also published as: GB8615206D0

Abstract

In a system for accessing a smaller reference region 2 within a larger image store 1, an address generator looks at each address in turn according to clock pulses. Data representative of the start address 5 of the region and the number of elements between the end of one line and the beginning of the subsequent line of the region is used to skip points in the store which lie outside the desired region. Hence, processing time is decreased since clock pulses are not wasted while unwanted data is processed. <IMAGE>

Description

SPECIFICATION Memory address system This invention relates to a memory address system and method. In particular, it relates to the sequential access of a small portion of a large frame-store memory array. Such access is required during a correlation process where a reference store is compared with its corresponding position in the memory array. The memory arrays to which the invention is particularly directed are those which store single frames of a video image.

In a typical frame store, the address generated for access of a memory array comes either from a host computer or from counters.

The host computer generates the address during slow speed processing and the counters generate the address in a high speed process during output to a TV monitor. Memory array access is only available in such systems in a sequential manner.

In a correlation or comparison type of process an image is scanned and stored in a memory array. When a target in a video image is found, a reference window is set up around it. The target is tracked during subsequent fields of the image by comparing the previously stored reference with each possible position of the reference in the new field, and moving the window to the position of best correlation. Hence every possible position of the small reference store within the larger frame store needs to be compared.

Previous memory addressing systems for use in correlation processes are limited in the size or resolution of the image which can be processed and tend to be slow. The present invention provides a system which speeds up processing and allows an image of greater size or resolution to be processed.

According to the present invention, there is provided a method for addressing a selected desired region of an image stored in a frame store memory array in which array elements are sequentially addressed, and wherein data defining the position, size and shape of the region within the memory array is used so that points in the array which lie outside the desired region are skipped during the addressing process.

The data used may for instance be the start address of the region and the number of elements between the end of each line and the beginning of each subsequent line of the region.

The invention further provides a memory address system for addressing elements of a frame store memory array used to store sequential data representative of a frame of an image, including an address generator adapted to sequentially generate addresses within the memory array and programmable control means used to control the address generator such that only memory elements corresponding to a desired region of the image are addressed, the control means being adapted to use programmed data to control the address generator to skip memory elements corresponding to parts of the image which lie outside the desired region.

In preferred embodiments, the invention is performed by multiplexing three inputs to an accumulator, the inputs being a) a "1", b) the "skip length" which is for example the number of pixels between positions 3 and 4 in figure 1, and c) the "start address" of the next correlation position for the reference store. The start address values may be generated by look up tables and inputs a), b) and c) are multiplexed into the accumulator in a manner which is further described below. The output from the accumulator is used to determine the current memory element addressed by the system.

Figure 1 of the accompanying drawings shows one typical position for a smaller reference store memory array 2 within a frame store memory array 1. Typically, in systems embodying the invention, the frame store will be 48x48 pixels and the reference store may be 8x8 pixels although the frame store could be larger than this.

In prior art systems, for each po'ssible position of the reference store, each pixel in turn is examined at a speed determined by a clock frequency. This method of access makes the processing system wait without performing a useful function, while it is counting between the last pixel in the first line of the reference store 3 to the first pixel in the second line of the reference store 4 and so on at the end of each line of the reference store, for a period equal to n clock cycles where n = (frame store width-reference store width) for every line of the corresponding position. Since the comparison process needs to be repeated for every possible position of the reference store within the frame store this can lead to a great deal of time being wasted to process a given frame store image.In the example given, with a frame store of 48 x 48 pixels and a reference store of 8x8 pixels the time wasted between positions 3 and 4 in figure 1 is 40 clock cycles. This occurs eight times for each correlation position and there are 41 x41 possible correlation positions of the reference store within the frame store. Hence the total time required to process one frame of the image is (41 x41 x8 > c(8+40)) = 645504 clock cycles. Given typically a 10MHz clock, the correlation time for one frame is 64.55ms which is equivalent to a processing rate of 15.5Hz. This rate is intolerable, however, since the new frames of image information arrive at a rate of 25Hz and hence more time is required to process each stored frame than it takes to receive the next frame.Prior systems are therefore severely limited in the im age size and resolution they are capable of processing.

By utilising the present invention, however, time is not wasted between sequential lines of the frame store, and processing can be achieved much quicker. i.e, in the example given, without the 40 cycle waste between for example positions 3 and 4 the total time spent processing a frame is (41 x41 x8 > c8)=107584 clock cycles. For a 10MHz clock this gives a correlation time of 10.78ms i.e, a processing rate of 92Hz. This time is well within the input frame rate and hence represents a substantial improvement over previous systems.

an embodiment of the invention will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1 shows schematically an image frame and one possible position of the reference frame within it.

Figure 2 shows apparatus adapted for use with the method of the invention and Figure 3 is a flow diagram for the operation of the apparatus of Figure 2.

Referring to Figure 2, memory addressing apparatus includes an accumulator 7 having an input from a multiplexer 8. Multiplexer 8 has three inputs 9, 10 and 11 representative of respectively the value "1" the "skip length" and the "start address" of the next correlation position. The start address values are stored sequentially in a look up table 12 which contains all the possible start positions 5 of the reference store 2 within the frame image 1. The output from accumulator 7 is representative of an address in the frame store 1, and may be applied to further processing or correlation circuits in which comparisons are made with a reference store.

The sequence of events of the method of the invention may be conveniently controlled by a microprocessor or other controlling means and is shown in flow diagram form in Figure 3. When an entire image frame 1 has been stored in memory the first start address for a reference image 2 within the frame 1 is fetched from the look up table 12. This may be for example pixel 5 shown on figure 1, although of course the first correlation position in any frame will have a start address at position 13. Accumulator 7 is then cleared and the start address 11 accumulated in. The image processing apparatus will therefore begin to look at address 5 on Figure 1, The accumulator 7 subsequently accumulates "1"s via the multiplexer until the end of the first line, position 3 is reached.A microprocessor (not shown) may be programmed with the line length of the reference store and provide a suitable signal at the end of the line for the multiplexer 2 to allow the skip length to be accumulated in. The address accessed by the equipment at the next clock cycle will therefore be address 4, all the pixel positions between 3 and 4 having been skipped.

The accumulator then begins to accumulate "ones" again until the end of the second line is reached whereupon the skip length 10 is accumulated in again and so on until the end of the last line is reached, position 6 on Figure 1. When the end of the last line has been detected, the next start address 11 is fetched from look-up table 12 and the cycle is repeated beginning from the new start address.

This process may then be repeated until every possible position of the reference store 2 within the frame store 1 has been correlated.

Claims

1. A method for addressing a selected desired region of an image stored in a frame store memory array in which array elements are sequentially addressed, and wherein data defining the position, size and shape of the region within the memory array is used so that points in the array which lie outside the desired region are skipped during the addressing process.

2. A method as claimed in claim 1 wherein the data is representative of the start address of the region and the number of elements between the end of each line and the beginning of each subsequent line of the region.

3. A method as claimed in claim 1 or 2 wherein the image is a frame of a scanned image and the selected region is a smaller region within the frame.

4. A method as claimed in any of the preceding claims wherein memory elements are addressed at a rate determined by regular clock pulses and, when the array element corresponding to the end of one line of the region has been reached, generation of the next clock pulse causes addressing of the array element corresponding to the beginning of the next line of the image.

5. A memory address system for addressing elements of a frame store memory array used to store sequential data representative of a frame of an image, including an address generator adapted to sequentially generate addresses within the memory array and programmable control means used to control the address generator such that only memory elements corresponding to a desired region of the image are addressed, the control means being adapted to use programmed data to control the address generator to skip memory elements corresponding to parts of the image which lie outside the desired region.

6. A system as claimed in claim 5 wherein the control means includes a multiplexor adapted to receive a plurality of inputs representative of (a) the start address of the desired region, (b) the number of memory elements between the end of one line and the beginning of the subsequent line of the region and (c) the value "one"; and to provide an appropriate output to the address generator depending on the current address being generated, the address generator thereby adding the value from the multiplexor to the current value to obtain a new address.

7. A system as claimed in claim 6 including a clock pulse generator and wherein the multiplexor provides an output each time a clock pulse is generated.

8. A system as claimed in any of claims 5 to 7 wherein the control means includes a microprocessor.

9. A memory address system as claimed in any of claims 5 to 8 wherein the image frame size is of a x b pixels and the desired region is any region within the image frame of c x d pixels where c and d are smaller than respectively a and b and wherein the control means is adapted to control the address generator to generate sequentially the addresses of each possible position of the smaller region within the larger one and is programmed to detect when the address of the last pixel of the region in one position is generated and to control the address generator to subsequently address the first pixel of the next position of the desired region, where the region is scanned through the image frame in a raster fashion.

10. A memory system substantially as hereinbefore described with reference to, and as illustrated by the accompanying drawings.

11. A method for addressing a memory store as claimed in claim 1 and substantially as hereinbefore described.

12. A correlation tracker including apparatus as claimed in any of claims 5 to 10.