GB2185170A - Tone detector - Google Patents

Abstract

A signal tone is detected and validated by counting the number of cycles of signal waveform in a set period and repeating the process a number of times, the signal being deemed valid if it produces an appropriate count in a sufficient number of tests. A count is appropriate in any test if it falls within an expected range which for a signal tone of 2700 Hz can be selectively set at +/-25Hz or +/-50Hz.

Description

SPECIFICATION Testing telephone lines This invention relates to testing telephone lines, to a device responsive automatically to atesttone received from the remote line end to provide e.g. a loop back condition for line testing, and to a method and device forvalidating a signal tone and responding thereto.

It is useful to be able to test a telephone line re motelyfrom telephone exchange in response to e.g. a subscriber complaint, before despatching an engineerto check the line orthe subscriber equip- ment. With the increase in the amount of equipment being connected to a telephone line at the subscriber's premises, there is clearly going to be an increase in the number offaults reported, and many of these may be due to the subscriber's equipment.If this is not purchased or leased from the telephone operating company such as BritishTelecom in the UK, then the operating company will only need to ensurethe leased telephone line is functioning normally and to distinguish between a faulty line and faultyequipmentforwhichtheoperating company may not be responsible.

It is an object of the present invention to provide a reliable remote line testing device which can be triggered remotely to provide e.g. a loop backcondi- tion so thatthe performance of the line itself can be checked from the exchange.

It is a further object of the present invention to provide a method and device for validating a signal tone received from a telephone line and responding to a valid signal.

According to the present invention there is provided a method for testing that a command signal has a predetermined frequency and persists for a predetermined duration, comprising the steps of selecting the command signal, shaping the selected command signal, and counting the oscillations ofthe shaped command signal a known numberoftimes, and generating an output signal representative of a valid signal when the selected signal is of the predetermined frequency and duration for each count.

According to the present invention there is also provided a device for testing that a signal has a predeterminedfrequencyand persistsfora pred etermined duration, comprising a filter for selecting thesignal,ashapingcircuitforshapingthesignal, and a bounded frequency counter for counting the shaped signal oscillations and whose operation is recycled a known number of times, and wherein the known number is representative of a positive test result.

According to the present invention there is further provided a device for validating a test tone signal comprising an input trigger circuit for receiving the signal, a first counter for counting the output ofthe trigger circuit, a time base qircuitfor periodically gat- ing the counter input, a decpderfor decoding the counter output over the gated periods, a reset circuit responsive to the decoded outputto resetthecoun- ter in the event the frequency of the received signal is notwithin predeterm ined to lera nces, and a second counter responsive to counting a predetermined number of successful periodic operations of the first counter to enable a response circuit representative of a va lid test tone sig nai received.

According to the present invention there is still further provided a circuitfor establjshing thata single tone exists for a finite time, wherein the tone oscillations are counted by a bounded frequency counter whose operation is recycled a known number oftimes, and if each operation is successful said known number of times an output signal ises- tablished representative of a valid tone received.

In orderthatthe invention can be clearly understood reference will now be made to the accompanying drawings which is a block diagram of a remote linetestertransponder according to an embodiment ofthe invention.

It is intended that the remote lina tester should respond to a signal tone sent from the exchange having a preset frequency and a preset minimum duration and so the tester has to recognisethis signal and onlythis signal to provide in one example a loop back connection between the receive and transmit pairs of a four-wire pair conventional telephone line.

It must not of course interfere with the normal usage of the line.

Referring to the drawings the testercomprises three sections, namely the manual and auto loop circuits 1, the common tone interface circuits 2 and the command tone processor 3 which in this embodimenu is realised in integrated circuitform.

There are in this embodiment two modes of oper ation,onefor2-wireandonefor4-wire.Themodes ofthe operation are separate and preset. In essence one mode of operation is latched and requirescom- mand tones (both the same) to (a) operate and (b) release the looping action (4-wire). In the other case the system is timed, requiring only one command to initiate looping, the unit restoring to the unlooped condition after a finite time has elapsed. In this timed mode an 800 Hz tone is emitted.

For the two modes of operation it is presently a requirement that the latched mode is used with 4wire circuits and the timed mode on 2-wire circuits.

This is not however two be regarded as a limitation on future use.

The loop circuit 1 comprises a manual circuit 10 which includes a "U" shaped link plug arranged so that it can be manually positioned to loop eitherthe serving exchange orthe customer's apparatus via an attenuator; in this example a 5 dB attenuator.

The automatic loop circuit is provided by reed re lays 1 la and 11 b driven fromthedecoded command tone of 2700 Hz transmitted from the serving exchange via the 4-wire receive line Rx. The other sides of the loop circuits extend to the equipmentter- minals Rx (EQUIP) and Tx (EQUIP). This also connects a 5 dB attenuator.

In the 4-wire receive line Rx is a line tranformer TRANS. The command tone interface circuit operates in conjunction with the balanced linetrans- former TRANS which has windings in series with the transmission path and also a furthersuitably-phased winding.which together with a balanced inputvoltageamplifier 12 (input buffer) and summing/limiter amplifier ? 3 are arranged that irrespectively of whether the customers' apparatus presents: (i) ltscorrectterminating impedance, (ii) an open circuit, (iii) a short circuit, then a substantially constant voltage is obtained in the summing amplifier 13. Hence tester operation is ensured under all customer conditions inclusive of a fault.

The interface circuits operate in dependence upon the principles employed in the line transformer. For an understanding ofthecircuitryconsiderthevol tages/currents in the transformerwindings during the three customer operation states mentioned above.

(i) Fora correct termination a given currentflows in the series line windings which therefore induces a known voltage in the suitably phased secondary windings. Also a known voltage appears across the customer termination which is sensed by the dif ferential input buffer 12. The results of these two signal paths are dealtwith in the summing amplifier 13 in a fixed ratio. This ratio is so chosen to preserve a given summed voltage for the othertime states mentioned above.

(ii) Forthe open circuit case no currentflows in the series windings and hence no voltage is induced in the secondaryofthe transformer butthe load vol tageofthefirstcase is doubled.

(iii) In the closed circuit case the current in the serieswindings and hence the voltage induced in the transformer secondary is doubled w.r.t. the firstcase but here there is no voltage input in the differential amplifier.

The overall mechanism is such that in the three cases a reasonably constant voltage is derived at the inputtothesumming amplifier 13.

The summing amplifer 13 is also configured as a limiterto provide approximately constant drive to the processor.

Noise immunity is enhanced by the inclusion of a single amplifier bandpassfilter 14 centred at 2700Hz.

The signal from the interface circuit2 is fed to a com mand tone processor3. Thjs circuit is realised as a semi-custom integrated device using low power technology. The principle is that of a sampling frequ ency counter with progranlmed bounds. The whole process is controlled bya highly stable crystal oscil lator2i with a masterfrequency of 4096 kHz.

Operation in latchedmode The inputfrequencyof 2700 Hz is applied a Schmitttrigger22 whose input sensitivity can be varied by a preset potentiometer 23. The output of the trigger 22 is fed to the mode select circuit 24 which preselects the mode of operation ofthe circuit.

An external signal, logic low, is preset at the select pin 24a to set up the latched mode of operation. In this mode both an 800 select circuit 37 and a 60 second timer circuit 25 are inoperative.

The input signal used via a data control circuit 27 to a decadic counter 28. The gate input 28A to this counter receives a timing signal from a mastertime base divider29 which gatesthe counteron fora period of 24C msec and offfor a period of 80 msec. During the "on" counting phasetheinputfrequency, if correct, will cause the counterto accumulate 648 counts. The decoder 30 which operates in three bit mode is arranged to "look" for predetermined counts above and below 648 representative of a band offrequencies. In thiswayfinelytolerancedfre quency limits can be set.An external logic signal preset bythe user allowsthe decoderto operate at any of two pre-fixed bandwidths. qounts represent ative of + 25 Hz are selected by logfc low and + 50 Hz by logic high. An "in range" frequency causesthe decoder 30 to provide a pulse every 320 msec via the frequency low/normal circuit 31 to both a continuity store 32 and a timer 33.

The continuity store is looking for seven suc cessive pulses within the period 2 to 3 seconds, and in response to that will set the relay latch 26 and op erate the outer loop relays 11 a, 11 b via windings 11 c.

Out of range frequencies are discriminated against in thefollowing ways:- (i) Where the frequency is too high then the dec oder 30 gives an output via the frequency high circuit 34 to a reset gate 35which is effective to reset the continuity store 32. Thus this store will not count more than one pulse and the relay latch 26 will not be set.

(ii) Where the frequency is too low, or indeed absent, then the decoder 30 will not provide pulses to the frequency low/normal circuit 31. This in turn will not provide pulses forthe timqr 33. This circuit acts as a re-triggerable monostable with a period in excessof320 m sec(inthis embodiment 420 m sec).

If the timer 33 is not reset it changes state to create, via reset gate 35, a reset of continuity store 32. Thus the absence of a single count or more is accommodated, thereby ensuring the detection of breaks in transmission of short duration. This provides a highdegreeofimmunitytomisoperation.

Afurther circuit, a two second data lock-out 36 also makes use ofthe monostabletimer31 properties.

When the condition arises that: a) The relay latch 26 has operated and b) Command tone has ceased * (*determined as detection of absence of tone by change of state of the timer 33), then the two second data lock-out comes into play.

When initiated it acts on the data control 27 to accept an alternative data source provided by the mastertime-base 29. This is fed to the decadic counter 28 to be decoded by a subsection of the decoder 30. The count, representative of the time span 2 seconds, uses a number smaller than those adopted for bandwidth checking in order not to create any unwanted states in the continuity store 32 or reset activities from the reset gate 35.

Thetermination of the count sequence reestablishes the data input via the data control 27 and resets the continuity store 32 via the reset gate 35.

The cycle of command decoding may now be repeated to releasethe latch.

The reset circuitry is carefully arranged such that in addition to out of range frequencies not operating the latch 26, the loss of a single cdunt (or more) in the sequence of seven counts gives an invalid total count. For example a short break or interruption in transmission of the frequency might occur, and this is to be rejected as invalid. This provides a high de greeofimmunityto misoperation.

Operation in timedmode For operation in the timed mode, the mode control 24 requires a preset logic high at its select input24a.

In this condition both the 800 Hz select circuit 37 and the 60 second timer 25 are operative.

The operation issimilartothatofthe latched mode in respect of command tone recognition. From the point of recognition, previously described as the setting ofthe relay latch, an instruction is passed from the continuity store 32 to the mode control 24. This activates the circuits 25 and 37. The 60 second timer takes input from the time base 29. On reaching count maturity it provides a signal to reset the relay latch 26 thereby releasing the relay coils 11 c and their contact sets Ila and 11j.

From the time that the 60 sec. counter is started, until termination, the 800 Hz select circuit 37 takes an output from the time-base, as a square wave, and passes it from the processor to an 800 Hztuned amplifier 38 to give a reasonably pure sinusoidal tone suited to line transmission. The level of this tone is further set by a potentiometer 39.

This mode of operation is used on two wire circuits in the described embodiment but other applications areforeseenfortimed mode.

2-Wire version A2-wireversion can be implemented instead of the 4-wire version described. This will operate as de scribed forthetimed mode of operation. Itwill differ from the embodiment described (applied to 4-wire circuits) by having only one looping relay and a modified buffer amplifier in orderto insert the 800 Hztone back on its receiving pair. The processor is already designed such that data guarding occurs i.e. Hz is prevented from reaching the counter.

The manual looping facilities forthe 2aversion are simplerthan those described. Looping attenuators are not required.

The processor can be used not only to operate an auto return signal facility such as loop-back or Hz signal in responseto an input frequency of predetermined parameter. The processor could be used to remotely operate some pther device where a high degree of immunity to misoperation is important.

The processor (3) can be realised in integrated cir cu it form as a custom uncommitted logic array.

Claims (5)

1. Amethodfortesting thatacommandsignal has a predetermined frequency and persists for a predetermined duration, comprising the steps of selecting the command signal, shaping the selected command signal, and counting the oscillations of the shaped command signal a known number of times, and generating an output signal representative of a valid signal when the selected signal is of the predetermined frequency and duration for each count.

2. Adevicefortestingthatasignal hasapred- oterniined frequency and persists for a predetermined duration, comprising a filter for selecting thesignal,ashapingcircuitforshapingthesignal, and a bounded frequency counter for counting the shaped signal oscillations and whose operation is recycled a known number oftimes, and wherein the known number is representative of a positive test resuit.

3. Adeviceforvalidating atesttonesignalcom- prising an input trigger ci rcu it for receiving the signal, a first counter for counting the output of the trigger circuit, a time base circuit for periodically gat- ing the counter input, a decoderfqr decoding the counter output over the gated periods, a reset circuit responsive to the decoded output to reset the counter in the event the frequency ofthe received signal is not within predetermined tolerances, and a second counter responsive to counting a predetermined number of successful periodic operations of the first counter to enable a response circuit representative of a valid test tone signal received.

4. Acircuitforestablishing thata singletone ex- ists for a finite time, wherein the tone oscillations are counted by a bounded frequency counter whose operation is recycled a known number of times, and if each operation is successful said known number of times an output signal is established representative of a valid tone received.

5. Atonesignalvalidating circuit substantially as hereinbefore described with reference to item 3 of the accompanying drawing.