GB2184580A

GB2184580A - External memory controller

Info

Publication number: GB2184580A
Application number: GB08630540A
Authority: GB
Inventors: Akira Kanda
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1985-12-23
Filing date: 1986-12-22
Publication date: 1987-06-24
Also published as: JPS62147548A; GB8630540D0

Abstract

An external memory controller 13 controls an external memory 4 constructed so as to be simultaneously accessible from a plurality of processor subsystems 1, 2 and can maintain the integrity of the contents of the input/output buffer areas 1c, 2c of the plurality of processor systems 1, 2. The controller 13 has therein a table 13a for managing existence states of all data blocks 4a of the external memory 4, a function of instructing each processor subsystem 1, 2 to invalidate a specified data block within the input/output buffer area 1c, 2c thereof, and a function of instructing each processor subsystem 1, 2 to send the specified data block within the input/output buffer area back to the external memory controller 13. Therefore, the input/output buffer areas can be set in the respective processor subsystems 1, 2 without causing contradictions in their update so that independent exclusive control mechanisms between electronic computers are not required. <IMAGE>

Description

SPECIFICATION External memory controller BACKGROUND OF THE INVENTION This invention relates to an external memory controller in an electronic computer system. More particularly, it relates to an external memorycontrol- lerwhich controls an external memory constructed so asto be simultaneously accessiblefrom a plurality of processor subsystems and which can maintain the contents ofthe input/output buffer areas of the plurality of processor systems without any contradic tions.

Fig. 2 is a block diagram showing the arrangement of an electronic computer system comprising a plurality of processor subsystems, an external mem ory which is accessed from these processorsubsys- tems, and a prior-art external memory controller which serves to control the external memory. Refer ring to the figure, one processor subsystem shown at numeral 1 consists of a central processor unit 1 a and a main memory unit 1 b. This main memory unit 1 b has an input/outputbufferarea 1 c. Likewise, another processor subsystem 2 has a central processor unit 2a, a main memory unit 2b and an input'output buffer area 2c.The external memory controller 3 is con nected to the processorsubsytems 1 and 2, and has an occupancycontrolflag3a.Theextenal memory 4 is connected to the external memory controller3, and one of the data blocks in this external memory is denoted by symbol 4a. Acommon memory 5 is shared by both the processor subsystems 1 and 2.

The electronic computer system employing the prior-artexternal memory controller3 is arranged as described above. Therefore, when a request seeking to alterthe data block4a in the external memory4is made by the processor subsystem 1,the data block 4a is loaded into an empty block (not shown) within the input/outputbufferarea 1 c of the main memory unit 1 b of the processor subsystem 1 through the external memory controllor3, and the content thereof is referred to and altered.Herein, in orderto reduce the numberofinputsto and outputsfrom the external memory 4, the altered data block4a within the input/outputbufferarea lcisnotwritten back into the external memory 4 until the input/output buffer area 1 c has no empty block.

On the other hand, if a request to referto and alter the identical data block 4a is made by the processor subsystem 2 in the meantime and the data block4a within the external memory 4 is loaded into the input/output buffer area 2c, the content of the data will be the old content prior to the alteration by the processor subsystem 1. Therefore, a a so-called update contradiction ofthe data content arises, and the electronic computersystem will not operate properly.

In orderto avoid this problem, either of the following methods have heretofore been adopted: (1) In the first method, when the processor su bsystem 1 first accesses the external memory 4, it requests that the occupancy control flag 3a within the external memory controller 3 be set. The occupancy control flag 3a is reset after a series of data input/output processes have ended and all data blocks within the input/output buffer area 1 c have been written back into the external memory4again. With this measure, the contradiction in updating data can be prevented.

However, this lengthens the period of time during which the other processor subsystem 2 waits for its access to the external memory 4 adversely affecting the efficiency of the electronic computer system.

(2) In the second method a resource exclusivemanagement mechanism is provided between a plurality of processor subsystems, such as the common memory 5 which can be shared by both the processor subsystems 1 and 2. Each processor subsystem 1 or2givesthecommon memory 5 a request of registration to the effect of occupying the data block4a, prior to accessing the data of the external memory 4, and it actually accesses the data block 4a after waiting forthe acceptance of the request. This measure provides an efficiency higher than that of the first method in which the external memory 4 is entirely occupied. However, a resource exclusive-management mechanism such as common memory 5 is required besides the external memory 4, and a data management program must access it frequently.

Withtheprior-artexternal memory controller, in either case, unless one processor subsystem writes the modified data block stored in the internal input/ output buffer area thereof, back into the original location of the external memory, the same data cannot be accessed from the other processor subsystem.

Conversely, forthe purpose of shortening the period of time during which the other processor subsystem is kept waiting, the altered data block needs to be immediately written from the input/output buffer area into the external memory. This incurs the problem that the essential intention of the input/output buffer area to reduce the number of inputs/outputs between the processor subsystem and the external memory is reduced to half.

SUMMARY OF THE INVENTION This invention has been made in order to solve the problem as mentioned above, and has for its objectto provide an external memory controllerwhich permits each processor subsystem to hold an input/output bufferareaforreducingthenumberofinputs/outputs, without causing any contradictions in the update of data when an identical external memory has been accessed from a plurality of processor subsystems.

The external memory controller according to this invention has therein a table which manages existence states of all data blocks of the external memory, a function for instructing each processor subsystem to invalidate a specified data block within the internal input/output buffer area, and a function for instructing each processor subsystem to send a specified data blockwithin the input/output buffer area back to the external memory controller.

Accordingtothisinvention,incompliancewith a requestfordata from a specified one ofthe processor subsystems, the existence of the latest data of the corresponding data block is detected by the use ofthe data block management table. If the data exists within the external memory, it is immediately transferred to the input/output buffer area of the specified processor subsystem, whereas if the data does not exist, the corresponding latest data block is transferred from another processor subsystem to the processor subsystem making the request. In addition, when the request accompanies an alteration, the other processor subsystem is caused to invalidate the data block stored in the input/output buffer area thereof.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is block diagram showing an electronic computer system which uses an embodiment ofthis invention; and Fig. 2 is block diagram showing an electronic computer system which uses an external memory controller in the prior art.

PREFERRED EMBODIMENT OF THE INVENTION Now, an embodiment of this invention will be described with reference to Fig. 1. Fig. lisa block diagram showing the arrangement of an electronic computer system which comprises the external mem ory controller ofthis invention. As in the system of Fig.

2, processor subsystems 1 and 2 have central processor units la and 2a and main memory units 1 band 2b, respectively. The main memory units 1 and 2b have input/output buffer areas 1c and 2c, respectively. The external memory controller 13 of this invention has a data block existence managementtable 1 3a. As in the system of Fig 2, and external memory 4 has data blocks, one of which is denoted by symbol 4a.

In the electronic computer system arranged as described above, the operation of access to the external memory 4 is divided into the transfer operation of sending data from the external memory 4 to the processor subsystem 1 or 2, and the return operation of bringing a data blockfrom the corresponding processor subsystem in a case where the latest data block does not existwithin the external memory 4. Further, there is the operation of invalidating data in which when a read request premised on the alteration of the content of data has been received, all the processor subsystems 1 and 2 are caused to delete parts of predetermined data blocks within the internal input/output buffer areas 1c and 2cthereof.

Thetransferoperation is subdivided in two; a copying mode in which the state of the data block existence managementtable 1 3a is not changed even afterthe completion of transfer, and a shifting mode in which a corresponding entry in the data block existence managementtable 1 3a is changed into nonexistence afterthe completion of transfer. Here, the expression "nonexistence" signifies a case where the pointer of a corresponding entry in the data block existence managementtable 13a designates any subsystem other than the external memory 4 itself.

Likewise, the return operation also included a copying mode which does not accompany the change ofthe data block existence managementtable 13a, and a shifting mode which accompanies the change of the corresponding entry of the existence management table 13a.

The operation ofthis invention will hereinafter be described in more detail.

In the data block existence managementtable 1 3a, there are pointers which correspond to all the data blocks ofthe external memory 4 and which designate the existence states thereof. In the initial state of the management table, the pointers designate that all the data items exist in the external memory4 itself.

(1) It is now assumed thata read requestforthe data block4a has been received by the external memory controller 13 in a read-only mode from the processor subsystem 1. Then, the external memory controller 13 detects the existence ofthe data block 4a in the external memory 4 in view of the data block existence managementtable 13a and immediately starts the transfer operation. Since the read request is in the read-only m ode, th is tra nsfe r operation is in the copying mode. That is, the data block 4a ofthe external memory 4 is transferred to the processor subsystem 1, and the content of the data block existence managementtable 13a does not change even after the completion of the transfer.The processor subsystem 1 holds therein the transferred data until all the blocks of the input/output buffer area 1 c are filled up. In the meantime, the processorsubsystom 1 does not alter the contents of data.

(2) Subsequently, when a read request in a modification mode has been received by the external memory controller 13 from the processor subsystem 2 underthe above state, the external memory controller 13 detects the existence ofthe pertinent data block 4a in the external memory4and immediatelystartsthe transfer operation. In this case, the transfer is performed in a shifting mode because ofthe read request in the modification mode. That is, the external memory controller 13 begins to transferthe data block 4a of the external memory4 and also gives all the processor subsystems 1 and 2 the invalidation instructions of deleting the data block 4a from the input/ output buffer areas 1 c and 2c.In addition, after the completion ofthetransfer, the pointer ofthat entry of the data block existence managementtable 1 3a which corresponds to the data block 4a is changed into nonexistenceso as to designate the p rocessor su bsys tem 2. In the processor subsystem 2, the data block4a is kept stored in the input/output buffer area 2c along with a flag which designate that the operation is in the modification mode.

(3) Next, there will be explained a case where the content of the entry corresponding to the data block4a in the existence management table 13a indicates nonexistence.

When, subsequently to the result of above item (2), a read requestforthe data block4a has been again transmitted from the processor subsystem 1 to the external memory controller 13 in the read-only mode, the external memory controller 13 starts the return operation upon detecting thatthe data block 4a does not exist in the external memory4 but in the processor subsystem 2. That is, a copying mode return request forthe data block 4a is sent to the processor subsystem 2. The processor subsystem 2 writes the data block4a into the external control memory 13.

Next, the external memory controller 13 executes the copying modes transfer to the processor subsystem 1.

The data block 4a transferred bythe copying mode is once loaded intothe input/output bufferarea 1c, and it is invalidated immediately after use.

(4) Lastly, there will be explained a case where, when the data block4alieswithin the processor subsystem 2 and is nonexistent in the external memory 4, a read request in the modification mode is also generated by the processor subsystem 1.

As in the case ofthe above item (3), the external memory controller 13 detects the nonexistence of the data block4a and starts the return operation. Since, however, the read request in the modification mode is received in this case, a return request in the shifting mode is sent to the processor subsystem 2. This processor subsystem 2 transfers the pertinent data to the external memory controller 13, and invalidates the entry of the data block 4a within the input(output buffer area 2c.

Subsequently, the content of that entry in the data block existence managementtable 13a within the external memory controller 13 which corresponds to the data block 4a temporarily indicates existence.

However, when the shifting modetransferto the processor subsystem 2 has been completed im mediately thereafter, the co ntent of the afo remen tioned entry comes to designate the processor sub- system 1 and to indicate the nonexistence of the data block4a.

In the above example, the processor subsystem 2 has been described as unconditionally complying with the shifting mode return request from the external memory controller 13. Actually, however, the processorsubsystem 2 can be locked in order to exclusively occupythe pertinent data block 4a for a fixed period oftime,to rejecttheshifting mode return requestfrom the external memory controller 13 orto keep it standing-by.

Thus, an access control mechanism in a more logical file unit can be realized with a program management layer of higher priority.

In the specification, the case of the two processor subsystems has been referred to. However, even when three or more processor subsystems are included, they can be operated quite similarly within a range where they can be designated by the pointers in the data block existence managementtable.

Further, although the entries of the data block existence managementtable have been the pointers which designate the corresponding processorsubsys- tems, they may well be replaced with flag which merely designate whether or not data blocks exist in the external memory, whereupon in case nonexist ence, a return request is sentto all the processor subsystems and is respondedto bythe corresponding processor subsystem.

Further, the read requestforthe nonexistent data block has been keptstanding-byuntilthecompletion of reading through the return of the data block. This operation, however, may well be replaced with an operation in which the read requestforthe nonexistent data is once broughtto an error end, and thereafter, when the return of the data is over, an interrupt is applied from the external memory control lerto the processor subsystem, and the processor subsystem can be retried.

As described above, according to this invention, in sharing an identical external memory with a plurality of processor subsystems, a mechanism for monitoring the existence situation of data and the update contradictions thereof is provided in an external memory controller. Therefore, the input/output buffer areas can be set in the respective processor su bsystems without causing contradictions in the update of data without requiring independent exclusive control mechanisms between electronic computers.

Claims

1. An external memorycontrollerforcontrolling an external memoryarrangedsoastobesimul- taneously accessible from a plurality of processor subsystems each of which includes a central processor unit and a main memory unit having an in putt output buffer area;; wherein said external memory controller has an existence management table for data blocks, a func- tion of requesting each of said processor subsystems to return a data block stored in said external memory, and a function of requesting said each processor subsystem to invalidate a specified data block within the input/output buffer area thereof, thereby to comply with a data transfer request from any of said processor subsystems to bring the latest data of the request from the corresponding processor subsystem and to transfer it to the requesting processor subsystem, and also to give the corresponding processor subsystem an instruction for invalidating the same data block in said input/output buffer area in a case where a data request from any of said processor subsystems accompanies an alteration of a data content, whereby contents of said input/output buffer areas in said plurality of processorsubsystems can be maintained without any contradictions.

2. An external memory controllerfor controlling an external memory substantially as described herein with reference to Figure 1 ofthe accompanying drawing.