GB2182491A - Protecting integrated circuits against electrostatic charges - Google Patents
Protecting integrated circuits against electrostatic charges Download PDFInfo
- Publication number
- GB2182491A GB2182491A GB08625069A GB8625069A GB2182491A GB 2182491 A GB2182491 A GB 2182491A GB 08625069 A GB08625069 A GB 08625069A GB 8625069 A GB8625069 A GB 8625069A GB 2182491 A GB2182491 A GB 2182491A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- polarity
- epitaxial
- integrated circuit
- protected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 239000007943 implant Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 6
- 230000003068 static effect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910052729 chemical element Inorganic materials 0.000 claims 4
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000021715 photosynthesis, light harvesting Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 206010037660 Pyrexia Diseases 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
An arrangement for protecting integrated circuits against electrostatic charges, ensuring reliable operation at high levels of damaging voltage, is composed of two SCRs coupled in inverse parallel and integrated in the same epitaxial (13) tub as the integrated circuit to be protected (3) employing top-bottom production techniques. <IMAGE>
Description
SPECIFICATION
Electronic device for protecting integrated circuits against electrostatic charges and process for the production thereof
The present invention relates to an electronic device for protecting ntegrated circuits from electrostatic charges, as well as to a process for producing the device.
As is known, in many applications it is necessary to have electronic devices arranged on the input of an integrated circuit to protect the same from electrostatic charges, both positive and negative, which can occur at the pins of the integrated circuit, causing at least its malfunction and in some instances its destruction.
Protection devices of this kind are known, with different embodiments. Some known devices, e.g., provide diodes and resistors in various configurations. The diodes are implemented in different manners, e.g. by employing the base-emitter or base-collector junction of integrated transistors. A known solution entails, as an example, the provision of two
Zener diodes having a first terminal connected in common with the input terminal of the circuit, to be protected through a resistor, and the other terminal connected respectively to the supply voltage and to the ground line, so that in case of electrostatic discharges of one sign or the other, one Zener diode or the other intervenes, blocking the voltage at a preset limit value.
These solutions, though very widespread, are not completely satisfactory, due to the high energy dissipation levels due to the fact that these diodes block the voltage at a relatively high value, with a consequently high dissipation.
Other known solutions employ SCRs (Silicon
Controlled Rectifiers) which, though they intervene at high voltage values, then maintain it at lower levels, allowing thus a smaller energy dissipation. However, these circuits, too, are not completely satisfactory. In fact they are currently produced employing different epitax
ial tub for each component, thus presenting a rather high bulk.
Taking into account this situation, the aim of the present invention is to provide an electronic device capable of reliably protecting the integrated circuits connected thereto, eliminating the disadvantages featured by the prior art.
Within this aim, a particular object of the present invention is to provide an electronic protection device having a small energy dissipation, such as to allow the attainment of high voltage levels, and therefore capable of ensuring the effective intervention and operation of the device even for very high discharges.
Still another object of the present invention is to provide a said electronic protection device having a small bulk so that the whole formed by the integrated circuit and of the protection device may have low production costs and high electric characteristics.
Not least object of the present invention is to provide a said electronic protection device which may be produced employing alreadycommon techniques for manufacturing integrated circuits, and that furthermore allows the production of the protection device and of the related integrated circuit at the same time.
The aim and the objects described, as well as others which will better appear hereinafter, are achieved by an electronic device for protecting integrated circuits from electrostatic charges, according to the invention, comprising solid-state static switches connected between the input of the integrated circuit to be protected and a reference-voltage line, characterized in that said solid-state static switches comprise two controlled rectifiers (SCRs) connected in inverse parallel and integrated in a single epitaxial tube with the integrated circuit to be protected.
The invention furthermore relates to a process for producing the electronic protection device, which allows the achievement of the above described aim and objects.
Further characteristics and advantages of the invention will be better apparent from the description of a preferred, but not exclusive, embodiment, illustrated by way of non-limitative example in the accompanying drawings, where:
Figure 1 is the circuital equivalent of the device according to the invention;
Figure 2 is a diagram illustrating the currentvoltage characteristic of the device according to Fig. 1, and
Figure 3 is a transverse cross section of a silicon wafer in which the structure according to Fig. 1 has been produced.
With reference to Fig. 1, the device according to the invention essentially comprises of a pair of SCRs 1, 2 connected in inverse parallel between the input terminal (IN) of a circuit to be protected (schematically represented in the figure as a broken-line rectangle designated with the reference numeral 3 and containing transistors and/or other semiconductor elements) and a ground line, designated with the reference numeral 4. In detail, the anode 5 of the SCR 1 is connected to the input line IN, while the cathode 6 of the same SCR 1 is connected with the ground 4, while the anode
7 of the SCR 2 is connected with the ground, the cathode 8 of the same SCR 2 being con
nected with the input IN.Consequently the
SCR 1 will operate in the case of positive electrostatic discharges, while the SCR 2 will operate in the case of negative electrostatic discharges, thus obtaining the voltage-current
behaviour illustrated in Fig. 2.
The circuit is completed by the resistors 9' and 9" formed in parallel between two layers of the SCRs 1 and 2 and having the function of preventing switching on of the same in the presence of variations in voltage or loss currents on the capacities of the connecions.
The characteristic of the present device lies in that the two SCRs in inverse parallel are integrated in a single epitaxial tube (as can be seen in Fig. 3) and produced during the same production process of the circuit to be protected allowing therefore a reduction in production costs and in occupied area.
With reference to Fig. 3, the device is composed of a P--type substrate 10 on which the insulating N± type layers 11 has been provided, said layer 11 at the same time forming the cathode of the SCR 1. Adjacent to the layer 11, the P± type layer 12 lies, having however a smaller area with respect to the layer 11. This layer 12 forms the anode of the SCR 2. The chip further comprises a Ntype epitaxial layer 13 extending above the substrate 10 up to an upper face 20 of the device and encircling the top part of the layers 11 and 12. Through the epitaxial layer 13 insulating zones 30 are formed, extending from the surface 26 to the substrate 10 so as to externally delimit the epitaxial tub accommodating the protection device according to the invention and the integrated circuit 3, as schematically shown in Fig. 3.The epitaxial tub 13 furthermore encircles the P'- type layer 14 which forms the anode of the SCR 1 and the
N± type layer 15, defining the cathode of the
SCR 2. Through the epitaxial tub 13 two regions are furthermore provided, designated at 11a and 12a and of the N ' and P'- type, respectively, extending from the top face 20 of the device to the respective insulating layer 11 or 12. Thereby an intermediate epitaxial zone 13' is formed between regions 1 1a and 12a, while an inner portion of the epitaxial layer 13, indicated at 13", is formed, as delimited at the bottom by the layer 12 and laterally by the region 12a. The epitaxial inner portion 13" in turn encircles layers 14 and 15 of the P and N± type, respectively.The regions 11a and 12a are intended to connect respectively the layer 11 corresponding to the anode 6 of the SCR 1 and the layer 12 which forms the cathode 7 of the SCR 2 with the major outer surface 20 of the device. The device is completed by the metal layers 16 and 18 and by the insulating oxide layer 17. As visible the metal layer 16 short-circuits the layers 14 and 15 (anode 5 of the SCR 1 and cathode 8 of the SCR 2) while metal layer 18 short-circuits layers 12a and 1 1a (and hence layers 12 and 11 defining, respectively, the anode 7 and cathode 6).
Furthermore, as schematically indicated with broken line, between the regions 1 1a and 12a the resistor 9' is provided, e.g., by means of a suitable diffusion or other conventional technique, while the resistor 9" is formed by the resistance distributed along the layer 14 between the layer 15 and the metal layer 16.
The device illustrated is produced as follows. First, on a substrate doped with boron, a phosphorus implant is carried out to provide the N± type layer 11. This implant is performed at the same time as the implant provided to obtain the bottom sinker of the integrated circuit to be protected. Subsequently, a boron implant is carried out to provide the P+type layer 12. This phase occurs at the same time as the implant of the implanted insulation of the integrated circuit to be protected. Then the epitaxial layer 13 is grown at high temper ature so as to cause the diffusion of the boron and phosphorus atoms inside the substrate 10 and the epitaxial layer 13, as well as the formation of the layers 11 and 12 and the bottom part of the insulation layer 30.
Subsequently, boron atoms ared deposited and diffused to obtain the region designated with 12a, employed to connect the anode of the SCR 2 with the surface 20. These phases are performed at the same time as the deposition and diffusion phases of the insulating layer in the integrated circuit to be protected thus obtaining also the upper part of layer 30.
Then phosphorous is deposited and diffused, to provide the region 1 lea. This phase is performed at the same time as the deposition and diffusion of the diffused sinker in the integrated circuit to be protected and provides a connection to the surface 20 for the cathode of the SCR 1. Then the other phases e.g.
deposition and/or diffusion follow for forming the layers 14 and 15, the insulation layer 17 and metal layers 16, 18 for providing the contacts.
As can be seen from the above description, the invention fully achieves the aims proposed.
In fact, an integrated device has been provided which is capable of protecting even from high-balue discharges by virtue of the use of SCR structures which, after operating, function at low voltage thus ensuring low dissipations. In fact, in an actual implementation of this structure it was possible to achieve very high damaging-voltage values for electrostatic discharges, even higher than 10,000
Volts.
The fact should be furthermore noted that this device has an extremely small bulk by virtue of being provided in a single epitaxial tub with the device to be protected.
Furthermore, the device can be produced during the same production phases as the integrated circuit to be protected, employing the same procedure phases employed for the latter.
The invention thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept.
Furthermore, all the details can be replaced by technically equivalent ones.
Claims (4)
1. Electronic device for protecting integrated circuits from electrostatic charges, comprising solid-state static switches connected between the input of the integrated circuit to be protected and a reference-voltage line, characterized in that said solid-state static switches comprise two controlled rectifiers connected in inverse parallel and integrated in a single epitaxial tub with the integrated circuit to be protected.
2. Device according to claim 1, characterized in that it comprises a substrate of a first polarity, a first implanted layer, adjacent to said substrate and having a second polarity, substantially opposite to said first polarity, a second implanted layer, substantially of said first polarity and extending at least partially adjacent to said first implanted layer, an epitaxial tub substantially of said second polarity extending at least partially adjacent to said second implanted layer and said substrate, and having portions facing an outer face of said device, a first diffused layer substantially of the first polarity, at least partially encircled by said epitaxial tub and having sections facing said outer face of the device, a second diffused layer substantially of said second polarity, encircled by said first diffused layer and facing with one side thereof said device outer face, a metal layer covering at least partially said sections and said sides of, respectively, said first and second diffused layers at said device outer face, a first insulating region substantially of said first polarity, extending through said epitaxial tub from said device outer face to ssaid second implanted layer and thereby externally delimiting an inner epitaxial region of said epitaxial tub, said inner epitaxial region being further delimited on the bottom by said second implanted layer and internally by said first diffused layer, as well as a second insulating region substantially of said second polarity extending through said epitaxial tub externally to said first insulating region from said device outer face to said first implanted layer.
3. Process for fabricating an electronic protecting device according to claims 1 and 2, characterized by:
-first implanting of atoms of a first chemical element on a substrate of a first polarity, for forming a first layer of a second polarity, substantially opposite to the first, said first implanting being performed at the same time as a sinker implant of the integrated circuit to be protected;
-second implanting of atoms of a second chemical element on said first implant, for forming a second layer substantially of said first polarity, said second implanting being performed at the same time as an implant for the implanted insulation of said integrated circuit to be protected;;
-growth of an epitaxial layer at high temperature with formation of said first layer, constituting a terminal electrode of one controlled rectifier, and of said second layer constituting a terminal electrode of a second controlled rectifier;
first deposition and diffusion of atoms of said second chemical element through said epitaxial layer to form a first insulating region substantially of said first polarity, connecting said second layer to a device outer face, said first deposition and diffusion being performed at the same time as diffuse insulating layers of said integrated circuit to be protected;;
-second deposition and diffusion of atoms of said first chemical element through said epitaxial layer externally to said first deposition to form a second insulation region substantially of said second polarity, connecting said first layer to said device outer face, said second deposition and diffusion being performed at the same time as a diffused sinker of said integrated circuit to be protected:
-per se known making of a third layer substantially of said first polarity and of a fourth layer substantially of a second type of polarity within said first and second insulation regions for providing two terminal electrodes of said controlled rectifiers; and
-deposition of a metal layer at least partially adjacent to and in contact with said third and fourth layers.
4. An electronic device for protecting an integrated circuit against electrostatic charges, substantially as described herein with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT22638/85A IT1186337B (en) | 1985-10-29 | 1985-10-29 | ELECTRONIC DEVICE FOR THE PROTECTION OF CIRCUITS INTEGRATED BY ELECTROSTATIC CHARGES, AND PROCEDURE FOR ITS MANUFACTURE |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8625069D0 GB8625069D0 (en) | 1986-11-26 |
| GB2182491A true GB2182491A (en) | 1987-05-13 |
| GB2182491B GB2182491B (en) | 1989-10-11 |
Family
ID=11198711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8625069A Expired GB2182491B (en) | 1985-10-29 | 1986-10-20 | Electronic device for protecting integrated circuits against electrostatic charges and process for the production thereof |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS62104155A (en) |
| DE (1) | DE3635729A1 (en) |
| FR (1) | FR2589278B1 (en) |
| GB (1) | GB2182491B (en) |
| IT (1) | IT1186337B (en) |
| NL (1) | NL8602704A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0338699A2 (en) * | 1988-04-20 | 1989-10-25 | Texas Instruments Incorporated | Transient protection circuit |
| EP0352896A3 (en) * | 1988-06-27 | 1990-02-07 | Advanced Micro Devices, Inc. | Esd protection circuitry for bipolar processes |
| EP0414934A1 (en) * | 1989-08-29 | 1991-03-06 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| EP0429709A1 (en) * | 1989-11-30 | 1991-06-05 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| EP0433758A2 (en) * | 1989-12-19 | 1991-06-26 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| EP0442391A2 (en) * | 1990-02-14 | 1991-08-21 | Texas Instruments Deutschland Gmbh | Circuit arrangement for protecting an input of an integrated circuit fed from a supply voltage source from overvoltages |
| EP0477393A1 (en) * | 1990-09-24 | 1992-04-01 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| US5637892A (en) * | 1991-03-28 | 1997-06-10 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
| WO2001004958A1 (en) * | 1999-07-08 | 2001-01-18 | Maxim Integrated Products, Inc. | Electrostatic discharge protection for analog switches |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2723904B2 (en) * | 1988-05-13 | 1998-03-09 | 富士通株式会社 | Electrostatic protection element and electrostatic protection circuit |
| DE3835569A1 (en) * | 1988-10-19 | 1990-05-03 | Telefunken Electronic Gmbh | Protective arrangement |
| DE19539079A1 (en) * | 1995-10-20 | 1997-04-24 | Telefunken Microelectron | Circuit arrangement |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5823471A (en) * | 1981-08-05 | 1983-02-12 | Toshiba Corp | Semiconductor device |
| US4484244A (en) * | 1982-09-22 | 1984-11-20 | Rca Corporation | Protection circuit for integrated circuit devices |
| IT1212767B (en) * | 1983-07-29 | 1989-11-30 | Ates Componenti Elettron | SEMICONDUCTOR OVERVOLTAGE SUPPRESSOR WITH PREDETINABLE IGNITION VOLTAGE WITH PRECISION. |
-
1985
- 1985-10-29 IT IT22638/85A patent/IT1186337B/en active
-
1986
- 1986-10-20 GB GB8625069A patent/GB2182491B/en not_active Expired
- 1986-10-21 DE DE19863635729 patent/DE3635729A1/en not_active Withdrawn
- 1986-10-27 FR FR868614920A patent/FR2589278B1/en not_active Expired - Lifetime
- 1986-10-28 NL NL8602704A patent/NL8602704A/en not_active Application Discontinuation
- 1986-10-28 JP JP61258101A patent/JPS62104155A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0338699A3 (en) * | 1988-04-20 | 1990-06-13 | Texas Instruments Incorporated | Transient protection circuit |
| EP0338699A2 (en) * | 1988-04-20 | 1989-10-25 | Texas Instruments Incorporated | Transient protection circuit |
| EP0352896A3 (en) * | 1988-06-27 | 1990-02-07 | Advanced Micro Devices, Inc. | Esd protection circuitry for bipolar processes |
| EP0414934A1 (en) * | 1989-08-29 | 1991-03-06 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| EP0429709A1 (en) * | 1989-11-30 | 1991-06-05 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| EP0433758A3 (en) * | 1989-12-19 | 1991-09-04 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| EP0433758A2 (en) * | 1989-12-19 | 1991-06-26 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| EP0442391A2 (en) * | 1990-02-14 | 1991-08-21 | Texas Instruments Deutschland Gmbh | Circuit arrangement for protecting an input of an integrated circuit fed from a supply voltage source from overvoltages |
| EP0442391A3 (en) * | 1990-02-14 | 1993-05-05 | Texas Instruments Deutschland Gmbh | Circuit arrangement for protecting an input of an integrated circuit fed from a supply voltage source from overvoltages |
| EP0477393A1 (en) * | 1990-09-24 | 1992-04-01 | Siemens Aktiengesellschaft | Input protection structure for integrated circuits |
| US5637892A (en) * | 1991-03-28 | 1997-06-10 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
| WO2001004958A1 (en) * | 1999-07-08 | 2001-01-18 | Maxim Integrated Products, Inc. | Electrostatic discharge protection for analog switches |
| US6188088B1 (en) | 1999-07-08 | 2001-02-13 | Maxim Integrated Products, Inc. | Electrostatic discharge protection for analog switches |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2589278A1 (en) | 1987-04-30 |
| GB2182491B (en) | 1989-10-11 |
| GB8625069D0 (en) | 1986-11-26 |
| IT1186337B (en) | 1987-11-26 |
| JPS62104155A (en) | 1987-05-14 |
| FR2589278B1 (en) | 1991-02-08 |
| NL8602704A (en) | 1987-05-18 |
| IT8522638A0 (en) | 1985-10-29 |
| DE3635729A1 (en) | 1987-04-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20021020 |