GB2180693A - Semiconductor structures - Google Patents
Semiconductor structures Download PDFInfo
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- GB2180693A GB2180693A GB08623532A GB8623532A GB2180693A GB 2180693 A GB2180693 A GB 2180693A GB 08623532 A GB08623532 A GB 08623532A GB 8623532 A GB8623532 A GB 8623532A GB 2180693 A GB2180693 A GB 2180693A
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- well
- layer
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- conductivity type
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 230000000873 masking effect Effects 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000000295 complement effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 29
- 238000012545 processing Methods 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- 239000002356 single layer Substances 0.000 abstract description 2
- 230000005669 field effect Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
- H01L29/0808—Emitter regions of bipolar transistors of lateral transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
A heterojunction structure comprising a well extending into a region of a substrate from the surface, the region being of one conductivity type (8) adjacent the well wall, and a layer of material of opposite conductivity type (10) being deposited in the well in contact with the well wall. The structure can be employed in, for example, a CMOS-compatible bipolar lateral transistor, where a base region (8) is formed at the walls of a hole-like well etched into an n-type well (16) of an n-well CMOS integrated circuit formed in a silicon semiconductor substrate (2). A deposited emitter (9) extends into the well and partially over the surface of masking layers (1,3) provided on the substrate (2), and is in contact with the base region (8). The deposited emitter (9) may comprise a doped-SIPOS (semi insulating polycrystalline silicon) layer 10 and a conducting polycrystalline silicon layer 11, or a doped single layer of polycrystalline silicon. An oxide layer (6) provides isolation preventing downward injection and ensuring good lateral operation. The heterojunction enables lower base resistance to be obtained than in homojunction devices by allowing high base doping. Such a lateral transistor structure requires only two additional maskings in comparison with conventional CMOS processing and, due to the use of a well, has a self-aligned action region. <IMAGE>
Description
SPECIFICATION
Semiconductor structures
This invention relates to semiconductor structures, and in particularto heterojunction structures for use in silicon technology, heterojunction lateral and planar bipolar transistor structures, which can be employed in CMOS integrated circuits, and methods of manufacturing these heterojunction and heterojunction lateral and planartransistorstructures.
Conventional integrated circuits generally employ eitherfield effect or bipolar elements. Field effect cir- cuits are used mainly in digital application, whereas for analogue applications, such as in radio signal processing, bipolar circuits are more suitable. in certain applications, e.g. telephony, processing of both digital and analogue signals is required and this nor mally requires the provision oftwo circuit chips, each with its associated peripheral circuitry. Clearly it would be advantageous to provide both bipolar and field effect functions on a single chip. Various tech niquesforcombining both field effect and bipolar elements on a single chip have already been suggested. However the previously proposed techniques suffer from various disadvantages.If, for example,
CMOS (Complementary Metal Oxide Silicon) processing is added to basic SBC (Standard Buried Collector) processing, good bipolar performance is achieved but the CMOS packing density, speed and predictability are compromised.
In our co-pending Application No. 8318320 (Serial
No. 2143082) (J.M. Young-P.F. Blomley-R.L. Baker 9- 9-2) a CMOS compatible bipolar lateral transistor structure is disclosed which can be manufactured using standard processing techniques and with only minimal disturbancetotheconventional CMOS pro cessing. These lateral transistor structures are formed by a three dimensional type technology and with such structures there can be problems of high base resistance and also alignment ofthe emitterto the base diffusion edge. In addition, suppression of vertical injection at the emitter base junction is difficu It.
Whereas the use of a heterojunction in a bipolar transistor was first proposed by W. Shockley in 1951, there has not been, until recently, a suitable system for producing them in silicon technology. It is an ob ject of the present invention to provide a heterojunction structure which is compatible with silicon technology and which enables CMOS compatible lateral bipolartransistorsto be obtained.
According to one aspect of the present invention there is provided a heterojunction structure comprising a semiconductor substrate having a surface, a hole-like well extending into a region ofthesubstrate from the surface, the region being of one con- ductivitytype adjacent the well wall, and a layer of material of the opposite conductivity type deposited inthewell in contactwiththewellwall.
According to another aspect ofthe present invention there is provided a method of manufacturing a heterojunction structureincludingthestepsoffor- ming a hole-like well in a region of a semiconductor substrate and extending from a surface thereof, causing a first portion of the region of the substrate which isadjacentthewell wall to be ofonecon- ductivitytype, a second portion ofthesubstratesurrounding the first portion being of the opposite con ductivitytype, and depositing a layer of material of the opposite conductivity type in the well in contact with the well wall.
Embodiments ofthe present invention will now be described with reference to the accompanying drawings, in which:
Figures 1 to 7showsuccessive processing steps requiredforthe manufacture of an npn heterojunction lateral transistor structure, and
Figure 8shows a plan view ofthe transistor structure of Figure 7, the emitter contact being omitted for reasons of clarity.
The processing sequence shown in Figures 1 to 7 comprises (Figure 1) growing a layerofsilicon dioxide 1 on an n-type silicon substrate 2, depositing a layer of silicon nitride 3 on the silicon dioxide layer 2 and by means of a mask (not shown) patterning the silicon nitride and oxide layers to provide an aperture 4therein. Awell 5 (Figure 2) is then etched in thesilicon substrate 2 by means, for example, of plasma etching,the silicon nitride layer3 acting as a mask.
Thewell baseorflooristhenimplantedwitha dopant,forexample arsenic or boron and thethus processed substrate is oxidised. During oxidation on thewell walls and floor is grown an oxide layer, a thicker oxide layer 6 being formed on the floor of the well, duetothe high doping level, than the layer7 on the side walls ofthewell (Figure3).Thesidewalls oxide layer7 is removed (Figure 4) by,forexample, immersion of the substrate in BHF (Buffered HydrofluoricAcid). A p-type base region 9 (Figure 5) is formed by,forexample,dopingthewell wallswith boron by implantation, or depositing a boron-doped glass layer thereon.In order to achieve the desired base width a drive-in procedure is performed.
A deposited n-type emitter 9 is formed as follows (Figure 6) by depositing a layer of intrinsic semiinsulating polycrystallinesilicon (SIPOS) 10, doping the SIPOS layer n-type by ion implantation with As or
P, depositing a layer of conducting polycrystalline silicon 11 on the doped SIPOS layer and patterning the layers 10 and 11 by means of a mask (notshown).
The emitter is basically comprised by the doped SIPOS layer 10 and an emitter contact 12 formed by patterning a deposited aluminium layer (Figure 7).
Thus there is provided a heterojunction emitter-base junction in silicon technology.
In Figure7there is also shown an n+ collectorcontact 13 diffused or implanted into the n-type sub strate and a metallic collector contact 14 which can be formed atthe same time as the emittercontact 12 by suitable patterning ofthe deposited aluminium layer. A metallic base contact 15 (Figure 8) can be similarlyformedfrom the aluminium layeron the surface of the semiconductor outside of the etched well. Whereas Figure 8 indicates a strip-like collector contact 14, the collector contact may alternatively extend in a ring-like manner around the well in orderto reduce the collector resistance.The base contact 15 may, with, for example, suitable use of an insulating layer in the vicinity ofthe SIPOS emitter, also extend in a ring-like manneraroundthewell ratherthan be strip-like as shown.
The npn heterojunction bipolartransistorthus, formed can be defined in an n-type well 16 (Figure 7) in a p-type substrate ratherthan directly in an n-type substrate. Thus the bipolar transistor may be formed with field effect devices in a single substrate, in part icular by using the n4ype wells available in an n-well
CMOS process to form the collector ofthe transistor, with the collector contact 13 being formed by the source/drain diffusion. The bipolar transistor requires onlytwo masking processes in addition to those employed to produce the CMOS devices, and has a self-aligned active region.The bipolartransistor is truly lateral in operation since downward injection is eliminated by use ofthe oxide isolation provided by oxide layer portion 6. The base resistance can be lowered, in comparison with homojunction transistors since the heterojunction emitter base junction allows the use of higher doping levels without lowering the gain of the transistor. This is particularly important in a lateral transistor, where a narrow base width can lead to a high base resistance rb. The device structure is particularly applicable to manufacture by low temperature processing and pulse an nealing, as disclosed for example in ourco-pending
Application No.8203242 (Serial No.211 4809)(P.D.
Scovell-P.J. Rosser-G.J. Tomkins 4-2-1) and Applica- tion No.81 28127 (Serial No. 2106709)(P.D. Scovell 3).
Whereas the manufacture of an npn heterojunction lateral transistor has been described, a pnp heterojunction lateral transistor may be correspondingly manufactured. Whereas an np emitter-base heterojunction in an integrated circuit has been described, bothnpandpn heterojunctionsmaybeformed inthe same circuit if required. The heterojunction maybe anisotype, that is between materials of opposite con ductivitytype, for example an n-SIPOS emitter and a p-Si base as described above, or isotype, that is one between materials of the same conductivity type, for example between n-SIPOS and n-Si which together comprise an emitter, the base comprising p-Si.In this case an n-type polycrystalline silicon layer may be deposited before the SIPOS layer. SIPOS is a useful material from which to form a heterojunction since the bandgap and resistivity can be changed simply by varying the oxygen doping.
Whilst the above processing involved depositing intrinsic SIPOS and subsequently doping it, alternatively doped SIPOS may be deposited. Instead of using a collector contact 13 formed by the n t sou rce/drain diffusion of n-well CMOS devices, a deposited SIPOS collector contact deposited at the same time as the emitter may be employed. The use of an etched well results in a particularly compact heterojunction making the structure particularly useful for bipolarl
CMOS applications where space (surface area) considerations are important
In an alternative embodiment a heterojunction lateral transistor, with the same basic structure as that described with reference to Figures 1 to 8, may be formed without the use of SIPOS. Instead ofthe
SIPOS layer 10 and the polycrystalline silicon layer 11, a single layer of polycrystalline silicon doped,for example, with arsenic may be employed. The use of a double layer including a SIPOS layer, however, has the advantage of involving a known contacting system to polysilicon. A SIPOS film is a CVD (Chemical Vapour Deposition) film deposited at around 600 Cforthe reaction of silane and nitride oxide.
Claims (23)
1. A heterojunction structure comprising a semiconductor substrate having a surface, a hole-like well extending into a region of the substrate from the sur- face, the region being of one conductivity type adjacent the well wall, and a layer of material ofthe opposite conductivity type deposited in the well in contact with the well wall.
2. A heterojunction structure as claimed in claim 1 wherein the surface of the substrate is provided with an electrically insulating layer at least adjacent to the well, and wherein the layer of material of opposite conductivity type extends out of the well and over a portion of the substrate surface on the electrically insulating layer.
3. A heterojunction structure as claimed in claim 1 or claim 2, wherein the substrate comprises silicon and wherein the layer of material of the opposite con ductivity type is comprised of doped semi-insulating polycrystalline silicon.
4. A heterojunction structure as claimed in claim 3 including a layer of conducting polycrystallinesil- icon disposed on the layer of doped semi-insulating polycrystalline silicon whereby to facilitate electrical contact thereto.
5. A heterojunction structure as claimed in claim 1 orclaim 2, wherein the substrate comprises silicon and wherein the layer of material ofthe opposite con ductivitytype is comprised of doped conducting polycrystalline silicon.
6. A heterojunction structure as claimed in any one ofthe claims 1 to 5, wherein the region ofthe substrate is of the opposite conductivity type except where it is adjacentthewell wall and is of the one conductivity type.
7. A heterojunction structure as claimed in claim 6 and including an oxide isolation layer at the floor of the well.
8. A heterojunction structure as claimed in claim 7, and comprising a lateral transistor, including a respective electrical contact to the region ofthe substrate ofthe opposite conductivity type, the region of the substrate ofthe one conductivity type andthede- posited layer of material of the opposite conductivity type.
9. A heterojunction structure as claimed in claim 8, wherein the region of the substrate of the opposite conductivity type is comprised by an n-well of an nwell CMOS (Complementary Metal Oxide Silicon) integrated circuit.
10. A method of manufacturing a heterojunction structure including the steps of forming a hole-like well in a region of a semiconductor substrate and extending from a surface thereof, causing a first portion of the region of the substrate which is adjacentthe well wall to be of one conductivity type, a second portion of the substrate surrounding the first portion being of the opposite conductivity type, and deposit ing a layer of material of the opposite conductivity type in the well in contact with the well wall.
11. A method as claimed in claim 10, wherein the well is formed by etching the substrate through an aperture in an insulating and masking layer disposed on the surface of the substrate, and wherein the deposited layer of material ofthe opposite conductivity type extends out of the well and over a portion ofthe insulating and masking layer.
12. A method as claimed in claim 1 1,whereinthe substrate is of silicon, and wherein the one conductivity type causing step comprises heavily doping the substrate the opposite conductivity type at the floorofthewell,oxidisingthefloorandwall ofthe well, removing the oxide from the well wall, and doping the well wall the one conductivity type.
13. A method as claimed in any one of claims 10 to 12, further including the steps of forming respective electrical contacts to the second portion of the region of the substrate, the first portion of the region of the substrate, and the deposited layer of material in the well.
14. A method as claimed in claim 13, wherein the region of the substrate comprises an n-well of an nwell CMOS (Complementary Metal Oxide Silicon) integrated circuit.
15. A method as claimed in anyone of claims 10 to 14, wherein the layer depositing step comprises depositing a layer of semih insulating polycrystalline silicon.
16. A method as claimed in claim 15, wherein the semi-insulating polycrystalline silicon is deposited in intrinsic form and subsequently doped the opposite conductivity type.
17. A method as claimed in claim 15 or claim 16 further including the step of depositing a layer of conducting polycrystalline silicon on the semiinsulating polycrystalline silicon whereby to facilitate electrical contact thereto.
18. A method as claimed in any one of claims 10 to 14, wherein the layer depositing step comprises depositing a layer of conducting polycrystalline silicon, which layer is doped the opposite conductivity type.
19. A heterojunction structure substantially as herein described with reference to and as illustrated in Figures 1 to 6 ofthe accompanying drawings.
20. A heterojunction lateral transistorsubstanti ally as herein described with reference to and as illus- trated in Figures 1 to 8 of the accompanying drawings.
21. A method of manufacturing a heterojunction structure substantially as herein described with referenceto and as illustrated in Figures 1 to 6 ofthe accompanying drawings.
22. A method of manufacturing a heterojunction transistor structure substantially as herein described with reference to and as illustrated in Figures 1 to 8 of the accompanying drawings.
23. A heterojunction structure made by a method as claimed in any one of claims 10to 18,21 to 22.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08623532A GB2180693B (en) | 1983-07-06 | 1986-10-01 | Semiconductor structures |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08318321A GB2143083B (en) | 1983-07-06 | 1983-07-06 | Semiconductor structures |
| GB08623532A GB2180693B (en) | 1983-07-06 | 1986-10-01 | Semiconductor structures |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8623532D0 GB8623532D0 (en) | 1986-11-05 |
| GB2180693A true GB2180693A (en) | 1987-04-01 |
| GB2180693B GB2180693B (en) | 1987-12-02 |
Family
ID=26286556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08623532A Expired GB2180693B (en) | 1983-07-06 | 1986-10-01 | Semiconductor structures |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2180693B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0316562A2 (en) * | 1987-11-19 | 1989-05-24 | Texas Instruments Incorporated | Semiconductor bipolar transistors with base and emitter structures in a trench and process to produce same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4303933A (en) * | 1979-11-29 | 1981-12-01 | International Business Machines Corporation | Self-aligned micrometer bipolar transistor device and process |
-
1986
- 1986-10-01 GB GB08623532A patent/GB2180693B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4303933A (en) * | 1979-11-29 | 1981-12-01 | International Business Machines Corporation | Self-aligned micrometer bipolar transistor device and process |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0316562A2 (en) * | 1987-11-19 | 1989-05-24 | Texas Instruments Incorporated | Semiconductor bipolar transistors with base and emitter structures in a trench and process to produce same |
| EP0316562A3 (en) * | 1987-11-19 | 1989-08-09 | Texas Instruments Incorporated | Semiconductor bipolar transistors with base and emitter structures in a trench and process to produce same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8623532D0 (en) | 1986-11-05 |
| GB2180693B (en) | 1987-12-02 |
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| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19930706 |