GB2177838A - Drive circuit for operating electroluminescent display with enhanced contrast - Google Patents

Abstract

An improved drive circuit for operating an electroluminescent display includes a circuit for basing column and row drivers to maximize the energization voltage for illuminated pixels 9 without reducing the contrast of the display. The energization voltages for the row and column drivers are combined with reverse biased de-energization voltages for inactivated pixels so that the applied voltage is less than the forming voltage. Interface circuitry is also provided for detecting the beginning of valid data for each line to be displayed, checking the selected display mode of the line and adjusting the timing of a system clock to display completely and uniformly characters in the 40-column, 80-column or graphics display mode. <IMAGE>

Description

SPECIFICATION Drive circuit for operating electroluminescent display with enhanced contrast The invention relatesto a driver circuit for energizing a direct currenteiectroluminescent (EL) display panel to display imagesofcharacters. More particular ly,the invention relates to a drive circuit which provides enhanced contrastforthe displayed characters and properly aligns the characters in 80 column, 40 column and graphics display modes.

The Cathode Ray Tube (CRT) has long been used as a video display, for example, in television sets and in computer display terminals. CRTs utilize an electron gun to selectively scan and energize a phosphor screen.The energized portions of the screen momen ta rily lu minesce to provide a visual image. CRTs have a substantial depth, in orderto accommodate the relatively large apparatus ofthe electron gun.

Electroluminescent display panels have been developed to provide a relatively thin display which does not have the size constraints inherent in the apparatus of a CRT. Electroluminescent display panels employ a matrix of phosphor pixels which are selectively flouresced to form an image. The phosphor pixels of an elecroluminescent display are caused to fluoresce bythe direct application of electrical energy.

The electroluminescent display has a plurality of anodes and cathodes which are arranged in overiap- ping relation to form columns and rowsofa matrix of pixel elements. An electroluminescent phosphor is disposed adjacent to each crossover point of the electrodes ofthe matrix. When a line and column electrode are simultaneously energized, the phosphor pixel element at the crossover pointofthe electrodes is caused to luminesce. An image isformed on the disply by sequentially energizing rows of electrodes of the matrix and selectively energizing corresponding column electrodes.

The brightness of the display is dependent upon the voltage difference between energized row and column electrodes. Thus, increasing the voltage difference between row and column electrodes hasthe desirable effect of increasing the brightness of energizing pixels. However, when row and column voltages are increased to provide added brightness, contrastofthe image is sharply reducedwhen either a row or column energization voltage exceeds a charac teristic "forming voltage" for the display. A desirable increase in brightness for the display has therefore not been achievable in view of this sharp loss of contrast with increasing voltage.

Accordingly, it is an object ofthe invention to provide a direct current electroluminescent display panel and associated driver circuitry which provide a substantially brighter image, without a corresponding sharp loss in image contrast.

Afurther object of the invention is to provide drive circuitry which,defines an increased voltage differ- encefor maximizingthe brightness of energized pixels and defines a reduced voltage below the formingvoltagaforde-energized background pixels.

Electroluminescent display panels are most efficiently and economically constructed with a sharply defined area for displaying the video information. It is desirableto display such information in standard 40-column, 80-column orgraphicdisplayformats. If different display formats are mixed on a screen of data, the sharply defined display area of the electroluminescent panel may cause the display characters at the ends of lines disappearfromthe screen. This problem is particularly likely to occur ifthe EL display panel is receiving data from a device, for example a computer, which operates with CRTs that have a less sharply defined display field.Under said circumstances, an end character of a line can be lost if the display is switched from either a 40-column or graphic display mode to an 80-column display mode within one screen of data.

Accordingly, it is an object ofthe invention to provide an interface circuit for an electroluminescent panel which synchronizes a clock generatorto incoming data signals in order to provide a complete, left justified display of information when display modes are changed in one screen of data.

Afurther object of the invention is to provide such an interface circuit which checks the data mode for each line of the display and adjusts the timing of the interface ci rcuitry to ensure that all data is displayed within the sharply defined display field of the screen.

These and other objects of the inventionwill become apparent from a review ofthe specification which follows and of the drawings which are described hereafter.

SUMMARYOF THE INVENTION In orderto achieve the objects of the invention and to overcome the problems ofthe prior art, the drive circuitforthe direct current electroluminescent display includes row and column drivers arranged in a matrix with an electroluminescentphosphordisposed at crossover points of the matrix. The energization voltages for the drivers ofthe rows and columns are selected to maximize the crossover voltage between an energized row driver and column driver and to thereby increase the brightnessofthe luminescent phosphoratthe crossover point.The energization voltages for the row and column drivers are combined with selected reverse biased de-energization voltages for inactivated pixels so that the differential voltage at such pixels is less than the forming voltage forthe EL panel.

The EL display apparatus ofthe invention includes an interface ci rcuit which detects the beginning of a display portion of each incoming row of character data, synchronizes an internal display clock to this valid data point and adjusts the phase ofthe clockto synchronize with the 80-column, 40-column or graphic display format of the data in the row. The circuit determines the selected displayformatforthe row by detecting the frequency of signals generated for each character of information passed to the display. The circuit shifts the phase ofthe internal clock by 90C if an 80-column format is detected.

The detection of the display fo rmat for each line and the adjustment ofthe internal clockensuresthatall data will be displayed, even ifthe display format is switched from a 40-column or graphics presentation to an 80-column presentation within a frame or screen of data.

BRIEFDESCRIPTION OF THE DRAWINGS FIGURE lisa diagrammatic illustration of a portion of an EL panel and ofthe energization voltages which are employed to light a pixel ofthe panel in a known manner.

FIGURE 2A is a diagrammatic illustration ofthe panel of FIG. 1 energized to provide increased brightness for a selected pixel, but having reduced contrast with respectto a vertical line passing through the pixel.

FIGURE 2B is an illustration of the reduced contrast displaywhich would result from the energized panel of FIG. 2A.

FIGURE 3A is a diagrammatic illustration ofthe panel of FIG. 1 energized to provide increased brightness for a selected pixel, but having reduced contrast between the pixel and the entire EL panel.

FIGURE 3B illustrates the reduced contrast display which would result from the energized panel of FIG.

3A.

FIGURE 4 is a diagrammatic illustration of a portion of an EL panel which is energized in accordance with the invention to provide increased brightness and contrastforan energized pixel.

FIGURES illustrates an alternative embodiment of an energized EL panel with an increased brightness and contrast in accordance with the invention.

FIGURE 6 illustrates yet another alternative embodiment of an energized EL panel with increased brightness and contrast in accordance with the invention.

FIGURE 7A illustrates a character offset which can occurfor a CRT displaywhen the display mode is switched from either the 40 column or graphic display modes to the 80 column display mode.

FIGURE 78 illustrates the loss of a characterwhich can occurwhen the offset characters of FIG. 7A are displayed on an EL panel.

FIGURE 8 isa block diagram ofthe drive circuit for operating an EL panel in accordance with the invention.

FIGURE 9 is a timing diagram of operational signals forthedrivecircuitofFlG.8.

FIGURElOisa logiccircuitdiagramofthedrive circuit of FIG. 9.

FIGURE 11 is atiming diagram of operational signals forthe logic circuit of FIG. 10.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The remaining portion of the specification will describe preferred embodiments ofthe invention when read in conjunction with the attached drawings, in which like reference characters identify identical apparatus.

The apparatus ofthe invention will hereafter be described with respect to a direct current electrol u- minescent (EL) display panel in which phosphor dots of a matrix display are selectively fluoresced to form character images. Such display panels may be produced in accordance with the disclosures of the following patents which are incorporated herein by reference.

Patent No. Issue Date Inventor Title 3,731,353 May 8, 1973 Vecht Method of Making Electroluminescent Devices 4,140,937 Feb. 20, 1979 Vecht et al. Direct Circuit Electroluminescent Devices A preferred process for manufacturing an EL display panel which may be used with the apparatus of the invention is particularly disclosed in a patentapplication of David Glaser, filed July3, 1985, entitled Phosphorescent Material For Electroluminescent Dis play, and assigned to the assignee ofthis invention.

The disclosure of this application is incorporated herein by reference, with the understanding that the disclosure is incorporated for the purpose of indicating the background ofthe present invention.

Fig. is a diagrammatic illustration of a portion of a direct current EL display panel and of apparatus for energizing the panel to form character images. As shown in Fig. lithe panel is comprised of phosphor pixel elements 1-17, which are arranged in a matrix at crossover points of conducting row electrodes 25,27, 29 and column electrodes 19,21 and 23. Elements 1,3 and 5 are arranged to form a top row, elements 7,9 and 11 form a middle row and elements 13,15 and 17 form and end row. The elements 1,7 and 13form a first column, elements 3,9 and 15 form a second column and elements 5,11 and 17 form a third column.

The row electrodes 25-29 are respectively connected to the outputs of associated row drivers R1, R2 and R3. Likewise, the column electrodes 19-23 are respectively connected to the outputs of associated column drivers Cl, C2 and C3.

In orderto facilitate an understanding of the invention, the row and column drivers are shown with associated switches 31-41 which are selectively operated to apply activating signals to the drivers. It should be understood that in actual practice digital circuits are employed to power and operate the drivers to energize the associated column and row electrodes.

The switches are used in Fig. 1 to broadly illustrate the operation of an EL panel, without introducing confusing complexity.

The operation of the panel of Fig. 1 will now be discussed, with the assumption that it is only desired to illuminate the central pixel element9 of the matrix, In operation, selected pixels ofthe panel of FIG. 1 are energized by sequentially scanning rows of the panel with columnar data provided by the drivers C1-C3.

Dataforthetop row25 of pixels 1,3 and 5 is initially provided atthe inputs ofthe drivers C2 and C3. In this example, the switches 37,39 and 41 are connected to ground to indicate that none ofthe pixels 1,3 and 5 ofthefirst row are activated. When the inputs of C1, C2 and C3 are grounded,the inputswitches31 and 33 are grounded and switch 35 of the row driver R1 is closed to apply an activating voltage, for example -60 volts to the row electrode 25. Energization ofthe row driver R1 results in a 60 volt signal being applied to each of the pixels 1,3 and 5. Itwill hereafter be assumed that the panel of Fig. 1 was "formed" with a voltage of approximately 70 volts and thattherefore, as is known in the art, pixels will luminesce only at voltages approaching or exceeding 70 volts. For purposes of discussion, it will hereafterbeassumedthatsignifi- cant luminescence begins at about 70 volts, while little or no luminescence occurs at about 60 volts. These assumptions have proven reasonable fortest EL panels formed at 70 volts. Accordingly, the 60-volt signals applied by the driver R1 do not cause the pixels 1,3and5to luminesce.

The input switch 35 isthen switched to ground to complete scanning of row25andthe switches 37, 39 and 41 are moved to define the columnar data for electrode 27. As indicated previously, it is desired to illuminate the pixel 9. Accordingly, as illustrated in Fig.

1 ,the input of driverC1 is connected to ground,the input of driver C2 is connected to an activating voltage, for example 60 volts, and the input of driver C3 is connected to ground. When the switch 33 at the input ofthe row driver R2 is connected to - 60 volts to scan row 27, 120 volts is applied at pixel 9 and 60 volts is applied at pixels7 and 11. The 120-volt signal at pixel 9 is greaterthan 70 volts and the pixel is therefore caused to luminesce.

The input of row driver R2 is thereafter grounded to discontinue scanning of row 27. When the row electrode 27 is de-energized, the pixel 9 continues to luminescefora predetermined time and therefore provides a persistent image to the eye. Following de-energization ofthe row driver R2, the inputs to the column drivers C1, C2 and C3 are all connected to ground to reflect the data forthe last row 29.

Thereafter, the switch 31 is activated to apply -60 volts to the electrode 29 from the row driver R3. The resulting 60-volt signals at the pixels 13,15 and 17 are insufficentto lightthe pixels.

The scanning cycle forthe rows and columns is repeated as often as is desired to maintain a continuous fluorescence ofthe pixel 9. Alternatively, now columnardata may be definedto illuminate other pixels when the row electrodes 25, 27 and 29 are sequentially energized.

It is known thatthe brightness of luminescence of a phosphor pixel may be increased by increasing the energization voltage applied to the pixel. Fig. 2A illustrates the EL panel of Fig. 1, with an increased voltage of 90 volts applied as a positive energization reference forthe column drivers C1, C2 and C3. The panel of Fig. 2A is scanned in the manner described with respectto Fig. 1 to energize the central phosphor pixel 9. In ordertofacilitate an understanding ofthe invention, the switches which operate the row and column drivers are shown connected in position to scan row 27. As illustrated, when the row driver R2 is activated with -60 volts, and the column driver2 is activated with +90 volts, a differential voltage of 150 volts is provided at the pixel 9.Accordingly, the brightness ofthe pixel 9 is increased with respect to the brightness illustrated with respect to Fig. 1.

However, as illustrated in Fig. 2A, the 90 volt column voltage is also applied to the pixels 3 and 15 which lie in the row ofthe illuminated pixel 9. These 90 volt signals exceed the 70 voltforming voltage and therefore cause the pixels 3 and 15 to fluoresce.

Fig. 2B is a diagrammatic illustration of a larger EL panel in which a central pixel has been energized in the manner disclosed for Fig. 2A. Thus, as shown in Fig. 2B, the central pixel 43 is illuminated. However, a distracting "ghost line" 45 isformed in thevertical column ofthe central pixel 43 by the associated pixels which luminesce in response to the 90-volt signals illustrated in Fig. 2A. The line 45 thus reduces the contrast ofthe pixel 43 and provides an undesirable artifact on the screen. If the voltage for the drivers C1-C3 its further increased, the luminescence ofthe central pixel 43 and the line 45 will increase.The energization scheme of Fig. 2A is therefore ineffective to provide increased brightness and high contrast for the energized pixel.

Fig. 3A illustrates an alternative undesirable ener gization mode. In this mode the energization voltage forthe row drivers R1-R3 is a -90 volts and the energization voltageforthe column drivers C1-C3 is returned to +60 volts. When the panel of Fig. 3 is scanned in the above-described fashion, the central pixel 9 again has a brightness which corresponds to an applied voltage of 150 volts. However, under these conditions, the remaining pixels all have 90 volts suppliedfromthescanning rowdriversRl-R3and therefore luminesce in the manner described with respect to the ghost line 45. The energization of all of the background pixels of Fig. 3A substantially reduces the contrast ofthe central pixel 43, as illustrated for the display of Fig. 38.

Figure 4 illustrates a mode ofenergization in accordance with the invention which allows the central pixel 9, or any other desired pixels, to be energized at 150 volts, without forming a vertical ghost line. As shown in Fig. 4,the row drivers R1-R3 are not returnedto ground after being activated at -60 volts for a scanned row. Instead, inactivated row lines are biased to a positive voltage of, for example, 30 volts. The biased voltage is selected so that 90 volts may be applied by the column drivers C1 -D3 without energizing any-pixel but the desired pixel 9. Thus, in operation, when the first row 25 is scanned by Rl ,the column drivers C1-C3 are grounded and 60 volts is applied to the first row of pixels.When the second row 27 is energized, 60 volts is applied to the pixels 7 and 11 with grounded column drivers C1 and C3 and 150 volts is applied to the pixel 9 with the column driver C2 operated at90 volts. Likewise, when the row driver R3 is activated,The pixels 13, 15 and 17 are energized with 60 volts and therefore do not luminesce.

Itshould be appreciated thatthe desirable high brightness and high contrast of Fig. 4 is achieved by providing a bias voltage forthe row drivers which maintains the voltage of deactivated or background pixels below the forming voltage (70 volts) ofthe panel. Thus, only activated pixels luminesce. The energization scheme of Fig. 4thus eliminates the display problem illustrated in Figs. 2A and 2B.

Fig. 5 illustrates an alternative embodiment ofthe invention wherein the voltage ofthe row drivers R1 -R3 is a -90 volts and a bias voltage of -30 volts is provided forthe column drivers Cl -C3. lfthe panel is scanned in the previously described manner, 150 volts will be applied to illuminate the central pixel 9 and only 60 volts will be applied to the remaining pixels of the display. The energization scheme of Fig. 5thus eliminates the display problem illustrated at Figs. 3A and 3B.

Fig. 6 illustrates an alternative embodiment of the invention wherein bias voltages and increased activation voltages are provided for both the row and column drivers. As shown in Fig. 6, the central pixel 9 is energized with a voltage of 180 volts and will therefore have a brightness that is substantially greater than was provided forthe EL panel of Fig. 1. It should be understood thatthe drivers are biased to ensure that the voltage of background pixels remains belowtheforming voltage of 70 volts.

It should generally be understood that the energiza tion schemes of Figs. 4,5 and 6 may be applied to illuminate any desired numberof pixels in any desired size of EL panel. Moreover, energization and bias voltages otherthan those disclosed may be employed in the manner described without departing from the invention.

It should now be understood that substantially increased brightness may be achieved with no loss of contrast, by providing bias voltages and increased activation voltages forthe drivers of an EL panel. The display of the EL panel may befurther improved in accordance with the invention to avoid display problems illustrated at Figs. 7A and 7B. Fig. 7A illustrates a CRT display which has two lines, the first line displayed in the 40-column or graphic display format and the second line displayed in the 80-column display format. As known by those skilled in the art, the 80-column format provides two characters of 7 pixels each forever 14pixel character of the 40column or graphic displayformats. As shown in Fig.

7A, if the mode of display is switched from 40 columns or graphics to 80 columns on a CRTscreen, it is possiblethatthe 80-column line will be offset by one characterwith respectto the 40-column or graphics line. CRT displays have an "overscan" operation which causes the 80-column lineto be offset by one character ("A") with respectto the 40-column or graphics line.

Fig. 7B illustrates the lines of Fig. 7A as they will appear own an EL display. EL displays do not typically have the overscan capability of a CRT and therefore, the first character ofthe offset 80-column line will be lost. Obviously, this mode of display is undesirable and must therefore be corrected by improved synchronization and mode switching apparatusforthe EL display. The invention therefore includes improved mode switching circuitry which ensures that modes such as 40-column, graphics and 80-column may be switched during a single frame screen, without providing the offset or loss of data illustrated at Figs.

7A and 7B.

Fig. 8 is a block diagram of an embodiment of the improved EL driving system of the invention. The system of Fig. 8 provides a display with high brightness and contrast and furtherchecks the display mode for each line of the display and synchronize the clock of the display to ensure that data is not lost when display modes are changed within a frame or screen of data.

A preferred embodiment of the EL display panel of the invention has been implemented with an Apple llc computer 51 as a display control. The system utilizes an interface circuit 53 which receives standard clock, data and timing signals ofthe Apple llccomputer, generates 4-phase data and clock signals and derives horizontal and vertical synchronization signals for operating the EL display. The interface thus converts Apple lic signalswhich are suitable for operating a CRTto the signals required to operate an EL display.

In ordertofacilitate an understandingofthe invention, only a few vertical and horizontal lines of the EL display matrix are illustrated in Fig. 8. Itshould generally be understood that a preferred embodiment of the invention utilizes 560 vertical column electrodes and 192 horizontal row electrodes. Also, each charac ter displayed on the EL panel has a predefined pixel width. Thus, each character in the 40-column or graphic display modes is 14 pixels wide and in the 80-column mode each character is 7 pixels wide.

With reference to Fig. 8, the computer 51 passes 560 bits ofserial data for each row of the display to the interface circuit 53. The interface 53 receives the serial data in groups of bits and transmits each ofthe 4 bits to an associated column shaft register. Thus, for example, bit 1 ofthe initial 4 bits of serial data is transmitted as DATA1 to a shift register 55, bit 2 is transmitted as DATA2 to a shift register 57, bit 3 is transmitted as DATA3 to a shift register 61. When the next group offou r serial bits is receivedfrom the computer, bit 5 is passed to register 55, bit 6 is passed to register 57, bit 7 is passed to register 59 and bit 8 is passed to register 61.The serial data is transmitted until each shift register has received 140 bits, for a total of 560 bits received.

With reference to the timing diagram of Fig. 9, when all 560 bits for the first horizontal row are received at 63, the interface 53 generates a derived vertical synchronization signal VSYNCD 65 and a derived horizontal synchronization signal HSYNCD 67 which initiate shifting of data into the shift registers of the display and control the application of powerto the column and row drivers.

Before proceeding to a detailed discussion ofthe operation of the circuit of Fig. 8, it should be understood that all of the circuit is supported on a single substrate board. Accordingly, the components ofthe circuit have been arranged to provide for a balanced transmission of signals on the board. Thus, thefour-phase column shift registers 55,57,59 and 61 are disposed attop and bottom positions on both sides ofthe board and the associated column electrodes are interleaved. Also, row shift registers 69 and 71 are disposed at opposite end positions on both sides ofthe board and their associated electrodes are interleaved.

With reference to the timing diagram of Fig. 9, when 560 data bits for the 560 pixels of the first horizontal line are received at 63, the derived horizontal sync signal HSYNCD 67 is applied to a power control circuit 81 which begins ramping positive and negative high voltage power respectively to the column drivers and row drivers. In a preferred embodiment ofthe invention, column drivers are manufactured by Texas Instruments and are generally designated SN75555, SN75556 and row drivers are generally designated SN75551 and SN75552. The power ramping rate for these drivers should not be greaterthan 50 volts per microsecond. Thus, with reference to Fig. 9,the leading edge of each HYSYNCD signal will cause the positive high voltage (for example 90 volts) for the column driversto beginto rampdoown andthe negative high voltage (for example -60 volts) of the rowdriversto begin to ramp upwardly.

The leading edge of the HSYNCD signal is delayed by a delay circuit 85 and is applied to latch the data of the shift registers 55-61 into respective latches 73-79 when the power of the column drivers has been sufficiently reduced to avoid an undersirable current surge ofthe drivers in response to changing data.

Thereafter, beginning on the trailing edge of the HSYNCD signal, the powerforthe column drivers is increased to its maximum positive voltage and the powerforthe row drivers is decreased to its maximum negative voltage.

It should generally be understood that the circuit of Fig. 8 operates in accordance with the improved energization scheme of Fig. 4. Thus, with reference to Fig. 9, row power is energized from -60 volts to +90 volts. As previously discussed with respect to Fig. 4, this energization scheme ensures that pixels will be energized with a total voltage of 150 volts, without forming a vertical ghost line. The embodiment of Fig. 4 has been successfully implemented with the particular designated Texas Instruments row and column drivers.

Asshown in Fig. 9, afterthefirst line of data is displayed, successive lines of data are sequentially received at 64 and 66 and successive HSYNCD pulses 68 and 70 cause the lines to be sequentially displayed.

Although Fig. 9 illustrates a timing diagram of signals for onlythe first three lines of the matrix of Fig. 8, it should be understoodthatthesametiming is repeated to sequentially energize the 1 92 rows of the matrix. Thereafter, energization of the EL panel is repeated from line 1.

The HSYNCD and VSYNCD pulses are also applied to the row shift registers 69 and 71 to scan the rows of the matrix. Thus, with reference to Fig. 9, when the first line of 560 pixels of data is received in the shift registers 55-61 at 63, the VSYNCD pulse 65 is applied as a data input to both ofthe shift registers 69 and 71.

The HSYNCD pulse 67 and the successive HSYNCD pulses are applied to a divider 87 which divides the frequency ofthe pulses by a factor of two. The output of the divider is applied to clock inputs of the left and right shift registers 69 and 71. Thus, the high data of the VSYNCD pulse 65 is simultaneously gated by the leading edgeofthe divided HSYNCDsignal 67 into the left and right shift registers. The divided HSYNCD signal is also applied to a blanking lead ofthe right shift register 71 and the inverse ofthis signal (at the outputofan inverter89) isappliedtoa blanking input ofthe left shift register 69.As a result ofthe reverse polarity ofthe blanking signals,theleftand right row drivers are alternately activated to sequentially scan the rows ofthe matrix. Successive divided HSYNCD pulses thereafter gate the initial data bit of the shift registers 69 and 71 through the shift registers to sequentially activate the row driverfor each line.

Fig. 10 illustrates a logic circuit diagram ofthe system of Fig. 8. Fig. 11 illustrates a timing diagram of operational signalsforthe logic circuit of Fig. 10. As shown in Fig. 10, the Apple llccomputer5l generates serial video data at its output 91, 14 MHz clock signals at its output 93 and timing signals WMDW, LDPS and SYNC at respective outputs 95,97 and 99.

The LDPS signal is a negative load pulse which is generated each time that the digital bits (pixels) of a character are passed from the serial output 91 ofthe computer. Thus, if the computer is generating data in the 80-column display mode, each character has7 pixels of data and an LDPS pulse is therefore generated for each 7 pixels. However, if the computer is generating data in the 40-column or graphic display mode, each character contains 14 pixels or bits of data.

Accordingly, in the 40-column or graphic mode the LDPS load pulse is generated once for each 14 pixels transmitted atthe serial output 91. Thus, it should be understood that the frequency of the LDPS load pulses generated by the computer 51 indicates the selected display mode. Relatively high frequency LDPS load pulses indicate operation in the 80-column display mode, while lower frequency pulses indicate operation in the 40-column or graphic display modes.With reference to Fig.11, the WNDW signal is comprised of horizontal blanking pulses 101 (examples 101 a-c are illustrated) which each precedethetransmission of a row of data, intervals 106 (examples l06a-care illustrated) which each contain a row of data, and a vertical blanking interval 103 which is generated after the last row of a frame or screen of data. Thus, as shown in Fig. 1 l,the interval 106b on the leftofthe timing diagram precedes the vertical blanking interval 103 and therefore contains the last row of data for a frame or screen.On the other hand, the interval 106c on the right ofthetiming diagram follows the interval 103 and therefore contains thefirst row of data for a following frame or screen.

The LDPS load pulses are continuously generated during the WNDW signals. Thefirst LDPS load pulse which occurs after the trailing edge ofWNDW signals generally designates the beginning of a display portion of each row of data contained within the respective following intervals 106. The timing of this first LDPS pulsethis indicatesa startpointwithin an interval 106for locating valid character data which must be displayed. Also, a horizontal composite sync pulse 102 of the computer is generated for each horizontal blanking pulse 101. Sixty-seven ofthe pulses 102 and four portions of 100 ofavertical sync pulse are generated during the vertical blanking interval 103.

TheWNDWand LDPSsignalsareemployedto detect the beginning of valid data, that is, the beginning of each row of data for the EL display. The signals are also used to adjustthetiming ofthe clock for the EL display in accordance with the operational display mode.

With reference to Fig. 10, a four-bit shift register 107 receives serial row data from the computer 51. The shift register 107 is clocked by the first four clock pulses of the 14MHz clock at port 93 of the computer.

After the four bits of data are received by the shift register 107, they are shifted in paralleltoafour-bit latch 109 and are applied from this latch to the four shift registers 55,57,59 and 61 described with respect to Fig. 8.

Flip-flops 111 and 113 divide the 14MHz clock of the computer by four. The resulting 3.5 MHz clock gates successive groups offour bits of serial data into the shift registers 55-61 of Fig. 8.

The3.5 MHz clock mustgate intothe column shift registers ofthe display only the incoming serial character data which is to be displayed. Accordingly, a JKflip-flop 115 receives the WNDW signal at its data inputs and receives the LDPS pulses at its clock input.

The flip-flop 115 generates a "Data Valid" signal to indicate the point in time atwhich valid serial character data is being generated for display at the port 91 ofthe computer 51. With reference to Fig. 11, the Valid Data indication is defined as true atthetime ofthe first LDPS pulse following the trailing edge of WNDW. The Valid Data signal is generated at the output ofthe flip-flop 115 when LDPS clocks the flip-flop on thetrailing edge of WNDW. The output is applied to an adjacentflip-fiop 117 to synchronize the Data Valid signal with respect to the 3.5 MHz clock of the dividers 111 and 1 1 3.Thus, the output of the 3.5 MHz clock is applied to the clock input ofthe flip-flop 117 and the Data Valid signal oftheflip-flop 115 is applied to the data inputs ofthe flip-flop 117. The flip-flop 117 generates a Data Valid signal which is synchronized to the 3.5 MHz clock.

The synchronized Data Valid signal ofthe flip-flop 117 isappliedto enable a NAND gate 1 19 so that the gate passes the 3.5MHz clock signals which occur when data is valid. These clock signals are then passed to gate four bits of data from the shift register 107 to the latch and to gate the data from the latch 109 into the shift registers 55,57,59 and 61 of Fig.8.The Data Valid signal thus applies the 3.5 MHz clock signalsto gate into the shift registers ofthe EL display only the character data which must be displayed.

In orderto achieve proper gating of data, the phase ofthe43.5 clock must be adjusted, depending upon the data display mode. Also, in order to avoid the data loss associated with the mode switching problem of Figs. 7A and7B. the 3.5 MHz clock must be synchronized and the Data Valid condition must be checked for every row of data. Moreover, the 3.5 MHz clock must be synchronized with respect to the display mode priortothe detection ofthe Data Valid condition and the consequent gating of valid character data.

In the system of Fig. 10, a counter 121 detects the display mode of data during horizontal synch pulses HSYNCD of Fig. 9. The HSYNCD pulses correspond to horizontal sync pulses of the computer and are generated in a manner to be described hereafter. It is known thatthe pulses HSYNCD have a fixed pulse width of 56 pulses ofthe 14MHz clock. Accordingly, if eight LDPS pulses are counted by the counter 121 within a HSYNCD pulse, the system is operating in the 80-column mode. Alternatively, if only four LDPS pulses are detected within the HSYNCD pulse, the system is operating in the 40-colu m n or graph ic display mode.

A circuitto be described in detail hereafter detects the horizontal sync pulses ofthe computer and generates corresponding derived pulses HSYNCD for the clearand load inputs ofthe counter 121. When the HSYNCD pulse is not present, the counter is maintained in a cleared state. However, when the HSYNCD pulse is present, LDPS pulses are applied to the clock inputofthe counter 121 and the counterthen counts thenumberofpulseswhichoccurduringthe HSYNCD pulse. If a count of eight is detected, the QD output of the counter 121 generates a high signal which is applied to a JKflip-flop 123 that is clocked bythe 14 MHz clock., TheJKflip-flop 123 thus provides a signal at its output that is delayed by one 14 clock cycle from the trailing edge of the HSYNCD pulse.The output oftheflip-flop 123 and the HSYNCD pulse itself are applied to a NOR gate 125 and the output ofthe NOR gate 125 is appliedto preset inputs of the flip-flops 111 and 113 which generatethe3.5 MHz clock. Thus, the 3.5 MHz clock is synchronized with respect to the HSYNCD pulse anda one pixel adjustmentinthe phase ofthe3.5 MHz clock is made if the system is operating in the 80-column display mode.

It should now be appreciated that, if the system is operating in eitherthe 40-column orgraphic display modes, the OD output of the counter 121 remains low and the HSYNCD pulse is applied to the preset inputs of the 3.5 MHz clock flip-flops to synchronize the clock signal so thatfour-bit data groups are clocked in the 40-column mode. Alternatively, if the system is operating in the 80-column mode, the counter 121 operates in association with the J K fl ip-flop 123 to preset the 3.5 MHz clock for an additional cycle ofthe 14 MHz clock and therefore shifts the phase ofthe3.5 MHz clock by 90" two synchronize the clock with serial data arriving in the 80-column display mode.

The synchronized 3.5MHz clock signal clocks the flip-flop 117 and thus synchronizesthe Data Valid signal to the four-bit gating scheme ofthe system of Fig. 10. The synchronized Data Valid signal is then used to control the transmission of 3.5 MHz clock gating signals to the column shift registers of Fig. 8.

The detection of the Data Valid point for incoming data from the computer 51 and the adjustment of the synchronization ofthe 3.5 MHz clock are required to ensure that the EL display will fully display 40-column, 80-column and graphics data andwilltherefore avoid the display problem of Figs. 7A and 7B.

In the graphics mode, delayed LDPS pulses are occasionally generated to provide colordisplaysyn- ch ronization. These delayed pulses do not interfere with the timing of the circuit of Fig. 10 because the HSYNCD pulse which synchronizes the 3.5 MHz clock is delayed by the same amount and therefore compen satesforthe momentaryphaseshiftof LDPS.

lftheApple lIc computer was designed to operate with an EL display, the computer would generate the vertical synchronization and horizontal synchronization pulses VSYNCD and HSYNCD illustrated at Fig. 9.

These pulses could then be applied directly to operate the above-described circuitry of Figs. 8 and 10.

However,the Apple lIc computerwas originally designed to operate with CRT displays. This operation was facilitated by use of SYNC signal which is comprised of the Exclusive Or ofthe vertical and horizontal sync pulses ofthe computer. In orderto operate the EL display horizontal sync pulses must be extracted from the SYNC signal and an EL vertical sync pulse VSYNCD must be generated as illustrated in Fig. 9.

With reference to Figs. 10 and 11, a counter 130 detects the vertical blanking signal 103 of the SYNC signal. The vertical blanking signal is differentiated by utilizing the Data Valid signal of theflip-flop 115 to resetthe counter 130 and thereafter counting the numberof SYNC pulses which occurbeforethe next resetting of the counter.With reference to Fig. 11, it can be seen that the counterwill be reset by the Data Valid signal ofthe data pulse lû6bt after only one SYNC pulse 102 is counted H'owever,foF following the resetting of the counter 130, a seriesof 71 SYNC pulses will be counted during the vertical blanking signal 103 before the counter is reset by the Data Valid signal ofthe data pulsel06cfollowingthevertical blanking signal.

Thus, in the presence of a vertical blanking signal, the counter 130 will count more than one SYNC pulse and will in fact count 71 SYNC pulses.

The NOR gates 131 and 133 applythe outputs of the counter 130 to force a high signal atthe outputs a NANDgate 135 which indicatesthatavertical blanking signal has been detected. The output of the NAND gate 135 is applied to a JKflip-flop 137 which is in turn clocked bythetrailing edgeoftheWNDWsignal.The flip-flop 137 thus acts as a delay which will cause the derived vertical sync pulses VSYNCD to be generated at the 0 output ofthe flip-flop immediately following the end of each vertical blanking interval 103.The derived vertical sync signal VSYNCD is applied by means of an optical coupler 139 to the data inputofthe left and right shift registers 69 and 71 of Fig. 8.

The signal ofthe NAND gate 135 is also applied to the data inputofaJKflip-flop 141 which is clocked by the SYNC signal. Theflip-flop 141 operates inconjunction with gates 143 and 145 to remove from SYNC the computer'sfour portions 1 00 of the compositevertical sync pulse and 65 of the 71 composite vertical and horizontal sync pulses ofSYNCwhich occurduring the vertical blanking interval 103. The remaining 194 pulses are derived horizontal synchronization pulses HSYNCD which are generated at the outputs of inverters 147 and 149 As discussed above, the HSYNCD pulses are applied to the counter 121 to detect the operational mode ofthe display.The HSYNCD pulses are also applied to optical couplers 151 and 153 which respectively control associated high power row driver transistors 155 and 157. With reference to Fig. 9, the leading edge of the HSYNCD pulse occurs at a time when the transistor 157 has previously charged the row power drivers to a negative 60 volts. The leading edgeoftheHSYNCDpulsethereforturnsonthe transistor 155 and thus begins to ramp discharge the -60 volts to a reverse supply voltage of, for example, +30 volts. At the trailing edge of the HSYNCD pulse, the transistor 155 is turned off and the transistor 157 is turned on to again begin the ramp charging of row powerfrom +30 volts to a -60 volts.

The HSYNCD pulse is also applied to control high powertransistors 159 and 161 to ramp up and ramp down powerforthe column drivers. In operation, the leading edge ofthe HSYNCD pulse occurs at a time when thetransistor 159 has charged up the column driverto power +90 volts. When the leading edge of HSYNCD occurs, the transistor 159 is turned off and the transistor 1611 is turned onto begin ramping the 9Q volt signal to ground. Atthetrailing edge ofthe HSYNCD signal, the transistor 161 is turned off and the transistor 159 isturned on to begin ramping up the column driver power from 0 volts to +90 volts.

It should be understood that the time delay required for ramping up and ramping down the power signals is determined bythe resistors 163, 165,167 and 169 of the respective transistors 155,157,159 and 161 These resistors operate in conjunction with EL panel capaci tance to define RCtime constants which provide the required delay for ramping power up and down.

As previously discussed for Fig. 8, the HSYNCD pulse is also divided by two by a divider 87 and is then applied to control clocking and blanking forthe left and right row shift registers. Also as discussed for Fig.

8, the leading edge of each HSYNCD pulses is delayed (by gates 180,182,184and 186) and is applied to enablethecolumn latchesto receive data.

It should now be appreciated that a driver circuit has been disclosed for operating a high luminescence and high contrast EL display in accordance with clock and timing signals derived from an Apple llc computer.

The derived signals have further been applied to adjust the timing of the system to display data in the 40-column, 80-column and graphics display modes on a row by row basis.

Although a particular preferred embodiment of the EL display driver circuit of the invention has been disclosed, it should be understood that other circuits and components may be used to achieve the objects of the invention, without departing from the spirit of the invention. Th us, the invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the claims ratherthan bythe foregoing description. All changes which come within the meaning and range ofthe equivalents ofthe claims are intended to be embraced therein.

Claims (21)

1. An electroluminescent display, comprising: a pluralityofconducting rowandcolumn electrodes disposed in intersecting relation to form a matrix; a plurality of phosphor pixel elements disposed at the points of intersection ofsaid electrodes; means for sequentially scanning each one of said row electrodes with a redefined row energization voltage and for simultaneously applying a predefined de-energization row voltage to the row electrodes which are not being scanned;; meansforapplying a selected pattern of column energization and column de-energization voltages to said column electrodesforthescan of each row electrode, the pixels ofthe scanned row in the energized columns receiving a differential voltaage which exceeds a predefined minimum fluorescence voltageforfluorescingthe pixels, all other pixels having a differential voltage less than said minimum fluorescence voltage so that said other pixels are not caused to fluoresce; and means for defining at least one of said energization voltages as equal to or greaterthan said minimum fluorescence voltage.

2. Thedisplayofclaim 1, further including means for defining said minimum fluorescence voltage as the forming voltage for said display.

3. Thedisplayofclaim l,whereinsaidde- energization row voltage is a reverse bias voltage which produces with the column energization voltage a differential voltage less than said minimum flouresc ence voltage.

4. The display ofclaim 1, wherein said column de-energization voltage is a reverse bias voltage which produces with the row energization voltage a differential voltage less than said minimum fluorescence voltage.

5. A method for increasing the brightness and contrast ofan electroluminescent display wherein a plurality of conducting row and column electrodes are arranged in intersecting relation to form a matrix, a plurality of phosphor pixels are disposed at the points of intersection ofthe electrodes and row and column drivers selectively apply energizing voltage to elec trodesto cause selected pixels to luminesce, the method comprising the steps of:: defining a row energization voltage for row electrodes and a column energization voltageforcolumn electrodes which when combined produce a differential voltage which exceeds a predefined minimum voltage required to cause a pixel to luminesce, at least one ofsaid energization voltages being equal to or greater than said predefined minimum voltage; defining a row de-energization voltage for row electrodes which when combined with the column energization voltage produces a differential voltage that is less than said predefined minimum voltage; defining a column de-energizationvoltagefor column electrodes which when combined with the row energization voltage produces a differential voltage that is less than said predefined minimum voltage; applying the rowenergization voltage to at least one selected row electrode;; applying the row de-energization voltageto the remaining row electrodes; applyingthecolumn energization voltage to at least one selected column electrode for illuminating the pixels atthe point of intersection ofthe energized row and column electrodes; and applying the column de-energization voltagetothe remaining column electrodes.

6. The method of claim 5, wherein said step of defining row and column energization voltages includesthe step of defining said minimum voltage as the forming voltage forthe electroluminescent display.

7. The method of claims 5, wherein at least one of said steps for defining de-energization voltages includesthe step of defining a nonzero de-energization voltage.

8. The method of claim 5, wherein said step of defining row and column energization voltages includes the step of defining such voltages of opposite polarity and wherein at least one of said steps of defining de-energization voltages includes defining a de-energization voltage for an electrode which is opposite in polarity to the energization voltage for the electrode.

9. In a computerdisplaysystem ofatypewhich transmits successive frames of data, each frame having a plurality of rows of character data, and generates a window signal that includes a horizontal blanking interval for each row of transmitted character data and a vertical blanking interval for each frame of character data, a load signal for each character which is transmitted and a horizontal sync signal for each row of displayed character data, the improvement comprising:: an electroluminescent display panel, including (a) a pluralityofconducting row and column electrodes disposed in intersecting relation to form a matrix; (b) a plurality of phosphor pixel elements disposed at the points of intersection of said electrodes; (c) means for sequentially scanning each one of said row electrodes with a predefined row energization voltage and for simultaneously applying a predefined de-energization row voltage to the row electrodeswhich are not scanned;; (d) meansforapplying a selected pattern of column energization and column de-energization voltages to said column electrodes forthe scan of each row electrode, the pixels ofthe scanned row in the energized columns receiving a differential voltage which exceeds a predefined minimum fluorescence voltage forfluorescing the pixelstoform characters corresponding to a display portion of said character data, all other pixels having a differential voltage less than said minimum fluorescence voltage so that said other pixels are not caused to fluoresce; and (e) meansfordefining at least one of said ener gization voltagesas equal to orgreaterthan said minimum fluorescence voltage; clock means for generating clock pulses; means for detecting the beginning of each row of a display portion of said character data; means for synchronizing the clock means atthe beginning of the display portion of each row of character data and adjusting the phase of said clock means in responseto the detected display mode for the row; and means responsive to said clock meansforforming said pattern of column energization and de-energization voltages corresponding to the display portion of each row of character data and displaying the characters of each row in the detected display mode fortherow.

10. The system of claim 9,further including means fordefiningsaidminimumfluorescencevoltageasthe forming voltageforsaid display.

11. The system of claim 9, wherein said deenergization row voltage is a reverse bias voltage which produces with the column energization voltage a differential voltage less than said minimum fluorescence voltage.

12. The system of claim 9, wherein said column de-energization voltage is a reverse bias voltage which produces with the row energization voltage a differential voltage less than said minimum fluorescence voltage.

13. The system of claim 9, wherein said means for detecting the beginning of the display portion of a row of character data includes means for detecting the trailing edge of said window signal and for recognizing the beginning ofthe display portion upon detection ofthe next following load signal.

14. The system of claim 9, wherein said means for detecting the display mode includes means for differentiating the 80-column mode from the 40 column or graphic display modes.

15. The system of claim 9, wherein said means for detecting the display mode includes means for counting the number of load signals which occur during a horizontal sync signal for a row of data and for determining the display modefrom said number on a row by row basis.

16. The system of claim 15,whereinacountof eight load pulses designates the 80-column display mode.

17. The system of claim 15, wherein a count of less than eight load pulses designates the 40-column display mode and the graphicdisplay mode.

18. The system of claim 9, wherein said means for detecting the display mode includes meansfor detecting the frequency ofthe load signals which occur during a horizontal syne signal and for determining the display mode from saidfrequency.

19. Thesystemofclaim 18,includingmeansfor identifying the 80-column display mode when the higher of two preselected frequencies is detected and for identifying the 40-column and graphic display modes when the lower of said two preselected frequencies is detected.

20. The system of claim 9, wherein said means for synchronizing includes means for synchronizing said clock meansatthe end of said horizontal syncsignal if a 40-column or graphic mode is detected and for synchronizing said clock means one pixel afterthe end of said horizontal sync signal if an 80-column mode is detected.

21. The system of claim 9, wherein said means for synchronizing includes means for synchronizing said clock means to the beginning ofthe display portion of a row ofcharacterdata ifa40-column orgraphic mode is detected and for synchronizing said clock means to the beginning ofthe display portion of a row of character display data and additionally shifting the phase of the clock means by 90 if an 80-column mode is detected.