GB2175110A - Memory addressing circuit - Google Patents

Abstract

A memory 40 is connected to a data bus RDAT and to an address bus RA. Access to the memory 40 from a first multi-bit bus SSB is controlled by a decoder and logic unit 43, both data and addresses being couplable to the buses RDAT and RA respectively from the first bus SSB. Access from the first bus SSB is denied by signals NEMFIBZ and XNBZ(-) from a second multi-bit bus MFB when the second bus MFB is busy. Data can be read out of one region of the memory 40 onto the bus MFB and written into other regions of the memory 40 from the bus MFB at addresses generated by counters 52 and 53, adder 54, and a latch 51 which is loaded with a number from the bus MFB. The counters receive clock pulses either from the bus MFB in the case of writing or from a slave state machine 48 in the case of reading. The region read out or written into is determined by the number in latch 51. The slave state machine 48 stops when part of the address generated matches a limit stored in a register 45. The circuit may include a master state machine 46 which becomes active on receiving a signal SOF INT decoded from signals supplied by the first bus SSB and which when active generates a predetermined series of the numbers which are loaded into the latch 51 and placed on the second bus MFB. <IMAGE>

Description

SPECIFICATION Memory processing circuit This invention relates to memory addressing circuits.

According to the present invention there is provided a memory addressing circuit comprising a memory connected to a data bus and to an address bus and to means for controlling reading from and writing to the memory respectively to the data bus and from the data bus at addresses in the memory determined by address signals on the address bus, first and second buses coupled to the data bus, the said first bus also being coupled to the address bus, and means for generating address signals on the address bus in response to control signals supplied to the address generating means from the said second bus.

In a preferred embodiment of the invention, the memory a memory is connected to a data bus and to an address bus. Access to the memory from a first multi-bit bus is controlled by a control decoder and logic unit, both data and addresses being couplable to the data and address buses and respectively from the first bus. Access from the first bus is denied by signals from a second multi-bit bus which are generated when the second bus is busy. Data can be read out of one region of the memory onto the second bus and written into other regions of the memory from the second bus at addresses generated by two counters, a full adder, and a latch which is loaded with a number from the second bus. The counters receive clock pulses either from the second bus in the case of writing data into the memory, or from a slave state machine in the case of reading data out of the memory.The region read out or written into is determined by the number supplied to the latch. The slave state machine stops when part of the address generated matches a limit stored in a limit register, a match being indicated by a limit comparator. The circuit may include a master state machine which becomes active on receiving an interrupt signal decoded from signals supplied by the first bus and which when active generates a predetermined series of the numbers which are loaded into the latch and placed on the second bus.

The invention will now be described by way of example with reference to the accompanying drawings in which: Fig 1 is a block diagram of an aircraft simulator embodying the invention, Fig 2 is a block diagram of an interface used in the simulator of Fig 1, Figs 3 to 20 are more detailed block diagrams of parts of the interface of Fig 2, Figs 21 to 28 are circuit diagrams of parts of the interface of Fig 2, and Figs 29 and 30 are flow diagrams of the operation of two parts of the interface of Fig 2.

Fig 1 of the drawings illustrates schematically an aircraft simulator in which the data processing hardware is divided into five modules, referred to herein as major functions, which are coupled, for the exchange of shared information, by a bus MFB, referred to as the major function bus, and is serviced by a management computer MC coupled to each of the five modules by two local area networks (LANs), referred to as the management link ML and the debug link DL.

The five data processing modules are the flight major function 11, the engines major function 12, the navigation and communications major function 13, the systems major function 14, and the instructor operation station major function 15.

The flight major function 11 receives input data from the simulator manual controls input and output 16 which includes a control column, pedals, nosewheel steering handle and toe brakes provided for a trainee pilot in a simulated aircraft cockpit. The simulator manual controls input and output 16 includes apparatus which converts the movements of the hand and foot controls (not shown) into digital data transmitted over a respective stand alone bus SAB to a respective stand alone interface SAI in the major function 11.

In response to this manual controls data and to other data the flight major function 11 generates motion control output data which it supplies through another respective stand alone interface SAI and stand alone bus SAB to a motion output 17 in the form of an electro-hydraulic apparatus for moving the simulated cockpit in a manner simulating the effect of operation of the hand and foot controls and other circumstances such as take off, landing, acceleration and air turbulence. The cockpit together with the motion output 17 constitute a motion cabinet. The manual controls input and output 16 also includes mechanical actuators for varying the resistance of or moving the control column and other mechanisms in response to computed flight or other conditions.

To simulate the charging scene that would present itself to the pilot flying a particular course from take off at one known airport to landing at another known airport, a visual display replaces the windows in the simulated cockpit and is driven by a visual field output 18 which is a moving image display generator which receives from the flight major function 11, acting as host computer, aircraft position and attitude data, which is transmitted to the visual field output 18 by a third stand alone interface SAI over a third stand alone bus SAB.

Apparatus which can be used as the simulator manual controls input and output 16, the motion output 17 and the visual field output 18 is well known to those skilled in the art and will therefore not be described in more detail.

The engines major function 12 generates data representing the response of the engines of the simulated aircraft to input from a throttle lever (not shown) and various switches provided in the cockpit, and to data representing factors such as atmospheric conditions and malfunctions of equipment systems serving the engines. The throttle lever is coupled to a position transducer (not shown) connected to an internal input/output unit 19 of the major function 12. The various switches and associated visual indicators are coupled to the engines major function 12 at the internal input/output unit 19 and, if necessary, at an external input/output unit 20 coupled to the major function 12 through a bus LB, referred to herein as a linkage bus, to a function control and interface unit FCI.The data generated by the major function 12 includes data representing engine conditions such as thrust gas temperature, rate of fuel use and oil pressure, for which indicators may be provided to be driven from the internal input/output unit 19.

Data representing equipment systems malfunctions affecting engine operation are supplied to the engines major function 12 by the systems major function 14 during a regular updating process involving all five major functions 11 to 15 and utilizing the major function bus MFB. Another indicator driven by the unit 19 shows changeover from battery to generator at a computed appropriate rate of engine operation.

The navigation and communications major function 13 receives from the flight major function 11, during the regular updating process via the major function bus MFB, three dimensional coordinate values specifying a computed aircraft position in a coordinate system having its origin at an arbitrary starting point, and generates from this the simulated aircraft position in longitude, latitude and height. The flight major function 11 also supplies, in the same way, aircraft attitude data.

The navigation and communications major function 13 includes an internal input/output unit which drives indictors representing primary navigation display instruments such as an artificial horizon, an attitude and direction indicator, and magnetic compasses. Other indicators driven by the internal input/output unit may include indicators for showing aircraft position relative to radio beacons, data for the radio beacons being down loaded at suitable times from the management computer MC via the management link ML to a management link processor MLF in the major function 13, and indicators showing aircraft position relative to a landing radar glide path at a destination airport. Simulated VHF and UHF communications equipment is provided in the cockpit and is coupled to the navigation and communications major function 13 at the internal input/output unit.If necessary, an external input/output unit may be provided coupled to the function control and interface FCl of the major function 13 through the linkage bus LB. The major function 13 generates background noise and chatter for the simulated communications receivers which may, for example, relay pre-recorded air traffic control messages or live messages simulating various situations from an instructor at the instructor operation station (IOS) major function 15.

In an alternative configuration of the system, the navigation and communications major function 13 includes a stand alone interface SAI which drives the visual field output 18, instead of the Itter being driven from the flight major function 11. This alternative may be preferred since the visual field output 18 uses the latitude and longitude data generated by the navigation and communications major function 13. In the present example, there is a slight delay in the availability of the current latitude and longitude data to the visual field output 18 since this data is transferred to the flight major funciton 11 from the navigation and communications major function only during the regular updating process via the major function bus MFB.

The systems major function 14 generates data representing the behaviour of equipment systems such as hydraulic and/or electrical systems for operating control surfaces of the aircraft, landing gear, cabin pressurisation, deicing, powered movable military equipment, and pumps, and, if not generated by the engines major function 12, the fuel system. This major function 14 has an internal input/output unit and, if necessary, an external input/output unit which is coupled through a linkage bus LB to its function control and interface FCI, which read inputs from the switches (manual circuit breakers) associated with the equipment systems, and drive indicators showing conditions of these systems.In generating the data representing the behaviour of the equipment systems, full amount is taken of the known characteristics at switch on and switch off of the real systems which are being simulated.

The IOS major function 15 includes a stand alone interface SAl coupled through a stand alone bus SAB to an instructor's visual display unit and terminal 21 to allow an instructor to alter data being processed by any of the four other major functions 11 to 14. An internal input/output unit is included in the major function 15 to allow indicators showing operating conditions of the system to be driven and to allow inputs such as recorded or line messages to be entered. An external input/output unit may also be provided if necessary, coupled through a linkage bus to the function control and interface FCI of the major function 15.

An instructor can also communicate with the management computer MC from the terminal 21 via a management link processor MLP of the major function 15 connected to the management link ML, for the purpose of commanding data to be unloaded from disk at the management computer MC and loaded into any designated major function through the management link ML, each major function including a respective management link processor MLP connected to the management link ML.

The management computer MC, in addition to having a disk controller 22 controlling two disk drive units 23, and two local area network controllers 24 and 25 controlling input to and output from the computer ML to the management link ML and the debug link DL, includes a memory 26, a central processor unit 27 and a main bus 28 coupling all these elements as indicated. A visual display unit and terminal 29 is provided for direct communication with the CPU 27, and a line printer 30 may be driven from the CPU 27. Further terminals 31 may be coupled to an input/output unit 32 in the computer MC.

Programs for the major functions 11 to 15 are stored on disk at the drive units 23 and are loaded from disk into the major functions 11 to 15 before the simulator is used by a trainee pilot and an instructor to carry out a simulated flight from a defined starting point to a defined end point in a defined aircraft.

The management link ML is used for such loading. The terminal 29 is used for controlling such loading operations, and can be used for amendment of existing programs and creation of new programs. For debugging programs under test, i.e. when loaded into the major functions 11 to 15, the terminal 29 can communicate with any major function through the debug link DL which is connected to a respective debug link processor DLP in each major function. To allow several operators to carry out debugging the additional terminal 31 may be utilized.

Each of the major functions 11 to 15 includes a central processor unit 33 with an associated memory unit 34 accessed by the CPU 33 through a local memory bus LMB.

Alternatives to this arrangement are that the CPU 33 accesses the memory unit 34 through a main bus SSB, referred to herein as the subsystem bus, present in each major function, or that the CPU 33 includes sufficient memory for the memory unit 34 to be dispensed with.

The CPU 33 may consist of six microprocessor cards which are connected through the local memory bus LMB to six memory cards.

A function control and interface FCI is provided in each major function and serves to generate clock pulses and to perform bus arbitration and bus termination for the respective sub-system bus SSB. It includes a block of RAM and a configuration EPROM for use by the management link processor MLP and the debug link processor DLP. For input and output functions, the FCI includes differential buffers coupling a subset of the sub-system bus SSB to input and output circuitry.

Each stand alone interface SAI includes a microprocessor allowing intelligent, i.e. programmed, interfacing between the respective major function and the external unit coupled by the respective stand alone bus SAB.

The internal input/output units in each major function consist of a number of circuit cards each having a microprocessor for intelligent interfacing.

In other embodiments similar to the present example, two major functions may require to work closely together, and for this purpose may each include a stand alone interface SAI, these two interfaces SAI being connected in a back-to-back configuration to allow direct communication between the two major functions.

The memory unit 34 of each major function is initially loaded with a program for that major function from the management computer through the management unit ML, and has capacity for all the computing required to be carried out by the major function, i.e. the memory unit 34 is the data processing memory of the major function.

Some of the data generated by each major function is needed by one or more of the other major functions. The total of such shared data is referred to herein as the total cross talk data. Each major function is provided with a special memory, referred to as the cross-talk memory, in which the total cross talk data is stored. The total cross talk data is updated at regular intervals by broadcasting of cross talk data over the major function bus. This is the regular updating mentioned hereinbefore. It is customary in aircraft simulators to carry out processing in regular steps, known as frames which are equal short intervals of time, the conventional frame duration being one thirtieth of a second.In the present simulator, the CPU 33 of one of the major functions 11 to 15 is designated master CPU in the simulator and generates a start of frame signal at the beginning of each thirtieth of a second. The start of frame signal is received in a major function interface MFI of that major function and triggers the broadcasting of cross talk data from each major function in turn through the major function bus MFB to all the other major functions. The broadcasting of cross talk data is completed within four milliseconds, leaving about twenty nine milliseconds for the major functions to utilize the updated total cross talk data in each frame.

Each major function has a major function interface MFI and its cross talk memory is part of its major function interface MFI. Control signals from the major function interface associated with the master CPU, and further control signals from the other major function interfaces are also transmitted over the major function bus MFB.

The cross talk memory of each MFI is organised in the same way, defined exclusive areas being allocated to the cross talk data generated by the different major functions. So that malfunctions or other conditions which may be present or not can be inserted by an instructor while the system is running, much of the cross talk data in the area allocated to the IOS major function cross talk in the cross talk memories is in the form of flags indicating presence or absence of the respective malfunctions and conditions, and the individual programs of the other major functions 11 to 14 include monitoring of the state of the relevant flags.For exmple, the instructor can insert an engine failure, during running, thereby setting a fail/not fail flag in the fail state in the cross talk area allocated to IOS data, and at the next broadcast of cross talk data which updates the IOS data in the cross talk memory of the engines major function 12, the same flag there will be set in the fail state so that the CPU 34 of the major function 12 will sense the fail state in its programmed monitoring of the IOS area of its cross talk memory. Also, the IOS area contains initial values for various parameters, such as starting position and height of the aircraft, which can be inserted by the instructor before the system begins a run.One input to the IOS major funciton 15 is a "total freeze" button which, if pushed during a run, sets a flag for "total freeze" in the IOS data area of the cross talk memory of the MFI of major function 15, and, after the next updating of all cross-talk memories, all the other major functions 11 to 14 halt operation on detecting that the total freeze flag is set.

The main concept of the functionally distributed simulator (FDS) is division of the overall simulation task into a number of specific areas allocated to major functions MF.

Analysis is undertaken to ensure that this split results in minimum interaction being required between them. Fortunately, typical requirements for a flight simulator have well-defined boundaries that ease the choice of that split.

The amount of interaction between major funcitons, measured in terms of total cross talk (variables generated by one MF and required by other MFs), is remarkably small. A Boeing 747 simulator, for instance, is shown to require only about 8K bytes.

The architecture of the system of Fig 1 can be regarded as a hierarchy of bus levels, each bus being tailored for a specific task.

The primary bus is the major function bus MFB which is a parallel path used for transmitting total cross talk between the major functions.

The two secondary busses, the management link ML and the debug link DL, which each go to all MFs are, unlike the major function bus, serial paths and also go to the Management Computer MC. Small simulator systems may not require both, or either of these links.

The next level down in the hierarchy of busses is the subsystem bus SSB. This is the backplane bus of each major function. All circuit cards in an MF are on the SSB.

The local memory bus LMB allows a processor card to communicate with a RAM or PROM card without having to use the SSB.

The LMB is dedicted to a particular CPU.

There are two cases when data needs to be transmitted from the SSB to an area outside the MF card bin. First, if more I/O cards (circuit cards in an input/output unit) are required than will fit into one bin then extra I/O bins (making up an external input/output unit) must be interfaced; this is done via the linkage bus LB. Secondly, when a 'stand-alone' system needs to be driven a stand alone bus SAB is used.

All I/O cards have local 'intelligence' built-in and hence they can perform their own status checks. A serial bus is built into the backplane of each MF to allow status information to be gathered from one point.

Maximum use is made of programmable LSI/VLSI integrated circuits. These components typically interface to a micro over a parallel data path. This 'Component Bus' is the lowest Bus Level in the architecture.

The Major Function Bus MFB is used only for the transmitting of the shared data referred to herein as cross talk, and associated control signals between major functions. The transfer is done on a broadcast basis at the start of every frame. Each major function interface MFI has high speed logic which performs the broadcast of its data to all other MFs, and then releases control to allow the next MF to do the same, and so on.

Each MFI therefore, holds a copy of the entire simulator's cross talk which is up-dated at the beginning of each frame.

The MFB is preferably a single ribbon cable, comprising twentyfive twisted pairs. It may be up to one hundred feet long and support up to sixteen major functions. The transfer rate is four million words (16 bit) per second.

The management link ML is implemented as an Ethernet serial link which is a high speed (10M bits per second) local area network (LAN).

The ML is used for program loading from disc, diagnostics reporting, access of IOS page and radio-station data from/to disc, and, for record/replay.

The debug link DL is also implemented as an Ethernet serial link.

The DL is used for 'look and enter' across MFs, Symbol Dictionary references from disc, Debug page access to/from disc, and hard copy from screen to line-printer. This card may not be necessary in small systems.

The controllers 24 and 25 in the management computer ML are accordingly Ethernet controllers.

Each major function is a self-contained multiprocessing system based around a multi-master bus, the sub-system bus SSB, which is implemented as a thirty-two bit multiplexed address and data path and is limited to a single card bin backplane. This sub-system bus SSB can be contained within a 96 way DIN connector P1 used with the extended double eurocard format pcbs. Up to sixteen bus masters are allowed, six CPUs, the MLP, the DLP, and eight others. All circuit cards within an MF reside on the SSB which is the communication path for transfer of data between microprocessors in a major function.

A sub-set of the SSB is defined to allow connection of a major function circuit card bin to one or more input/output unit (1/0) card bins. The buffer circuitry to do this is resident on the Function Control and Interface card FCI.

The linkage bus LB connects the FCI to the one or more I/O card bins. The I/O cards are always SSB slaves, i.e. they can only be read from or written to. The linkage bus LB, therefore, allows only 'slave' cards to be used. The I/O card bin(s) may be local to or remote from the MF card bin.

The stand alone bus SAB interfaces system such as the visual field output 18, weather radar, sonar, and the instructor's terminal 21 which can require blocks of data to be transferred in either direction at relatively high rates, to a major function.

Each stand alone bus SAB is controlled by a stand alone interface card SAI which may be designed to emulate a Could SEL HSD controller to be compatible with systems which use an High Speed Data (HSD) interface. In addition a stand alone bus may be driven by two stand alone interface circuits in a back-to-back configuration allowing fast data transfers between two major functions. The stand alone interface is a bus master on the subsystem bus SSB of a major function and hence must reside in the major function circuit card bin, not an I/O card bin.

Each I/O circuit card has its own eight bit micro on-board with an associated serial port (UART). That UART is used to receive/drive an I/O test link ITL (not shown) which is a multi-drop serial link controlled by the management link processor MLP of the respective major function. The MLP polls each I/O card and allows the l/O cards to transmit status information. Although the ITL is built into the backplane of the major function card bin, cards in any I/O card bins connected by the linkage bus LB are still accessible for status requests.

The central processor unit CPU of each of the major function 11 to 15 may consists of six microprocessors each on a circuit card, the presently preferred microprocessor type being the Intel 80286. In a modification, the separate memory unit 34 is omitted and each CPU card has included on it a dual port RAM of sufficient capacity.

The memory unit 34 of each major funciton may consist of six circuit cards each having a 256 byte RAM data processing memory.

The local area network controllers 24 and 25 in the management computer MC, where the management link and debug link are Ethernet links, each include an Ethernet controller.

In simpler embodiments, the debug link and associated circuitry may be omitted. Also, in an embodiment have a restricted library of routines, the whole management computer MC and the management and debug networks are omitted, programs being permanently or semipermanently loaded into the major functions in PROMs.

Where present, the management link processors MLP in the major functions can serve as the sources of an initialisation signal when the system is powered up, this signal setting the respective major function interfaces MFI in an initial condition. All the management link processors MLP and the debug link processors DLP contain respective Ethernet controllers for Ethernet networks. A block of RAM and a configuration EPROM may be included in each function control and interface FCI for use by the Ethernet networks.

The structure and operation of one major function interface MFI and its interaction with the other major function interfaces through the major function bus MFB will now be described in more detail. The hardware for each major function interface MFI is identical, but only one is set in a condition to act as a master controlling the time of broadcasting of cross talk data.

Fig 2 illustrates in block form the principal functional components of a major function interface MFI. The MFI is connected to the subsystem bus SSB and to the major function bus MFB by means of suitable multi-pin connectors.

The total cross talk memory 40 is connected to an internal data bus RDAT and an internal address bus RA. Microprocessors within the major function can obtain access to the cross talk memory 40 from the sub-system bus SSB through controlled data and address buffers 41 and 42 respectively coupling SSB to RDAT and SSB to RA. Address signals from the sub-system bus SSB can reach the memory 40 only when a signal XNBZ(~) is active. This signal is active when low i.e. it is a low active signal, as indicated herein by (-). High active signals, i.e. signals active when high, are indicated herein by mnemonics which are not followed (-).Data signals from SSB can reach the memory 40 only when a control logic signal CLS1(-) is active, and a direction control signal DIR1 is such as to set the data buffer 41 for transferring data from the SSB to RDAT, this buffer 41 being a twoway buffer. The signals CLS1(-) and DIR1 are developed by a control decoder and logic unit 43 connected to the SSB and coupled through buffers (not shown) to the MFB. Control signals on the SSB indicate when the major function microprocessors wish to access the memory 40, but access through the data buffer 41 is allowed by the control decoder and logic unit 43 only while there is no broadcasting of data on the MFB.Similarly, the signal XNBZ(~) which controls the address buffer 42 is a control signal derived from the MFB and is active when data is not being broadcast over the MFB, XNBZ being a mnemonic for cross talk not busy.

In the preferred embodiment, the total cross talk memory 40 has a capacity of 32 kilobytes and is implemented as a matrix of four 8000 x 8 bit RAMs adapted for addressing 2byte words. Separate defined areas, each of a minimum of 64 words and all being either 64 words or an integer multiple of 64 words, are allocated to be written into respectively by exclusively one of the major functions. Thus in the present example the memory 40 has five distinct areas each one of which can be written into only by a respective one of the five major functions 11 to 15.The most significant part of the address of the first word in such an allocated area is used as the address of the respective major function for the purpose of broadcasting of data over the major function bus, and is therefore set manually in a four bit switch SW2 connected by a major function number bus MFN to an address comparator 44. Also for the purpose of broadcasting, the size of the area allocated to the respective major function is set as a number loaded into a "broadcast limit" register 45.

The loading of the broadcasting limit register is normally an operation carried out before use of the system, and can be effected through the internal data bus RDAT. Microprocessors in the respective major function which have access to the memory 40 over the SSB are of course programmed to write only into the allocated area for that major function, but are able to read from any location in the memory 40 which contains data required by these microprocessors.

During each updating of the total cross talk memories, which occurs in the first four milliseconds of each frame, the addresses of the major functions are placed on the major function bus MFB one after another in a predetermined order. In the present example, this is done by a master state machine 46 activated in one of the major function interfaces MFI chosen as master by the manual setting of a switch SW1 connected to the master state machine 46 of that major function interface MF1. The activated master state machine 46 responds to a control signal SOF, generated at the start of each frame from control signals issued over the sub-system bus SSB by the microprocessor designated master, by generating one after the other in synchronism with selected timing pulses from a divider and logic unit 47 all the partial addresses of the lowest locations of the sixteen blocks of 1056 words areas making up the total 32 kilobytes of memory starting with the lowest of these addresses. Each such partial address consists of the four most significant bits of the full address. Five of these addresses are the addresses of the five major functions 11 to 14 for broadcasting purposes. Whenever one of the five major functions receives its broadcasting address over the major function bus, it issues a control signal TMFIBZ, this major function interface busy, which passes onto the major function bus MFB through a buffer not shown in Fig 2.The activated master state machine receives from MFB a signal NEMFIBZ corresponding to TMFIBZ and, in response, pauses in its generation of addresses until the signal NEMFIBZ goes low, indicating that the major function which was emitting the signal TMFIBZ has completed broadcasting of the contents of its allocated area of cross talk memory from its own total cross talk memory 40.

The signal TMFIBZ is generated by a slave state machine 48 driven by an 8 megahertz crystal controlled clock 49, which also drives the divider part of the divider and logic unit 47. Any slave state machine which is carrying out its broadcating operation generates, in addition to the signal TMFIBZ and other control signals, a read command signal READ which is placed on the major function bus through a buffer not shown in Fig 2 and is received in all other major functions as a control signal DATASTB(-) from which a write enable signal to the memory 40 of each of these other major functions is developed by a validating circuit 50 and the control decoder and logic unit 43.

Each major function interface MFI includes an address generator consisting of a latch 51, two counters 52 and 53, a full adder 54, an address generator bus XA coupling the counter 53 to the full adder 54, a major function address bus MFADS coupling the latch 51 and the full adder 54, and a buffer/driver 55 receiving two lines from the address generator bus XA and the output of the full adder 54.

The carry output of the counter 52 is connected to the clock enable input of the counter 53, and the outputs of the counter 52 and the buffer/driver 55 are connected to the internal address bus RA so that the counter 52 drives the least significant address bits and the buffer/driver 55 drives the most significant address bits. Whenever the major function interface is receiving data from another major function, the clock signal supplied to the counters 52 and 53 is the validated version of the signal DATASTB(-) and is coupled from the validating circuit 50. Thus the READ signal of the broadcasting major function is used to clock the counters 52 and 53.The major function address currently broadcast by the master state machine 46 of the master major function is latched by the latch 51 and serves as the four most significant digits of the address generated by the address generator. It will be seen that the latch 51 receives its input from four lines of a cross talk data bus XDAT which connects a set of input and output differential buffers 56 to a broadcast data buffer 57, the differential buffers 56 coupling the cross talk data bus XDAT to the major function bus MFB, and the broadcast data buffer 57 coupling the cross talk data bus XDAT to the internal data bus RDAT.By using the READ signal of the broadcasting major function to clock the counters 52 and 53, adding the outputs of the counter 53 to the latched major function address, and driving the internal address bus RA with the outputs of the buffer/driver 55 and the counter 52, the addresses generated correspond to the addresses in the total cross talk memory from which the data being received over the major function bus MFB and through the buffers 56 and 57 originates. Thus the area allocated to the broadcasting major function in the total cross talk memory 40 of each receiving major function interface MFI is updated.

The major function address bus MFADS also connects the latch 51 to the address comparator 44 which compares the latched address with the address set in the four bit switch SW2. If these two address match, the comparator 44 generates an active control signal THIS MFI (-) which is supplied to the slave state machine 48. The slave state machine responds by cycling through a number of states in a predetermined order, in synchronism with clock pulses from the clock 49.

During this cycle of states, the slave state machine generates the signal READ to produce a write enable signal and address clocking signals in the MFls of the other major functions, a control signal DISSTART which is used to control differential buffers connected to the major function bus and to set the direction of data transfer at the buffer 57 which is a two way buffer, the signal TMFIBZ to cause the master state machine in the master MFI to pause at the current major function address, and a low active read enable signal RD(-) which it supplies to the control decoder and logic unit 43 to cause a read enable signal to be applied to the memory 40. The generation of TMFIBZ inhibits the reception of DA TASTB(-) in the MFI having the cycling slave state machine 46.However, addresses are generated as described hereinbefore by its address generator, with the difference that the clock signals for the counters 52 and 53 are in this case the read enable signal RD(-). The slave state machine 48 resets to its idle condition on receiving a control signal BCOMP(-) indicating that broadcasting of cross talk data from the allocated cross talk memory area of this major function is complete.

The signal BCOMP(-) is generated when a "broadcast limit" comparator 58 senses a match between a number related to the address being supplied to the memory 40 and a number stored in the broadcast limit register 45. To carry out its comparison operation, the broadcast limit comparator 58 is supplied at one set of input pins with the number stored in the broadcast limit register 45 over a broadcast limit bus BLR, and at another set of input pins with part of the address on the internal address bus RA and the output of the counter 53.

The internal address bus RA is connected to an address parity generator 59 which generates a one-bit parity signal corresponding to the parity of any address on the internal address bus RA. If the slave state machine 48 is carrying out its cycle of operations to broadcast the cross talk data of the major function concerned, the parity signal is transmitted to each of the other major function interfaces over the major function bus MFB where it is compared in a logic unit 60 with the parity signal generated by the respective address parity generator 59 in response to the address being generated there by the address generator of the receiving major function interface.If the compared address parity signals in a major function interface do not match, the logic unit 60 develops a parity error signal which sets a bit in a low byte status latch 61 connected to the internal data bus RDAT, and results in an interrupt signal SYSFAIL (not shown in Fig 2) being supplied to the subsystem bus for action by a major function microprocessor which can read the low byte status latch 61. Similarly a data parity generator 62 is connected to the internal data bus RDAT and generates a parity signal which, in the case of an MFI with an active slave state machine, is broadcast over the MFB to each of the other MFls, where it is compared with the locally generated parity signal by the logic 60 which accordingly develops a signal indicating whether or not there is a data parity mis-match.This signal is stored in the respective low byte status latch 61 and results in a SYSFAIL interrupt if there is a mis-match.

The low byte status latch 61 also stores the major function address, being connected to the major function address bus MFN. The remaining two bits in the latch 61 are determined by the status of two test condition signals which may be entered from the sub-system bus SSB through the address buffer 42, internal address bus RA, a three-to-eight decoder referred to herein as the SOF decoder 62, and the logic unit 60.

A high byte status latch 63 connected to the internal data bus RDAT is set by the con tents of the broadcast limit register 45, being connected to the broadcast limit bus BLR.

The major function acting as master generates an address on the sub-system bus SSB at the beginning of each frame which address results in the SOF decoder 62 producing a start of frame interrupt signal SOF INT which is supplied to the master state machine 46 of the major function and to the major function bus MFB for communication to the sub-system buses of the other major functions. On receiving the signal SOF INT, the activated master state machine 46 enters its active cycle of thirty two states. Whilst thus active, the master state machine 46 generates the series of sixteen partial addresses, five of which are major function address, which it supplies to a buffer 64 connected to four lines of the cross talk data bus XDAT for transmission to the major function bus MFB through differential buffers in the set 56.The machine 46 also sets a control signal BNBZ(~) high, thereby indicating that broadcasting is taking place, this low active signal BNBZ(~) in its active state indicating that broadcasting is not taking place. At this and the other major function interfaces, the signal BNBZ(~) generates from the major function bus the corresponding signal XNBZ(~). Hence when the master state machine 46 is active, the address buffers 42 in all major function interfaces are inhibited.

Each time the master state machine 46 issues a new major function address, it also generates an address strobe signal BGOAST which generates, through the major function bus MFB, a corresponding strobe signal GOASTB (not shown in Fig 2) in every major function interface MFI. This strobe signal is used to enable the latch 51 and some of the buffers in each MFI.

The master state machine 46 includes a timer which starts in response to the interrupt signal SOF INT, and runs out after 5 milliseconds. If the signal NEMFIBZ is still active after this 5 milliseconds, the broadcasting of data on the major function bus MFB has continued beyond the normal time, and the master state machine 46 issues an error signal XERR to the logic unit 60 which responds with the signal SYSFAIL.

Fig 3 shows in more detail the memory 40 and inputs and outputs to the data buffer 41, address buffer 42 and decoder and logic unit 43. The memory 40 includes a memory matrix 140, chip selection logic 141, and a read and write control multiplexer 142. The chip selection logic 141 is driven by three lines of the internal address bus RA and a control signal 143 from the decoder and logic unit 43. The control signal 143 is active when either a memory function is signalled by the sub-system bus SSB or the signal NEMFIBZ is active indicating that cross talk data is being broadcast on the major function bus MFB. The multiplexer 142 provides paths from one of its two pairs of input pins to its two output pins in accordance with the state of a low active signal NEMFIBZ(~) produced from NEMFIBZ by the decoder and logic unit 43.If the signal NEMFIBZ(~) is active, a signal VALlDSTB(-) and the signal RD(-) control the outputs WE(-) and OE(-) of the multiplexer 142 respectively. The signal VALIDSTB(#) is blocked by an OR gate 144 if there is a parity error. If NEFMIBZ(-) is not active, the multiplexer output signals WR and RD are controlled respectively by write and read control signals MWC(-) and MRD(-) developed by the decoder and logic unit 43 in response to signals on the sub-system bus.Since NEM FlBZ(-) is active whenever NEMFIBZ is active, the sub-system bus cannot read or write into the memory matrix 140 while any slave state machine of the system is active. Also, the address buffer 42 and part of the decoder and logic unit 43 receive the signal XNBZ(~) which enables the buffer 42 and the respective part of unit 43 only when the master state machine of the system is not active.

The direction of data flow and the enabling of the data buffer 41 are controlled respectively by the signals DIRI and CLSl(-) developed by the unit 43, the signal DIRI being representative of the state of the read control signal MRD(-), and the signal CLSl(-) being set high by the active state of the signal NEM FIBZ.

An address strobe signal ASTB(-) is supplied by the sub-system bus SSB to an inverter 145 coupled to the address buffer 42 and the unit 43.

Whenever the unit 43 is enabled to decode a control signal from the sub-system bus SSB, it develops an acknowledgement signal XACK(-) which returns to the bus SSB. If such a control signal is decoded while the master cross talk signal XNBZ is low, indicating that the master state machine is active, the unit 43 develops a signal MERR(-) indicating to the bus SSB that access to the memory 40 of this MFI is not possible at present.

Fig 4 shows the master state machine 46 in more detail.

The master state machine 46 includes a master state machine memory 46' and a master latch 146. The start of frame interrupt signal SOF INT acts as a clock signal to latch a signal MASTER in the latch 146. The signal MASTER is supplied by the switch SW1 and is active when the master state machine of this MFI is to be enabled. The latch 146 supplies a signal SOF at the start of a frame to the memory 46' and a timer 147 which then runs for 5 milliseconds during which it presents a low output signal to one input of an AND gate 148 which receives NEMFIBZ at its other input. Consequently if NEMFIBZ is still active when the output of the timer 147 goes high, the gate 148 produces the error signal XERR which is supplied to an input of the memory 46' and to the logic unit 60 of Fig 2.

The divider and logic unit 47 comprises a divider circuit 47 which divides the 8 megahertz clock signal from the clock 49 down to 1 megahertz and to 4 megahertz to clock the output signal BGOAST from the memory 46' into a stretching circuit 149 which lengthens BGOAST into a low active signal LGOAST(-) for enabling the buffer 64.

Fig 21 shows an implementation of Fig 4 in which the stretching circuit 149 consists of a D flip flop 150 supplying one input of an OR gate 151 which drives an inverter 152, the other input of the OR gate 151 and the D input of the flip flop 150 receiving the signal BGOAST. A type 74LS74 circuit can be used to provide 125 nanoseconds delay. The master state machine memory 46' in Fig 21 consists of a registered PROM 153 and a latch 154 clocked by opposite phases of the 1 megahertz output of the divider 47'. The registered PROM 153 generates programmed sets of output levels at eight output pins QO to Q7 in dependence upon sets of input levels supplied to nine input pins Ao to A8, but only in response to a clock signal, so that its outputs change only at a clock signal.Output QO provides BNBZ(-), output Q2 provides BGOAST, and outputs Q3 to Q7 provide the major function addresses which are placed on lines 0 to 3 of KDAT by the buffer 64. The output pins Q2 to Q7 are connected respectively to the input pins A2 to A7 as indicated in Fig 21.

The latch 154 is connected to latch a clear signal PURlNlT(-), the start of frame signal SOF, and the slave busy signal NEMFIBZ. The registered PROM in this example is the type Am 27525.

The master latch 146 can be formed by a D flip flop 155 cleared by the Q7 output of the PROM 153, clocked by SOF INT, and having MASTER as the D input. The timer 147 may employ a type 74LS123 circuit, connected to a capacitor of 0. 1 microfarads in series with a resistor of 100 kilohms.

In operation the master state machine PROM 153 broadcasts sixteen addresses to the buffer driver 64 in the course cycling through 32 states. The address broadcasts occur during odd-numbered states. The state diagram for the master state machine is shown in Figs 29a and b.

The latch 154 clocks the following control signals into the PROM 153: 1. CLEAR 2. SOF (start of frame) onto address input AO 3. NEMFIBZ (any major function busy) onto address input Al.

The master state machine remains in its reset/idle state with the Q0-Q7 outputs of the PROM 153 at zero if inputs AO and Al are low. These inputs, SOF and NEMFIBZ respectively, determine the next state (wait or otherwise) assumed by the state machine at its next clock pulse.

The state machine starts its cycle i.e. enters state 1 from its idle/reset state only when its SOF input is high and its NEMFIBZ input is low.

All state 1 and all subsequent states the state machine issues BNBZ high to indicate that a broadcast is taking place. During state 1, BGOAST is issued to partially enable all slave state machines, and major function address 0 is broadcast to complete the enabling of the slave state machine for the MFI at address 0. This slave state machine then begins its own cycle, asserting TMFIBZ (this major function busy) for the whole slave cycle.

TMFIBZ is returned as NEMFIBZ (any major function busy) high to the master state machine latch 154.

At the next 1MHz clock pulse the master state machine enters state 2 and SOF is cleared. If the MFI at address 0 is still busy with its own slave cycle, NEMFIBZ is still high at input Al in the master state machine which therefore waits at state 2 until NEMFIBZ goes low. The master state machine continues broadcasting MFI address 0 and issuing BNBZ high while in state 2.

At the next 1MHz clock pulse that occurs after NEMFIBZ goes low, the master state machine enters state 3 issuing BNBZ high, BGOAST, and broadcasting an incremented major function address (address 1).

The master state machine cycle continues in this way up to state 32 when SOF is cleared and the master state machine returns to the reset/idle state.

When major function addresses are output for a non-existent major functions, NEMFIBZ remains low and the master state continues to its next state at the next clock pulse.

In Fig 29, the output data values from the PROM 153 at each of the state SO to S32 are indicated by a column of hexadecimal values headed DATA.

The slave state machine 48 is similar to the master state machine and is shown in more detail in Fig 5. The slave state machine 48 includes a slave state machine memory 48' - which, when running through its cycle of states, is clocked by the 8 megahertz clock 49. Two inverters 155 and 156 produce the signals RD(-) and DlSSTART(-) from the control signals READ and DISSTART generated by the memory 48'. An enabling latch 157 supplies an enabling signal ENABLE M/C to the memory 48' in response to a strobe signal GOADSTB corresponding to the signal BGOAST issued by the master state machine 46, but the slave state machine 48 only begins its cycle of states if a signal THIS MFI(~) is active from the major function address comparator 44.

Fig 22 shows a circuit for implementing the slave state machine in which the memory 48' comprises a registered PROM 158 and a latch 159. The latch 159 and the corresponding latch 154 of Fig 21 may each be a type 745379 circuit. The registered PROM 158 may again be an AM 27525 circuit. The latch 159 is clocked by the opposite phase of the 8 megahertz clock signal from the phase clocking the PROM 158.

The enabling latch 157 may be a D flip flop 160 with a clear signal applied through a negative logic OR gate 161. The strobe signal GOADSTB clocks the flip flop 160, and the slave output control signal DlSSTART(-) normally clears the flip flop 60.

The latch 159 receives the signals BCOMP(-), THIS MFI(~) and ENABLE M/C(-) (from the latch 157) as inputs, which it applies respectively to address input pins A8, Ao and A1 of the PROM 158.

The slave state machine cycle for a particular MFI operates within a respective even-numbered state in the master state machine cycle.

The state diagram for the slave state machine is shown in Fig 30.

The associated master state machine is in most cases in another MFI and runs asynchronously at a different frequency (1MHz). To cater for these differences 13 wait states are included in the slave state machine cycle. This ensures that the major function bus MFB is clear before the slave state machine initiates cross talk broadcastings.

The PROM 158 is addressed on inputs A2 A7 by the corresponding wrapped around outputs 02-Q7. The Q7 output asserts TMFIBZ (this major function interface busy).

Other outputs from the PROM 158 are the READ output from QO, and the DISSTART output from Q1.

The slave state machine remains in its reset/idle state with QO-07 outputs at zero if any of the inputs AO, Al or A8 are high. These inputs determine the state assumed by the machine at its next clock pulse. The slave state machine starts its cycle i.e. enters state 1 only when all three inputs are low. At state 1 the slave state machine asserts TMFIBZ high on output Q7 and the moves on to state 2 to the next clock pulse. This signal TMFIBZ remains high for the next twenty-two states.

The machine steps through states 2-13 to allow the major function bus lines to settle down after a previous broadcast.

At state 14, DISSTART is issued from Q1 to prepare conditions for the first of a number (defined in the broadcast limit register) of read operations.

At state 15, the contents of the allocated area in the cross talk memory 40 are read at the address present on the internal address bus RA.

At state 16, the address on the counters 52 and 53 is incremented by READ going low on output 08. States 15 and 16 then continue in a loop until the broadcast limit comparator 58 sets the input As high on the PROM 158.

States 19 to 22 comprise dummy read operations with consequent dummy address increments. These are necessary to ensure that data broadcast over the major function bus is not lost due to pipelining.

At state 23, DISSTART goes low at the Q1 output and thereby disables the latch 157.

At state 24, the PROM 158 sets its output Q7 (TMFIBZ) low. This signal is sent to the master state machine as NEMFIBZ (any other function not busy) allowing the master state machine to broadcast the next major function address to all MFls. The new major function address is received by this card and latched by the latch 51 onto 'A' inputs of the address comparator 44 which has the address for this MFI (from the address selector switch SW2) present on 'B' inputs. As the two addresses are not equal, the signal THIS MFI(-) goes high causing input AO on the slave state machine to go high. In response, the slave state machine returns to state 0 (the idle condition).

The values of the outputs from the PROM 158 at each state are shown in a column of hexadecimal values headed DATA in Fig 30, which illustrates the slave cycle.

Each control and data bit signal on the major function bus MFB is a differential signal requiring a pair of lines. Consequently each such signal is placed on the major function bus by a differential output buffer and is received from the bus through a differential input buffer. Gated buffers are used, some being gated permanently open to enable transmission or reception under all working conditions.

Fig 6 shows a differential output buffer 162 for the high active signal TMFIBZ connected through a pair of lines 163 of the major function bus to a permanently open differential input buffer 164 which produces the high active signal NEMFIBZ whenever there is a high active signal TMFIBZ at any output buffer 162 connected to the lines 163. The signal TMFIBZ is used to gate a permanently high input, indicated by one input value 1 in Fig 6, through the buffer 162. The gate terminal of the buffer 164 is not shown but is permanently high so that the buffer 164 is permanently open. With this arrangement, any slave state machine generating TMFIBZ causes the signal NEMiFBZ to be produced in all the major function interfaces.

Fig 7 shows a differential output buffer 165 receiving the master state machine generated signal BNBZA(-), which is active whenever the master state machine is in its idle state, as input signal, and gated by the signal MAS TER which is high only in the MFI in which the master state machine is activated by the switch SW1. The signal BNBZ(~) produces the signal XBZ on a respective pair of lines 166 of the MFB. A permanently open differen tial input buffer 167 produces the signal XNBZ(~) in response to XBZ. Since the signal MASTER is active throughout operation of system, the signal XNBZ(~) is produced in all major function interfaces and is a replica of BNBZ(~).

Fig 8 shows the signal READ, produced by the slave state machine, applied as an input to a differential output buffer 168 which is gated by the signal DISSTART(-), also produced by the slave state machine, and is connected through a pair of lines 169 of the MFB to the inputs of a differential input buffer 170 gated by an inverted version of the signal TMFIBZ.

The output of the input buffer 170 is held high through a resistor 172. Consequently, in a major function interface MFI in which the slave state machine is active, and therefore producing the signal TMFIBZ, the signal DA TASTB(-), produced by the buffer 170, is high, i.e. not active. In all other MFls, DA TASTB(-) is high when READ is high in the broadcasting MFI, and low when READ is low in the broadcasting MFI.

Fig 9 shows the signal BGOAST, produced by the master state machine, applied as an input to a differential buffer 173 which is gated by the signal MASTER, produced by the switch SW1, and is connected through a pair of lines 174 of the major function bus to the inputs of a differential input buffer 175 which is permanently open. Since the signal MAS TER is active throughout operation of the system, the signal GOASTB in all the major function interfaces is a replica of the signal BGOAST.

Fig 10 shows the validating circuit 50 which provides a validated version of the signal DA TASTB(-), labelled VALlDSTB(-), and, in combination with a negative logic OR gate 176 provides the clock signal for the address generator counters 52 and 53, this clock signal, INCR.ADR., being the signal RD(-) in an MFI in which the slave state machine is active, i.e. in the broadcasting MFI, and being the validated strobe signal VALlDSTR(-) in all other MFls. The validated strobe signal VAL lDSTR(-) is a replica of the signal DA TASTB(-) except for the first two occurrences of active DATASTB(-) in each broadcast of cross talk data.The replica signal GOADSTB, which is generated at each odd number state of the master state machine cycle, is inverted by an inverter 177 and the inverted signal is supplied as a reset to a counter 178 which, unless disabled by a test signal RECEIVE DISABLE (-), produces a high output during the next two occurrences of an active DATASTB(-) signal which is supplied as a clock signal to the counter 178. The output of the counter 178 and the signal DA TASTB(-) are supplied as inputs to a two input negative logic AND gate 179 supplying one input of the negative logic OR gate 176.

The output from the negative logic AND gate 179 is the validated strobe signal VAL lDSTB(-).

The transmission of data and major function addresses onto the major function bus MFB and their reception from that bus are controlled in each major function interface MFI by the differential buffer set 56 which consists of a transmitter set 56a of sixteen differential output buffers, and a receiver set 56b of six teen differential input buffers, connected to sixteen pairs of major function data lines 180 represented schematically in Fig 11.

Each buffer in the transmitter set 56a is gated by output of an OR gate 181 with inverted inputs, the input signals supplied being DlSSTART(-) and LGOAST(-). Consequently data can be transmitted from the crosstalk data bus XDAT to the data lines 180 of the major function bus if either DlSSTART(-) or LGOAST(-) is active, i.e. if the slave state machine of this MFI is active, or if this MFI is the master and the master state machine is generating a major function address, the duration of LGOAST(-) being chosen to enable the buffer set 56a for the broadcasting of a major function address.

Each buffer in the receiver set 56b is gated by the output of another OR gate 182 with inverted inputs. The inputs to this OR gate are supplied by a two input AND gate 183 with inverted output and a three input AND gate 184 with inverted output. The inputs to the AND gate 183 are the replica signal GOADSTB and the inversion of MASTER. The inversion of MASTER is a high active signal which is active in all major function interfaces except that in Which the master state machine is activated, referred to herein as the master MFI, the other major function interfaces being referred to as slave MFls. In a slave MFI, the gate 183 is open, i.e. enabled by MASTER, and the receiver set 56b of buffers is enabled whenever GOADSTR is active, so that major function addresses can be received from the MFB and placed on the cross talk data bus XDAT.

In the master MFI, the gate 183 is disabled by MASTER, and the gate 184 produces a low output, and therefore enables the receiver set 56b, only when it is true both that LGOAST(-) is not active and one of the slave state machines which is not that of the master MFI is active. The latter condition is indicated by NEMFIBZ active and TMFIBZ, which is the inversion of TMFIBZ, is active. In a slave MFI, LGOAST(-) is always not active, i.e. is high and the gates 182 and 184 enable the receiver set 56b whenever a slave MFI, other than one to which these gates 182 and 184 belong, is active. Thus the receiver set 56b is enabled to receive major function addresses, by the gate 183, and cross talk memory data, by the gate 184, from the major function bus.The major function addresses generated by the master MFI are not received from the major function bus at the master MFI, since its gate 183 is disabled by MAS TER. Instead, since the first four lines, XDAT O to 3, of the cross talk data bus XDAT are connected directly to both the buffer 64 for the master state machine (Fig 4) and the latch 51 (Fig 2), the major function addresses are latched directly into the latch 51 from the buffer 64.

The cross talk data bus XDAT is coupled to the internal data bus RDAT by the data buffer 57 which, as shown in Fig 12, is controlled by four control signals, TRANSEN(-), DIS START(-), RD(-) and DATASTB(-). The signal TRANSEN(-) is a low active enabling signal produced by a two input negative output AND gate 185. The two inputs to the gate 185 are the low active signal LGOAST(-) which is active only in the master MFI, and the signal NEMFIBZ which is active in all major function interfaces whenever any one of them has an active slave state machine.Consequently the buffer 57 in all MFls is disabled when no MFI is broadcasting cross talk data, and the buffer 57 in the master MFI is dis abled whenever a major function address is placed on the four lines XDAT O to 3 of the cross talk data bus. If there is no major function address being placed on XDAT O to 3, LGOAST(-) is high and the gate 185 is enabled for the signal NEMFIBZ, so that the data buffer 57 is enabled by TRANSEN(-) for the reception and transmission of cross talk memory data. The direction of transfer of data through the buffer 57 is determined by the status of the signal DlSSTART(-), which is low with a transmitting slave state machine and high in a receiving MFI.The buffer 57 has two clock inputs, one being the signal RD(-), which is active only with a transmitting slave state machine. In a receiving MFI, the signal DATASTB(-), which is a low active replica of READ in at the transmitting slave state machine, is the clock input. The transmitting direction in Fig 12 is designated BA, and the receiving direction AB. Thus in an MFI in which the slave state machine is active, DIS START(~) is low, RD(-) is the clock signal and cross talk memory data is transferred from the internal data bus RDAT to the cross talk data bus XDAT, whereas in an MFI in which the slave state machine is not active, DISSTART(-) is high and data is transferred from the cross talk data bus XDAT to the internal data bus RDAT in synchronism with the signal DATASTB(-).

Figs 13a and 13b show in more detail those parts of the logic unit 60 of Fig 2 which are coupled to the data parity generator 62 and the address parity generator 59. The generators 59 and 62 supply their outputs to a parity comparator 186 which receives two further inputs from a major function bus parity latch 187. The outputs of the generators 62 and 59 are also supplied to a latch 188 clocked by the low active signal RD(-), and therefore only enabled in an MFI in which the slave state machine is active. The latch 188 supplies two signals BPARDAT and BPARADS, respectively representing the data parity generator output and the address parity generator output, to respective differential output buffers 189 and 190 shown in Figs 14 and 15.The output of the buffer 189 is enabled by the signal DISSTART, which is active only when the slave state machine of that MFI is active, and applies a corresponding data parity signal PARDAT to a pair of lines 191 of the major function bus. Similarly, the buffer 190 applies a corresponding address parity signal PARADS to a pair of lines 192 of the major function bus, when DISSTART is active. Permanently enabled differential input buffers 193 and 194 in each MFI produce a cross talk data parity signal XPARDAT and a cross talk address parity signal XPARADS corresponding to BPARDAT and BPARADS.In a receiving MFI, the signals XPARDAT and XPARADS are clocked into the latch 187 (Fig 13a) by the signal DATASTB(-), so that the parity comparator 186 compares the received data parity signal XPARDAT with the locally generated parity signal from the data parity generator 62, and compares the received address parity signal XPARDAT with the locally generated parity signal from the address partiy generator 59. The data on the internal data bus RDAT at this time is the cross talk data received from the transmitting MFI, so that if the data parity signals do not match, an error has occurred in the transmission of that data.If a parity error has occurred, the output of the comparator 186 causes a parity error signal to appear at one output of an error latch 195 which is a high active signal and is locked on by a negative logic AND gate 196 enabled by the signal VALlDSTB(-). The address on the internal address bus RA at this time is the address generated locally by the counter 52 and the buffer/driver 55. If the parity of the locally generated address does not match the received address parity signal XPARADS, the comparator 186 produces an output signal causing the parity error signal to appear from the error latch 195, unless already locked on.

The parity error signal is locked on for whichever type of parity error is sensed first. The parity error signal is also supplied to Block the OR gate 144 (Fig 3) and thereby prevent the signal VALlDSTR(-) being supplied as a write control signal to the multiplexer 142.

The error latch 195 also sets a signal CROSS TALK ERROR active on receiving the time out error signal XERR from the master state machine 46 which can occur if this MFI contains the activated master state machine.

The error latch 195 can be cleared by either of two signals, CLEAR STATUS REG and PURlNlT(-). The error signals from the latch 195 are supplied to an OR gate 197 driving an inverter 198 to produce an interrupt signal SYSFAIL which is supplied to a line of the sub-system bus SSB of the major function to inform an interrupt handling microprocessor of the major function that an error has occurred.

The clearing signal CLEAR STATUS REG is decoded from an address which can be transmitted to the internal address bus RA from the sub system bus SSB.

Fig 16 shows the decoder 62 which receives the three internal address bus lines RA1, RA2 and RA3, and the input write control signal lWC(-) from the decoder and logic unit 43 (Fig 3). According to the status of these four inputs,the decoder 62 develops ones of five output signals, LOAD BLR, CLEAR STATUS REG, SOF INT, BCAST REG and RE CEIV REG. The signal LOAD BLR is an input write control signal and is used for loading a number into the broadcast limit register 45 from the sub-system bus. The functions of CLEAR STATUS REG and SOF INT have already been described hereinbefore.The start of frame interrupt SOF INT is also supplied to all other MFls through the major function bus by transmission through a differential output buffer 199, enabled by the signal MASTER, to a pair of lines 100 of the major function bus (allocated to major function interrupt 0, MFINT 0), and reception through a differential input buffer 101 enabled by the inversion of the signal MASTER by means of an inverter 102.

The SOF INT line within each MFI is connected directly to the subsystem bus SSB of the major function so that SOF INT can be received directly within all major functions.

Fig 18 shows the address generator in more detail. A low active signal GOADSTB(~), which is active whenever GOADSTB is active, is supplied as a clearing signal to the two counters 52 and 53. The carry output of the counter 52 is connected to the clock enabling input of the counter 53, and the signal IN CR.ADR. produced by the circuit of Fig 10 is supplied as the clock signal to both counters 52 and 53. The signal XNBZ, which is active whenever the activated master state machine is not active, disables the counter 52. When the master state machine is active, the counter 52 is enabled by the low state of XNBZ, and both counters 52 and 53 are cleared at the beginning of each odd numbered state of the master state machine cycle.Each successively active slave state machine can then clock the counters 52 and 53 with either the locally developed signal VALlDSTB(-) or the directly supplied signal RD(-).

The count in the counter 52 is applied directly to the eight lines RA1 to 8 of the internal address bus RA, which consists of sixteen lines RAM to 14 and RBHEN. The lines RAO, RA14 and RBHEN are connected to the chip selecting logic 141 (Fig 3). The counter 53 is also an eight bit counter. The first two bits of its count are supplied to the first two lines XA9 and 10 of a cross talk address bus XA, consisting of lines XA9 to 14, and these two lines are connected directly to the first two input pins of the buffer driver 55. The buffer driver 55 supplies lines RAO, RA9 to 14 and RBHEN of the internal address bus RA. The first two lines XA9 and 10 from the counter 53 are arranged to drive the lines RA9 and 10 of the internal address bus RA through the buffer driver 55.The signal XNBZ is supplied to disable the buffer driver 55, so that its output drives lines of the internal address bus RA only when the activated master state machine is active. The signals on lines RAO and RBHEN are held low by grounding of the corresponding two inputs of the buffer driver 55.

This is done because the cross talk memory matrix 140 is, in the present example, an arrangement of four eightbit RAMs adapted to store sixteen bit words. Which pair of RAMs is addressed is determined by the status of the signal on RA14. The inputs to the buffer driver 55,for the lines RA11 to RA14 are supplied by the full adder 54 which produces the sum of the binary number on lines XA11 to 14 of the cross talk address bus XA from the counter 53 with the binary number on the major function address bus MFADS from the latch 51. The signal GOADSTB enables the latch 51 which may be a type 74LS75 circuit.

Clock pulses cease to be supplied to the counters 52 and 53 when the active slave state machine receives the signal BCOMP(-) from the broadcast limit comparator 58 in the broadcasting MFI, this comparator 58 being enabled by the concurrent presence of the signal TMFIBZ and high levels on the lines RA1 to RA6. The comparator 58 compares the eight bits of the broadcast limit register output bus BLR with the eight bits on the lines RA7 and 8 and XA9 to 14. When these two sets of eight bits match and TMFIBZ and RA1 to 6 are all high, the comparator 58 issues BCOMP(-). This condition for the issuing of the broadcast complete signal BCOMP(-) allows the highest word address in the allocated cross talk memory area to be immediately below a word level which is an integer multiple of sixty four words.Each RAM of the cross talk memory matrix 140 is addressed by lines RA1 to 13. Lines RAO and RBHEN are used to enable the low and high bytes respectively of each word. The line RAI4 is used to select the lower or higher 16 kilobytes of the total of 32 kilobytes. Lines RA1 to 13 provide the addresses within each of these 16 kilobyte divisions for the 8192 words, which are organised as two blocks of 8192 bytes, each held in a respective 8 kilobyte chip addressed by RA1 to 13. Thus the word addresses are given by lines RA1 to 14.

The lines RA1 to 6 are all high at each 63rd word from zero. Thus the present example has 64 word granularity i.e. minimum block length. In the present example, each major function is allocated an area which is 1024 words or a multiple of 1024 words, and the activated master state machine generates the full set of sixteen initial addresses which, in hexadecimal notation, are 0 to F supplied as four binary bits to the latch 51. The four output bits of the full adder 54 drive the address lines RA11, Ray2, RA 13 and Ray4, and thus determine Which 1024 word area is being addressed, since RA11 is the bit for 210 words.

The signal on line RA14 is logic 0 for the first 8192 words, and logic 1 for the next 8192 words, the address of the first word being logic 0 on all lines RA1 to 14. The signals on the lines XA11 to 14 determine the relative values of the signals on lines RA11 to 14.

The signals on the lines MFADS 11 to 14 from the latch 51 determine the starting level for each allocated area of the cross talk memory. If the allocated areas are all no more than 1024 words, lines XA12, XA 13 and XA 14 are always logic 0.

The size of an allocated area of cross talk memory is indicated by the largest number which appears on the combination of the lines RA1 to 8 and XA9 to 14. Since the allocated areas have 64 word granularity, their largest number always has lines RA1 to 6 high.

Therefore the concurrence of TMFIBZ high and RA1 to 6 high is used to enable the comparator 58, and the comparator 58 compares the number on lines RA7 and 8 in combination with lines XA9 to 14 with the number stored in the broadcast limit register 45.

In the present embodiment, the broadcast limit register 45 is cleared, at power up, by a signal PURINlT(-) which is active at power up. Fig 19 shows the circuit which produces PURlNlT(-). This circuit has a series combination of a resistor 200 and a capacitor 201 connected between a 5 volt power supply line and data ground. The junction of the combination is connected to one input of an OR gate 202 with inverted inputs. Since the resistor 200 is connected to the power supply line, this input of the gate 202 is held low at power up, until the capacitor 201 charges up.

Consequently the output of the gate 202 is initially high and is inverted by an inverter 203 to produce the low active signal PURlNlT(-).

The other input of the gate 202 is a signal INIT supplied from a line 204 connected to the sub-system bus and shown in Fig 20. The signal PURlNlT(-) is produced after power up only if the signal INIT goes low.

In the master MFI, the switch SWI is open as shown in Fig 20 and the signal MASTER is active. Consequently the output of an inverter 205 is low and the output of an AND gate 206 with inverted output is high. The output of the gate 206 is supplied to the line 204 through an open collector buffer 207 or equivalent buffer circuit. Hence if the line 204 is not pulled low at the sub-system bus, an inverter 208 supplies a high signal to a differential output buffer 209 enabled by MASTER. A corresponding signal MESET is supplied by the buffer 209 to a pair of lines 210 of the major function bus. These lines are connected to a differential input buffer 211 in each MFI which supplies one input to the AND gate 206, which is blocked in the master MFI but open in each slave MFI, since MASTER is not active there, the switch SWI being closed.The output from the buffer 211 in each slave MFI is a replica of the input to the buffer 209 in the master MFI. Consequently, if the line 204 is high in the master MFI, it is high in the slave MFls. If the subsystem bus in the major function with the master MFI pulls the line 204 low, the input to the buffer 209 goes high, the outputs from the buffers 211 in the slave MFls go high, and the lines 204 in the slave MFls go low.

Active PURlNlT(-) also clears the error latch 195 (Fig 13a), the enable slave start latch 157 (Fig 5) and the master state machine memory 46' (Fig 4): The major function address comparator 44 (Fig 5) can be disabled by a signal BROADCAST DISABLE(~) which is set by a latch 212, shown in Fig 16, when the SOF decoder 62 describes BCAST REG and RDAT O clocks the latch 212. The non-inverted output of the latch 212 is supplied as one bit to the low byte status latch 61 (Fig 18). Similarly, the validating circuit 50 (Fig 10) can be disabled by a signal RECEIVE DISABLE (-) which is set by a latch 213, shown in Fig 16, when the SOF decoder 62 decodes RECEV REG and RDAT 0 clocks the latch 213. The non-inverted output of the latch 213 is also supplied as one bit to the low byte status latch 61.The eight bits in the latch 61 are the four bits making up the major function address, the broadcast and receive disable bits, and the parity and cross talk error bits from the error latch 195 (Fig 13a).

Fig 23 shows in more detail part of the circuitry of Fig 3. The memory matrix 140 consists of four RAM chips 212 to 215 of 8 kilobytes capacity, each addressed by the lines RA1 to RA13 of the internal address bus. Each chip has two, complementary chip select input pins. The high active chip select pins of chips 212 and 213 are driven from RA14 through an inverter 216, and the high active chip select pins of chips 214 and 215 are driven directly by RA14. This arrangement divides the memory matrix 140 into higher and lower 8 kiloword areas. The low active chip select pins of chips 212 and 214 are driven by the output of a negative logic AND gate 217 which has two inputs connected respectively to RAM and to the decoder and control logic unit 43 which supplies a signal MYEN(-). Consequently the chip 212 or 214 is enabled when RAO(~) and MYEN(-) are active. RAO(-) is active whenever the buffer driver 55 is enabled. The low active chip select pins of chips 213 and 215 are driven by the output of another negative logic AND gate 218 which has two inputs connected respectively to RBHEN and to the unit 43 to receive MYEN(-). Consequently the chip 213 and 215 is enabled when RBHEN(~) and MYEN(-) are active. RBHBN(-) is active whenever the buffer driver 55 is enabled.The inverter 216 and the gates 217 and 218 form the chip select logic 141 of Fig 3. The output pins of the chips 212 and 214 are connected to lines RDAT O to 7, and the output pins of the chips 213 and 215 are connected to the lines RDAT 8 to 15. The write enable and output enable pins of each of the chips 212 to 215 are connected respectively to the two output pins of the multiplexer 142 shown in Figs 3 and 24 to receive respectively either VAL lDSTB(-) and RD(-) or MWC(-) and MRD(-).

The data buffer 41 is formed by two type 74LS640 two way buffers. The address buffer 42 is formed by two tri-state latch circuits, type Am 74LS533.

Fig 24 shows the decoder and selection logic unit 43 in detail, the multiplexer 142 and the SOF decoder 62.

The unit 43 includes a decoder 219 which receives addresses and an input/output select signal IOSEL from the sub-system bus SSB.

The decoder219 has two outputs 220 and 221, one for input/output functions and the other for memory functions respectively. Signals on these outputs 220 and 221 are latched by a latch (type 74LS75) 222 enabled by the signal ASTB from the inverter 145 (Fig 23). Input/output function selection is gated by a negative logic AND gate 223 enabled by XNBZ(-). Memory function selection signals from the latch 221 pass directly to a negative logic OR gate 224 which supplies the signal MYEN(-) to the chip selection logic 141, and directly to two negative logic AND gates 225 and 226. The gate 225 produces MWC(-) when supplied a memory function selection signal by the latch 222 and a memory write control signal MWTC(-) by the subsystem bus SSB.The gate 226 produces MRD(-) when supplied a memory function selection signal by the latch 222 and a memory read control signal MRDC(-) by the sub-system bus.

A negative logic AND gate 227 produces the input write control signal IWC(-), which is supplied to the SOF decoder 62, when supplied an input/output selection signal by the gate 223 and an input/output write control signal lOWC(-) by the sub-system bus. For loading a broadcast limit number into the broadcast limit register, lWC(-) is active. To allow the major function to read the status latches 61 and 63, another negative logic AND gate 228 produces the signal lRC(-) when supplied with an input/output selection signal by the gate 223 and an input/output read control signal lORC(-) by the sub-system bus.

Any output from the gates 225 to 228 is returned to the subsystem bus as XACK(-) through a negative logic OR gate 229 and an open collector buffer 230. If XACK(-) is generated at the same time as XNBZ is not active, i.e. if the sub-system bus attempts to access the memory matrix 140 or an input/output function, then another negative logic AND gate 231 produces, through an open collector buffer 232, a memory error signal MERR(-) which is supplied to the sub-system bus. The signal XACK(-) is also supplied as one input to a negative logic AND gate 233 which receives NEMFIBZ as an input. The output from gate 233 is the control logic signal CLS1(-) which enables the data buffer 41.

Thus the data buffer 41 is enabled whenever there is both no cross talk and any one of the gates 225 to 228 is producing an active signal. The direction control signal DIR1 for the data buffer 41 is produced by a negative logic OR gate 234 which receives lRC(-) and MRD(-) as inputs.

An inverter 235 produces NEMFIBZ(~) for the memory function multiplexer 142. The OR gate 224 which receives the memory function selection signals from the latch 222 also receives NEMFIBZ(~), so that MYEN(-) is active when either the latch 222 produces an active memory function selection signal or NEMFIBZ is active. Thus the multiplexer 142 is enabled when access to memory is required by the sub-system bus or by the slave state machine of this MFI or from the major function bus by another MFI. Since the signal paths through the multiplexer 142 and the enabling of the data buffer 41 are controlled by NEMFIBZ, the sub-system bus is over-ridden at any coincidence of access demands.

Fig 25 shows the validating circuit 50 of Figs 2 and 10 in more detail. The counter 178 is formed by two D flip flops 236 and 237, which receive DATASTB(-) as clock signal. The signal RECEIVE DISABLE(~) is not normally active, and is therefore high, so that both flip flops 236 and 237 receive high inputs at their D input pins, and are normally in their set conditions so that the AND gate 179 is enabled by the complementary output from the second flip flop 237. The signal DA TASTB(-) is active whenever the signal READ of a broadcasting slave state machine is active, and consequently is active in states 15, 17, 19 and 21. States 15 and 16 are repeated in a loop until a broadcast is complete.

The signal GOADSTB(~) is active immediately before any slave broadcast begins, and therefore the flip flop 236 resets immediately before a slave broadcast, and thereby also resets the flip flop 237. The complementary output from the flip flop 237 in its reset state is high, so that the gate 179 is blocked. The first active DATASTB(-) sets the first flop 236 but not the second flip flop 237 since the output from the first flop 236 is still low when the first active DATASTB(-) reaches the second flip flop 237. The second active DATASTB(-) sets the second flip flop 237 but does not pass through the gate 179 since at the time that it reaches the gate 179 the complementary output from the second flip flop 237 is still high.Thus the first two active DATASTB(-) signals do not produce VAL IDSTB(-) signals.

Fig 26 shows in more detail the circuitry of the address generator. In the present example the major function address comparator 44 is a type 74LS85 circuit having its output pin coupled through a resistor and capacitor combination to an inverter 238 such as type 74LS240 to produce the signal THlSMFI(-).

The broadcast limit comparator 58 consists of a type Am 25LS2521 circuit with its enable pin receiving the output from an eight input coincidence gate 239 which produces a low active signal when TMFIBZ is active and lines RA1 to 6 are all high. The buffer driver 55 is a type 74LS244 which has the input pins corresponding to the outputs for RAO and RBHEN connected to data ground. The counters 52 and 53 are type 74LS593 circuits. Pin 18 of counter 52 receives the signal XNBZ, produced by an inverter (not shown) driven by XNBZ(~). Pin 14 of counter 52 is connected to data ground. Pins 12 and 11 are connected respectively to the output of the inverter 177 of Fig 25 and pin 14 of counter 53. Pins 18 and 12 of counter 53 are connected respectively to data ground and the output of inverter 177. Pin 11 of counter 53 is not used.Pin 15 also of counter 53 is connected to data ground.

Fig 27 shows the data buffer 57, the parity generators 59 and 62, and the latch 188 of Fig 13b. The data buffer 57 consists of two type 74LS646 circuits having their enabling input pins connected to receive TRANSEN(-), and their pins 2 and their pins 22 connected, with the pins 2 receiving logic 1 as indicated.

The parity generators 59 and 62 both consists of two type 74S280 circuits. The latch 188 is formed by two D flip flops, type 74LS74, acting independently on the outputs from the two parity generators 59 and 62.

Fig 28 shows the parity latch 187, parity comparator 186, error latch 195, latches 212 and 213 of Fig 16, the status latches 61 and 63 and the broadcast limit register 45 of Fig 18, and associated circuitry. The parity comparator 186 is formed by two exclusive-ORgates 240 and 241, and an OR-gate 242. The parity latch 187 is formed in the same way as the latch 188 in Fig 27. The error latch 195 also has two D flip flops, 243 and 244, but includes a negative logic OR gate 245 supplying its output to the reset inputs of the flip flops 243 and 244 and driven by the signal PURlNlT(-) and the signal CLEAR STATUS REG from the SOF decoder 62.The broadcast limit register 45 is a type Am 25LS2520 circuit clocked by LOAD BLR from the SOF decoder 62 and cleared by PURINlT(-). The status latches 61 and 63 are type 74LS244 circuits having pins 1 and 19 driven by lRC(-).

The interrupt signal SYSFAIL generated in response to a parity error or to a cross talk error is passed through an open collector buffer 246 to the sub-system bus. The status of the parity error signal produced by the flip flops 243 is visually indicated by a pair of LEDs 247 in series with a resistor 248 between the outputs of the flip flop 243, the LEDs being oppositely poled and emitting respectively green and red light. The LEDs may be PCL 200RG, with the resistor 248 being 620 ohms.

It should be noted that the master state machine and its associated circuitry for generating major function addresses need not be incorporated in any of the major functions but may be constructed as a separate unit connected to the major function bus.

Although the particular embodiment of the invention described hereinbefore is for use in a flight simulator, other embodiments may be used in other contexts. For example, the control of a chemical process plant may be analysed into a number of major functions and a computing system embodying the invention be adapted to monitor and control the plant. Similarly, other industrial processes may be monitored and controlled. Furthermore, an unmanned vehicle such as an unmanned spacecraft may be controlled by a computing system embodying the invention.

Claims (18)

1. A memory addressing circuit comprising a memory connected to a data bus and to an address bus and to means for controlling reading from and writing to the memory respectively to the data bus and from the data bus at addresses in the memory determined by address signals on the address bus, first and second buses coupled to the data bus, the said first bus also being coupled to the address bus, and means for generating address signals on the address bus in response to control signals supplied to the address generating means from the said second bus.

2. A memory addressing circuit according to claim 1, wherein the address generating means includes means for initiating generation of address signals in response to at least one said control signal which is numerically related to a predetermined address in the memory.

3. A memory addressing circuit according to claim 1 or 2, wherein the address generating means includes counting means adapted to count control signals supplied as a series of pulses from the said second bus, and the address signals generated in response are incremented in dependence upon the count in the counting means.

4. A memory addressing circuit according to any preceding claim, wherein the address generating means includes counting means adapted to count a series of pulses generated in the circuit by pulse generating means adapted to become active in response to a predetermined one of the said control signals.

5. A memory addressing circuit according to claim 4, wherein the address generating means includes means for limiting the number counted of the pulses generated by the pulse generating means.

6. A memory addressing circuit according to claim 5, wherein the limiting means includes means for storing a predetermined number, and means for comparing a signal numerically related to the number of counted pulses generated by the pulse generating means with the predetermined number and generating a limit signal when the said numerically related signal matches the said predetermined number.

7. A memory addressing circuit according to claim 6, wherein the pulse generating means is coupled to the comparing means and is such as to stop generating pulses in response to the limit signal.

8. A memory addressing circuit according to any preceding claim, wherein further means are provided for generating a series of control signals each numerically related to a different respective address in the memory and for supplying the series of control signals to the said second bus, the further means being such as to begin generating the said series in response to a start signal supplied thereto from the said first bus.

9. A memory addressing circuit according to claim 4 or 5 or 6 or 7, wherein the pulse generating means is such as to generate a busy signal when active, the said busy signal being supplied to the said second bus.

10. A memory addressing circuit according to claim 8, wherein the further means is such as to go into a waiting state when receiving a busy signal from the said second bus after generating any one of the first to penultimate control signals in the said series.

11. A memory addressing circuit according to any preceding claim, wherein means are provided for isolating the date bus from the said first bus.

12. A memory addressing circuit according to claim 11, wherein means are provided for setting the direction of data flow between the data bus and the said first bus.

13. A memory addressing circuit according to any preceding claim, wherein means are provided for isolating the data bus from the said second bus.

14. A memory addressing circuit according to claim 13, wherein means are provided for setting the direction of data flow between the data bus and the said second bus.

15. A memory addressing circuit according to any preceding claim, wherein means are provided for isolating the address bus from the- said first bus.

16. A memory addressing circuit according to any one of claims 4 to 7 or to claim 9, wherein the pulse generating means supplies read command signals to the memory during generation of the said series of pulses.

17. A memory addressing circuit according to claim 3, wherein means are provided for supplying write command signals to the memory during counting of the said series of pulses.

18. A memory addressing circuit substantially as described hereinbefore with reference to Figs 2 to 30 of the accompanying drawings.