GB2170954A - Transmission gates with compensation - Google Patents

Abstract

Each IGFET (NG1, PG1) of a complementary transmission gate (TG1) has associated with it a corresponding "dummy" device (CNG1,CPG1) of like conductivity type. Each dummy device is operated in a complementary manner to its corresponding transmission gate IGFET to provide substantial cancellation of gating signals that may tend to be coupled via parasitic capacitance (CG) to the conduction paths of the IGFETs. <IMAGE>

Description

SPECIFICATION.

Transmission gates with compensation This invention relates to transmission gates and, in particular, to transmission gates comprised of insulated-gate field-effect transistors (IGFETs).

IGFETs are used extensively as transmission gates because: a) conduction-between the source and drain, which define the ends of the conduction path of the IGFET, is readily controlled by the application of a control, or gating, signal to -the. gate electrode of the IGFET; -and b) ordinarily, the control signal applied to the gate electrode does not contaminate, or mix with, the signal being translated along the conduction path of the IGFET, due to the extremely. high impedance between the gate and the conduction path of the IGFET.

In circuits and systems requiring great precision, -complementry transmission gates are used to provide symmetrical bipolar conduction.. Such a circuit is illustrated in the prior art circuit of Fig; 1, which shows a conventional comparator circuit.using Complementary Metal Oxide-Semiconductor (CMOS) transmission gates. Complementary transmission gates (e.g.

TG1, TG2, TG3) ar formed by connecting the source-to-drain (i.e. conduction) path of an IG FET of one.conductivity type (e.g. P) in parallel with the conduction path of an IGFET of second conductivity type (e.g. N). Normally, complementary control signals are applied to the gate electrodes of the two IGFETs to either turn them both on or both off at any one time.Complementary transmission gates using IGFETs of complementary conductivity type are normally considered to produce "zero-offset switching" because: a) there are no-diode-drops as.in bipolar transistor circuits; and.b) the complementary signals (e.g., CLR, CLR and CL1, C) applied to the gate electrodes of the complementary IGFETs should cancel. each other because of the symmetrical structure of.thecomponents and because of their complementary operation.

Hoever, Applicants discovered that using complementary transmission gates at high sampling rates (e.g. above 1 MHz) to translate signals onto a high impedance sample and hold node (erg. node 1) resulted in the intro d.uction of significant voltage offsets at the node. Applicants recognized that the offsets were due, in. part, to parasitic gate-to-source/drain capacitances and to non-symmetric operating conditions. At high sampling rates the rise and fall times of the enabling (turn-on) and disabling (turn-off) signals (also referred to herein as clocking-or gating signals) applied to the gate electrodes of the transmission gate transistors arn-very fast (e.g. 2V/nanosecond).

As a result, a greater portion of the high frequency clock signal transitions get coupled from the gate-electrode to the source and drain electrodes via the parasitic gate-to-drain (CDG) and gate-to-source (CGS) capacitances.

Consequently, at high frequencies more of the clocking signals applied to the gate are mixed into the signals or reference levels being propagated along the source-drain (conduction) paths. The problem is most severe when the transmission gate is being turned-off and is most evident at the end of the transmission gate conduction path connected to a node having a relatively high direct current (d.c.) impedance.

The offset problem resulting from non-symmetric operation is best explained with reference to Figs. 1 and 2. The circuit of Fig. 1 functions to compare an input (VIN) against a reference signal (V,,EF) and to produce an amplified version of the difference between VIN and V,,, at the output of a inverter 11. In operation, transmission gates TG2 and TG3 are enabled (turned-on) simultaneously. The turn-on of TG2 couples V,,Ep to node 1 which functions as a sample and hold node. The turn-on of TG3 "auto-zero's" inverter 11 which may be assumed to be a CMOS inverter. The auto-zero'ing of inverter 11 causes the input and output of 11 to be set at the toggle (or flip) point of the inverter.For ease of explanation, assume inverter 11 to have an operating potential (VOD) of 5 volts, and to be symmetrical, whereby its toggle point may then be assumed to be 2.5 volts (i.e. VDD/2).

Following the coupling of V,,, to node 1 and the auto-zeroing of 11, clock signals are applied to transmission gates TG2 and TG3 to turn them OFF. Transmission gate TG1 is then enabled to couple VIN to node 1. The voltage difference between VIN and VREF is then amplified about the toggle point of inverter 11.

However, a major problem with the circuit of Fig. 1 occurs when TG2 (or TG1) is disabled. For then, uncompensated charge is injected onto sample and hold node 1 by the disabling clock signal transitions applied to TG2 (or TG1) and TG3 and an offset voltage is generated at node 1, which alters the true value of VREF (or VIN) previously applied to that node, and is therefore an error signal.

For example, assume that a gating signal of +5 volts is applied to the gate electrodes of NG2, NG3 and PG1 and that a gating signal of O volts is applied to the gate electrodes of PG2, PG3 and NG1. Consequently, TG2 and TG3 are-ON and TG1 is Off. Assume also that: 1) VREF is at 0 volts whereby node 1 is charged to 0 vols via TG2; and 2) nodes 2 and 3 are charged to 2.5 volts due to the turn-on of TG3 and inverter 11 being a complementary, symmetrical, inverter. A detailed examination of TG2 for the assumed signal condition reveals that the gate, source and drain of PG2 are at, or close to, zero volts.

For this signal condition PG2 does not have a conduction channel between its source and drain and its parasitic capacitances (i.e. CGl and C62). are set to "low" capacitance values.

By way of example, the "low" parasitic capacitance values may be assumed to be in the order of 0.01 picofarad (pf). On the other hand, the gate of NG2 is at 5 volts while its source and drain are at 0 volts. The 5 volt differential between the gate and the source/drain ensures that NG2 is ON, that there is a conduction channel (enhancement layer) between its source and drain, and that the parasitic capacitance of NG2.are set to "high" capacitance values. By way of example, the "high". parasitic capacitance value of each parasitic capacitor may be assumed to be in the order. of 0.03 picofarad (pf).

When the clock signal CL, makes a negative going transition from +5 volts to 0 volts and CLR makes- a positive going transition from 0 volts.to +5 volts, TG2-is disabled. For these gating conditions, it was expected that the falling edge of CL, would cancel the rising edge. of CL,, However, as noted above, Applicants -discovered, as shown in Fig. 2, that when a V,,, (or a VIN) of zero volts is propagated via TG2 (or TG1) to node 1 and TG2 (or (TG1) is subsequently disabled, a negative charge is trapped at node 1 resulting in a negative voltage offset of up to 50 millivolts being produced at node 1.Applicants recognized. that the offset was, to a great extent, due to: a) the initial differences in the parasitic capacitance of NG2 and PG2; and b) the difference in the responses of NG2 and PG2 to the turn-off signal. The negative going transition of CLR is coupled via the initially "high" parasitic capacitance of NG2 to node 1 while the positive transition of CL,, is coupled via the initially "low" parasitic capacitance of PG2 to node 1.Hence it is evident that more negative charge than positive charge will be injected into node .1. But, perhaps even more important, as.CL, goes negative and CL11 goes positive, and with VREF=O, NG2 is driven from a high (e.g., 0.03 pf) parasitic capacitance state to a low (e.g., 0.01 pf) parasitic capacitance state while PG2 is driven from a low (eg., 0.01 pf) parasitic capacitance state to an-even still- "lower." (e.g., 0.005 pf) parasitic capaci tance.state. Thus Applicants recognized that, for certain signal or bias levels, the complementary transistors of the transmission gate, although driven by complementary signals, do not respond in a complementary manner.Con sequently,.more negative charge is injected via C62 of NG2 into node 1 than positive:charge is injected via the CG2 of PG2, and the negative charge trapped at node 1 produces a negative offset (error) voltage at that node.

In.an anaiogous manner when V,,EF is at, or near 5 volts, and TG2 is ON, NG2 is in a low capacitance state and PG2 is in a high capacitance state. When TG2 is subsequently turned-off: a) the gate of PG2 is driven from 0 volts to +5 volts with its source-drain path remaining close to +5 volts. PG2 is then driven from a "high" parasitic capacitance (e.g. 0.03 pf) state to a "low" parasitic capacitance (e.g. 0.01 pf) state; and b) the gate of NG2 is driven from +5 volts to 0 volts with its source to drain path remaining at +5 volts. NG2 is then driven from a "low" parasitic capacitance (e.g. 0.01 pf) to a still "lower" parasitic capacitance (e.g. 0.005 pf) state.Consequently, the positive going CL,, transition injects more positive charge into node 1 via C62 of PG2 than the negative going CL, transition injects via C62 of NG2. Hence a positive voltage offset is produced at node 1.

As shown in Fig. 2, the offset introduced at node 1 is a function of the voltage level translated along the conduction path of complementary transistor transmission gates. The offset voltage is a maximum at the extreme range (e.g. 0 and 5 volts) of the volages being translated and a minimum midway between the extremes. When the voltage level (e.g. VREF, VIN or Vb,a5) along the conduction paths of the transmission gates is mid-way (e.g. 2.5 v) between the high (e.g. 5 volts) andziow (e.g. 0 volts) levels of the clocking signal transitions the transmission gates are operated in a very symmetrical manner.

Charge trapping is then approximately compensated and the resultant offset is negligible.

Conventional complementary transmission gate operation results in voltage offsets of up to +50 millivolts over the full range of the signal input or reference voltage levels, as shown in Fig. 2. This is unacceptable where it is desired to sample the input and reference voltages and compare them with an accuracy of 1 millivolt (0.001 volt) when using 5 volt clock signals (some 5000 times greater than the detection level) without injecting contaminating charge.

As discussed above, Applicants' invention resides, in part, in the recognition that, for a variety of factors, complementary transmission gates do not provide compensation against contamination from gating signals throughout the range of input or reference signal level being translated via the complementary transmission gates.

Applicants' invention also resides in means for compensating complementary transmission gates to obtain very little offset. In circuits embodying the invention, each IGFET of a complementary transmission gate has associated with it a corresponding "dummy" device of like conductivity type. Each dummy device is operated in a complementary manner to its corresponding transmission gate IGFET to provide substantial cancellation of the gating signals which are capacitively coupled to the conduction paths of the lGFETs.

In the accompanying drawing, like reference characters denote like components; and Figure 1 is a schematic diagram of a prior art circuit; Figure 2 is a drawing showing offset vol tages obtained with conventional complemen tary transmission gates; Figure 3 is a schematic diagram of a circuit embodying the invention; Figure 4 is a drawing of waveforms associ ated with the circuit of Fig. 3; Figures 5A and 5B are drawings of the characteristics of the parasitic capacitances of the N-type and type lGFETs as a function of gate-to-source/drain voltages; Figure 6A isis cross section diagram of "dummy" devices which may be used to practice the invention; and -Figure 6B is a schematic diagram of the equivalent-circuit of Fig. 6A.

The active devices, which are preferred for use in practicing the invention, are lGFETs.

For this reason, the circuit is illustrated in the drawing as employing such transistors and will be so described hereinafter. However, this is not intended to preclude the use of other suitable devices and to this end, the term "transistor", when used without limitation in the appended claims, is used in a generic sense.

In the Figures, enhancement type IGFETs of P-conductivity type are identified by the letter P followed by a particular reference numeral, and enhancement type IGFETs of N-conductiv ity type are identified by the letter N followed by a particular reference numeral. The charac teristics of IGFETs are well known and need not be described in detail. But, for a clearer understanding of the description to follow, the following definitions and characteristics perti nent to the invention are set forth: 1. Each IGFET has first and second elec trodes which define the ends of its conduction path and a control electrode (gate) whose ap plied potential determines the conductivity of its conduction path. The first and second elec trodes of an IGFET are referred to as the source and drain electrodes.For a P-type IG FET the source electrode is defined as that one of the first and second electrodes having the more positive (higher) potential applied thereto. For an N-type IGFET, the source elec trode is -defined as that one of the first and second electrodes having the less positive (lower) potential applied thereto.

2. Conduction occurs when the applied gate-to-source potential (V(;s) is in a direction -to turn on the transistor and is greater in magnitude than a given value, which is defined .as the threshold voltage (VT) of the transistor.

To turn-on a P-type enhancement IGFET its gate voltage (V6) has to be more negative than its source voltage (Vs) by at least VT. To turn on an N-type enhancement-lGFET its V6 has to be-more positive than its Vs by VT.

3. IGFETs are bidirectional in the sense that when an enabling signal is applied to the control electrode, current can flow in either direction in the conduction path defined by the first and second electrodes, i.e. the source and drain are interchangeable.

4. In the drawing and in the discussion to follow, the parasitic gate to drain/source capacitances (C65 and C66) are identified as C61 and C62 since the source and drain are interchangeable, particularly when the IGFETs are operated as transmission gates.

In the discussion to follow, a potential at, or near ground is arbitrarily defined as a logic "O" or "low" condition and any potential at or near +V66 or +V volts is arbitrarily defined as logic "1" or "high" condition.

The circuit of Fig. 3 includes complementary transmission gates TG1 and TG2 and their respective associated compensatory ("dummy") transmission gates CGT1 and CGT2.

TG1 is intended to selectively couple an input voltage, VIN, between an input terminal 11 and a sample and 'hold node 1. TUG 1 is comprised of complementary IGFETs PG1 and NG1 having their conduction paths connected in parallel between terminal 11 and node 1.

CTG1 is comprised of complementary IGFETs CPG1 and CNG1 having their conduction paths connected in parallel between node 1 and a floating node, F1. As discussed below CPG1 and CNG 1 need only be connected in common at node 1 to provide parasitic capacitive coupling between their respective gate electrodes and the one end (source or drain) of their conduction paths connected to node 1. The other end of their conduction paths may be left floating as shown in Figs. 6A and 6B. The gate electrodes of NG1 and CPG1 are connected in common to line 13 and are driven by a clock signal CL, applied to line 13. The gate electrodes of pG1 and CNG1 are connected in common to line 15 and are driven by a clock signal CL; applied to line 15.Clock signals CL, and CL; are complementary to each other as shown in Fig. 4.

TG2 is comprised of complementary IGFETs PG2 and NG2 having their conduction paths connected in parallel between terminal 17 and node 1, between which TG2 selectively couples a reference voltage VREF. CTG2 is comprises of complementary IGFETs CPG2 and CNG2 having their conduction paths connected in parallel between node 1 and a floating node, F2. As for CPG1 and CNG1, CPG2 and CNG2 need only be connected in common at node 1 to provide parasitic capacitive coupling between their gate electrodes and the one end (source or drain) of their conduction paths connected to node 1. The other end of their conduction paths may be left floating.

The gate electrodes of NG2 and CPG2 are connected in common to line 19 and are driven by a clock signal CL, appled to line 19.

The gate electrodes of PG2 and CNG2 are connected in common to line 21 and are driven by a clock signal CL,, applied to line 21.

Clock signals CL5 and CL,, are complementary to each other as shown in Fig. 4.

Node 1 is connected to one plate of a cou pling capacitor Cc whose other plate is connected to the input of a complementary inverter i1. The conduction path of a complementary transmission gate TG3 comprised of lG- FETs PG3 and NG3 is connected between the input and output of inverter 11. The conduction paths of PG3 and NG3 are connected in parallel between nodes 2 and 3, which define the input and output nodes, respectively, of inverter 11. In this embodiment CL, is applied to the gate -electrode ofNG3 and CL,, is applied to the gate electrode of PG3 whereby TG2 and.TG3 are either turned-on or turnedoff at the same time.

Transmission gate TG3 -functions to "autozero" inverter 11. That is, when TG3 is enabled inverter Ii is driven to its toggle point with the voltage at node 2 being essentially equal to the voltage at node 3. For the case where 11 is symmetrical it may be assumed that the turn-on of TG3 causes the voltage (V2) at its input node 2 and the voltage (V3) at the output of Ii to go to Odd/2; where VOD volts is assumed to be 5 volts, Odd/2 is equal to 2.5 volts. The clock signals (CL,. CL,, and CL". CL,) make transitions between 0 and 5 volts. When TG3 is being disabled (i.e.

turned-off), the gate voltage of PG3 goes from 0 volts to +5 volts while the gate voltage of NG3 goes from 5 volts to zero volts. With the voltage at the drains and sources of pG3 and NG3 at Odd/2, C;;1 and C(;2 of PG3 are approximately equal to CG and C(;2 of NG3.

Hence the effect of the complementary clock transitions applied to the gate electrodes of PG3 and NG3 is substantially cancelled at these nodes. For this reason no compensation is provided for transmission gate TG3.

The compensation provided by the compensating (''dummy'') transmission gates is now further detailed.

Assume, by way of example, that VRFr is first applied via TG2 to sample and hold node .1 beginning- at time t1 by CL, going high and .CLR going low, as shown in Fig. 4, and that, concurrently, inverter 11 is auto-zero'ed by the turn-on of TG3. During the application of V,,, (actually until time t5) CL, is low and CL, is high whereby TG1- is turned-off.

The turn-on- of TG3 causes V2 and V3 to go to, or near, Vow/2 volts. The turn-on of TG2 causes V,,sF which may'have any value in the range between 0 volts and 5 volts, to be applied via the conduction paths of PG2 and NG2 to node 1. Thus at time t3, V1 is charged (or-discharged) to V,,; and V2 is set at, or close to Odd/2.

At time t3, CL, goes from high-to-low and -CL,, goes from low-to-high turning-off Tug2 and TG3 and- turning ON CTG2. The response of TG2 and CTG2 will now be discussed assuming VREF to have been equal to zero volts and V1 to be charged to zero volts. (a) Just prior to time t3, the gate of NG2 is at +5 volts while its source and drain are at 0 volts. For this turn-on condition NG2 is set to a "high" parasitic capacitance condition as shown in the characteristic curve of Fig. 5A which shows how the parasitic capacitance between the gate and source/drain varies as a function of the potential between the gate and the source-drain, for an N-type IGFET. From Fig.

5A, each one of C61 and C62 of NG2 may be assumed to equal 0.03 pf. Between time t3 and t4 the gate of NG2 is driven from 5 vols to 0 volts, while the potential, V1, at node 1 remains close to zero volts. With the gate-tosource potential of NG2 at zero volts, C62 of NG2 goes to a "low" capacitance value which may be assumed to be equal to 0.01 pf. Thus from time t3 to t4, the parasitic capacitance of NG2 goes from a "high"-value to a "low" value. (b) Just prior to time t3, the gate, source and drain of CNG2 are at 0 volts.

CNG2 is then set to a "low" capacitance value. Between time t3 and t4, the gate of CNG2 is driven from 0 volts to +5 volts while its source/drain remains at zero volts, setting CNG2 to a "high" parasitic capacitance condition. The operation of NG2 and CNG2 is therefore highly complementary whereby their complementary gating signals tend to cancel to a high degree. (c) Just prior to time t3, the gate, drain and source of PG2 are at zero volts placing PG2 in a non-conducting "low" parasitic capacitance state. Between time t3 and t4, the gate of PG2 is driven to +5 volts while its source/drain remains at zero volts.

This causes PG2 to be turned-off more, with an effective reverse bias of 5 volts, and to be placed in a still "lower" capacitance state as shown in the characteristic curve of Fig. 5B which shows how the parasitic capacitance of a P-type device varies as a function of gateto-source/drain voltage. Therefore, very little of the positive going transition of CL,, occurring between time t3 and t4 is coupled into node 1. (d) Just prior to time t3, the gate of CPG2 is at +5 vols while its source and drain are at 0 volts. CPG2 is then set to a "lower" parasitic capacitance as shown in Fig. 5B.

When CL, goes from +5 volts to 0 volts between time t3 and t4, the-gate of CPG2 is driven to 0 volts and the drain and source of CPG2 remain at that level. CPG2 is then placed in a "low" parasitic capacitance state.

Thus, between time t3 and t4, PG2 is driven from a "low" to a "lower" capacitance state while CPG2 is driven from a "lower" to a "low" capacitance state. The complementary gating signals applied to the gate electrode of PG2 and CPG2 then tend to cancel each other and very little offset is-produced at node 1 as shown in Fig. 4.

Fig. 4 shows how the voltage (VI) at node 1 varies as a function of the switching transients applied to the gates of the transmission gate transistors. The waveforms of Fig. 4 are somewhat idealized being actually relatively complex. However, the point to be noted is that in circuits embodying the invention, there is a significant reduction in the offset with very little charge being trapped upon the turnoff of TG2 (or TG1). The portion of Fig. 4 .labeled A depicts the idealized response at V1 for VREF and VIN being at zero volts and the portion labeled B depicts the idealized response at. V1 for V,,E,, -and VIN being at +5 volts.

When VREF is +5 volts, it can be shown that CTG2 provides a high degree of compensation for TG2, for analogous reasons to the ones discussed above. In this instance when TG2 is being turned-off, after having sampled V,,E'F and coupled V,,, to node 1, the circuit has the following properties: (a) NG2 goes from a "low" capacitance state (its gate, drain and source were initially at +5 volts) to a "lower" capacitance state (its gate goes to zero while its drain and source remain.at +5 volts); (b) CNG2. goes from a "lower" capacitance state. (since its gate was zero while its source and drain were at +5 volts) to a "low" capacitance state (since its gate goes to +5 volts while. its source and drain remain at +5 volts; (c) PG2 goes from a "high" capacitance.

state. (since its gate was at zero volts while its source and drain were at +5 volts) to a "low" capacitance state (since its gate, source and drain are then at +5 volts); and (d) CPG2 goes from a "low" capacitance state (since its gate, source and drain were at +5 volts) to a "high" capacitance state (its gate goes to zero volts while its source and drain remain at +5 volts).

As before, CNG2 varies in an inverse manner to NG2 and CPG2 varies in an inverse manner to PG2. The gating signals coupled via their parasitic capacitances will then tend to cancel. The high degree of compensation obtained at +5 volts with the addition of the compensating ("dummy") devices (CPG2, CNG2 and/or CPG1, CNG1) is shown in portion B of Fig. 4.

It is evident that where a. high degree of compensation is obtained at the extreme ends of the levels being translated, an even higher degree of compensation is present within the middle range, between 0 and +5 volts.

In the circuit of Fig. 3, a high degree of cancellation results since reliance is now made on a P-dummy device (e.g. CPG2) to cancel the effect of a P-type IGFET (e.g. PG2) and on an N-dummy device (e.g. CNG2) to cancel the effect of an N-type IGFET (e.g. NG2).

The gating signals as shown in Fig. 4 may be designed to have relatively symmetrical rise and fall times to ensure that the gating signals complement each other to a great extent. Best compensation is achieved when waveforms are symmetrical, but the present compensating scheme has considerable tolerance even where the gating signals are not exactly symmetrical.

An important aspect of the invention is that in Applicants' invention, the "dummy" devices need not be full transistors. That is, each dummy device may include connection to a single diffused region (source or drain) with a gate/channel region adjacent to the diffused region. This is illustrated in Figs. 6A and 6B.

Fig. 6A is a cross section of a compensating N device (CN) and a compensating P device (CP). The CN-device has two regions (62, 64) of N+ conductivity type separated by a channel (or substrate) region, and a gate electrode 61 overlying the channel and isolated therefrom. The CP-device likewise has two regions (66, 68) of P+ conductivity type separated by a channel region, and a gate electrode 63 overlying the channel and isolated therefrom.

Complementary gating signals (clock and clock) are applied to the gate electrodes of the CN and CP devices. Only one N+ region of CN and only one P+ region of CP are shown connected in common to node 1. Regions 64 and 68 need not be connected to anything, reducing the space needed to lay out the CP and CN devices. Furthermore regions 62 and 68 can be made smaller than regions 64 and 66, further reducing the space required. Fig. 6B shows the equivalent schematic diagram of the structure of Fig. 6A.

Note that CNG 1 and CPG1, or CNG2 and CPG2 could be formed as shown in Fig. 6A and/or replaced by devices having the equivalent circuit shown in Fig. 6B. The structure of Fig. 6 enables very small devices to be formed. This is a distinct advantage in a high density array since it allows minimum design rule devices.

This arrangement is also important in that it enables very small capacitances to be formed reducing the loading effect on the sample/hold node. Also, the dummy device may be made to have a comparable geometry to the IGFET which it is intended to compensate. So formed, process variations tend to cancel.

Another important aspect of Applicants' invention relates to the application of the clocking signals to the transmission gates. Referring to Fig. 4, note that CL5 and CL, are designed to turn-off TG2 and TG3 before CL, and CL turn-on TGl. The "break" before "make" clocking arrangements ensure that the high degree of compensation produced at node 1 is not effected by interaction between the reference voltage and input signal clocking signals and by interaction between the reference voltage and the input signal voltage. Also, turning-off TG2 before turning-on TUG 1 ensures that V,,EF is never shorted to VIN.

It would appear that turning-on TG1 as TG2 is being turned-off would obviate the need for separate compensation devices associated with each complementary transmission gate.

However, Applicants discovered that the break before make arrangement is preferable to turning-on TG1 as TG2 is being turned-off and provides a much higher degree of, and more reliable, compensation.

In the circuit of Fig. 3, compensation was provided for each one of TG1 and TG2. It was found that in some applications it was sufficient to provide a "compensatory transmission gate" for only the gate TG1 coupling V,N-into the system. However in this instance, the sizings -of CnG1 and CPG1 had to be increased over the full compensation scheme of Fig. 3 to provide compensation for TG2. . !.

Claims (9)

1. -A circuit wherein a first insulated-gate field-effect transistor (IGFET) of first conductivity type and a second IGFET of second conductivity type have conduction paths thereof connected in parallel between first and second nodes for translating a signal between said first and second nodes, and have respective gate electrodes for receiving mutually complementary control signals; said second node is coupled via a capacitor to the input of an amplifier; and in order to cancel any voltage offset produced at said second node due to capacitive coupling of a control signal, there are provided: third and fourth insulated-gate field-effect devices of said first and second conductivity type, respectively, said third device having a first region of first conductivity type and a control electrode insulated therefrom for receiving the control signal received by said sec ond- lGFET, - and said fourth device having a first region of second conductivity type and a control electrode insulated from its first region for receiving the control signal received by said first IGFET, said first regions of said third and fourth devices being connected to each other and to said second node.

2. A circuit as claimed- in claim 1 wherein one control signal is connected directly to the control electrode of said fourth device and to the gate electrode of said first IGFET; and the complement of that control signal is connected directly to the control electrode of said third device and to the gate electrode of said second IGFET.

3. A circuit as claimed in claim 2 wherein said first conductivity type is N-conductivity type and said second conductivity type is Pconductivity type.

4. -A circuit as claimed in claim 1, 2 or 3 wherein said third device includes a second region of said first-conductivity type; and said fourth device includes a second region of said second conductivity type; and wherein said second regions of said second and third devices are unconnected to any circuit point.

5. A circuit as claimed in claim 1, 2 or 3 wherein each of said third and fourth devices includes a second region spaced apart from, and of the same conductivity type as, its said first region.

6. A circuit as claimed in any preceding claim and further includjng a third node for the application thereto of a signal to be compared with the signal at said first node; and fifth and sixth IGFETs of first and second conductivity, respectively, having conduction paths thereof connected in parallel between said third node and said second node and having respective gate electrodes for receiving other mutually complementary control signals; and wherein there are further provided:: seventh and eighth insulated-gate field-effect devices of said first and second conductivity type, respectively; said seventh device having a first region of said first conductivity type and a control electrode insulated therefrom for receiving the control signal received by said sixth IGFET, and said eighth device having a first region of said second conductivity type and a control electrode insulated therefrom for receiving the control signal received by said fifth IGFET.

7. A circuit as claimed in claim 6, arranged for the respective control electrodes of said first and second IGFETs to receive complementary control signals of a polarity and magnitude to turn said first and second IGFETs either ON at the same time or OFF at the same time: and for the respective control electrodes of said fifth and sixth IGFETs to receive other complementary control signals of a polarity and magnitude to turn said fifth and sixth IGFETs either ON at the same time or OFF at the same time.

8. A circuit as claimed in claim 7, wherein said control signals are phased for turning-off said first and second IGFETs before turning-on said fifth and sixth lGFETs, and for turning off said fifth and sixth IGFETs before turning-on said first and second lGFETs.

9. A transistor circuit provided with "dummy" compensating devices substantially as hereinbefore described with reference to Figs. 3 or 6 of the accompanying drawing.