CA1246159A - Transmission gates with compensation - Google Patents
Transmission gates with compensationInfo
- Publication number
- CA1246159A CA1246159A CA000501608A CA501608A CA1246159A CA 1246159 A CA1246159 A CA 1246159A CA 000501608 A CA000501608 A CA 000501608A CA 501608 A CA501608 A CA 501608A CA 1246159 A CA1246159 A CA 1246159A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23Q—DETAILS, COMPONENTS, OR ACCESSORIES FOR MACHINE TOOLS, e.g. ARRANGEMENTS FOR COPYING OR CONTROLLING; MACHINE TOOLS IN GENERAL CHARACTERISED BY THE CONSTRUCTION OF PARTICULAR DETAILS OR COMPONENTS; COMBINATIONS OR ASSOCIATIONS OF METAL-WORKING MACHINES, NOT DIRECTED TO A PARTICULAR RESULT
- B23Q1/00—Members which are comprised in the general build-up of a form of machine, particularly relatively large fixed members
- B23Q1/25—Movable or adjustable work or tool supports
- B23Q1/26—Movable or adjustable work or tool supports characterised by constructional features relating to the co-operation of relatively movable members; Means for preventing relative movement of such members
- B23Q1/30—Movable or adjustable work or tool supports characterised by constructional features relating to the co-operation of relatively movable members; Means for preventing relative movement of such members controlled in conjunction with the feed mechanism
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
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- Mechanical Engineering (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
RCA 81,831 TRANSMISSION GATES WITH COMPENSATION
Abstract of the Disclosure Each IGFET of a complementary transmission gate has associated with it a corresponding "dummy" device of like conductivity type. Each dummy device is operated in a complementary manner to its corresponding transmission gate IGFET to provide substantial cancellation of the gating signals coupled via parasitic capacitance to the conduction paths of the IGFETs.
Abstract of the Disclosure Each IGFET of a complementary transmission gate has associated with it a corresponding "dummy" device of like conductivity type. Each dummy device is operated in a complementary manner to its corresponding transmission gate IGFET to provide substantial cancellation of the gating signals coupled via parasitic capacitance to the conduction paths of the IGFETs.
Description
- 1 - RCA 81,831 TRANSMISSION GATES ~ITH COMPENSATION
This invention relates to transmission gates and, in particular, to transmission gates comprised of insulated-gate field-effect transistors (IGFETs].
IGFETs are used extensively as transmission ga-tes because: a) conduction between the source and drain, which define the ends of the conduction path oE the IGFET, iS readily controlled by the applicat;on of a control, or gating, signal to the gate electrode of the IGFET; and bl ordinarily, the control signal applied to the gate electrode does not contaminate, or mix with, the signal being translated along the conduction path of the IGE'ET, due to the extremely high impedance between the gate and the conduction path of the IGFET.
In the accompanying drawing, like reference characters denote like components; and FIGURE 1 iS a schematic diagram of a prior art circuit;
FIGURE 2 is a drawing showing offset voltages obtained with conventional complementary transmission gates;
FIGURE 3 is a schematic diagram of a circuit embodying the invention;
FIGUR~ 4 iS a drawing of waveforms associated with the circuit of FIGURE 3;
FIGURES 5A and 5B are drawings of the characteristics of the parasitic capacitances of the N-type and P-type ~, . ~
i - la - RCA 81,831 IGFETS as a function of gate-to-source/drain voltages;
FIGURE 6A iS a cross section diagram of 'Idummy"
devices which may be used to practice the invention; and FIGURE 6s is a schematic diagram of the equivalent circuit of FIGURE 6A.
The active devices, which are preferred for use in practicing the invention, are IGFETs.
In circuits and systems requiring great precision, complementary transmission gates are used to provide symmetrical bipolar conduction. Such a circuit is illustrated in the prior art circuit of FIGURE 1, which shows a conventional comparator circuit using Complemen-tary Metal-Oxide-Semiconductor (CMOS) -transmission ga-tes. Complementary transmission gates (e~g~ TGl, TG2, TG3) are .Eormed by conllec-t.ing t~e source-to-drain (i.e. conduction) path o~ an IGFET of one conductivity type (e.g. P) in parallel with the conduction path of an IGFET of second conductivity type (e.g. N).
Normally, complementary control signals are applied to the gate electrodes of the two IGFETS to either turn them both on or both off at any one time. Complementary transmission gates using IGFETS of complementary conductivity type are normally considered to produce "zero-offset switching"
because: a~ there are no diode-drops as in bipolar transistor circuits; and b) the complementary signals (e.g., CI.RI CLR and CLI, CLL) applied to the gate electrodes of the complementary IGFETS should cancel each other because of the symmetrical structure of the components and because of their complementary operation.
However, Applicants discovered that using complementary transmission gates at high sampling rates
This invention relates to transmission gates and, in particular, to transmission gates comprised of insulated-gate field-effect transistors (IGFETs].
IGFETs are used extensively as transmission ga-tes because: a) conduction between the source and drain, which define the ends of the conduction path oE the IGFET, iS readily controlled by the applicat;on of a control, or gating, signal to the gate electrode of the IGFET; and bl ordinarily, the control signal applied to the gate electrode does not contaminate, or mix with, the signal being translated along the conduction path of the IGE'ET, due to the extremely high impedance between the gate and the conduction path of the IGFET.
In the accompanying drawing, like reference characters denote like components; and FIGURE 1 iS a schematic diagram of a prior art circuit;
FIGURE 2 is a drawing showing offset voltages obtained with conventional complementary transmission gates;
FIGURE 3 is a schematic diagram of a circuit embodying the invention;
FIGUR~ 4 iS a drawing of waveforms associated with the circuit of FIGURE 3;
FIGURES 5A and 5B are drawings of the characteristics of the parasitic capacitances of the N-type and P-type ~, . ~
i - la - RCA 81,831 IGFETS as a function of gate-to-source/drain voltages;
FIGURE 6A iS a cross section diagram of 'Idummy"
devices which may be used to practice the invention; and FIGURE 6s is a schematic diagram of the equivalent circuit of FIGURE 6A.
The active devices, which are preferred for use in practicing the invention, are IGFETs.
In circuits and systems requiring great precision, complementary transmission gates are used to provide symmetrical bipolar conduction. Such a circuit is illustrated in the prior art circuit of FIGURE 1, which shows a conventional comparator circuit using Complemen-tary Metal-Oxide-Semiconductor (CMOS) -transmission ga-tes. Complementary transmission gates (e~g~ TGl, TG2, TG3) are .Eormed by conllec-t.ing t~e source-to-drain (i.e. conduction) path o~ an IGFET of one conductivity type (e.g. P) in parallel with the conduction path of an IGFET of second conductivity type (e.g. N).
Normally, complementary control signals are applied to the gate electrodes of the two IGFETS to either turn them both on or both off at any one time. Complementary transmission gates using IGFETS of complementary conductivity type are normally considered to produce "zero-offset switching"
because: a~ there are no diode-drops as in bipolar transistor circuits; and b) the complementary signals (e.g., CI.RI CLR and CLI, CLL) applied to the gate electrodes of the complementary IGFETS should cancel each other because of the symmetrical structure of the components and because of their complementary operation.
However, Applicants discovered that using complementary transmission gates at high sampling rates
- 2 - RCA 31,831 1 (e.g. above 1 MHz) to translate signals onto a hign impedance sample and hol~ node (e.g. node 1) res~lted in the introduction of significant volt3ge offsets at the node. Applicants recognized that the offsets were due, in part, to parasitic gate-to-source/drain capacitances and to non-symmetric operating conditions. At high sampling rates the rise and fall times of the enabling (turn-on) and disabling (turn-off) signals ~also referred to herein as clocking or gating signals) applied to the gate electrodes of the transmission gate transistors are very ~ast (e.g. 2V/nanosecond). As a result, a greater portion of the high frequency clock signal transitions get coupled from the gate electrode to the source and drain electrodes via the parasitic gate-to-drain (CDG) and gate-to-source (CGs) capacitances- Consequently, at high fre~uencies more of the clocking signals applied to the gate are mixed into the signa]s or reference levels being propagaked along the soucce-drain (conduc~ion) paths. The problem is most severe when the transmission gate is being turned-off and is most evident at the end of the transmission gate conduction path connected to a node having a relatively high direct current (d.c.) impedance.
The offset problem resulting from non-symmetric operation is best explained with reference to FIGU~ES 1 and 2. The circuit of FIGURE 1 functions to compare an input signal (VIN) against a reference level (VREF) and to produce an amplified version of the difference between VIN and VREF at the output of a inverter Il.
In operation, transmission gates TG2 and TG3 are enabled (turned-on) simultaneously. The turn-on of TG2 couples VREF to node 1 which functions as a sample and hold node. The turn-on of TG3 "auto-zero's" inverter Il which may be assumed to be a CMOS inverter. The auto-zero'ing of inverter Il causes the input and output of Il to be set at the toggle (or flip) point of the inverter. For ease of explanation, assume inverter Il to have an operating potential (VDD) of 5 volts, and to be symmetrical, whereby its toggle point may then be assumed to be 2.5 volts (i.e. VDD/2). Following the coupling ol VREF to
The offset problem resulting from non-symmetric operation is best explained with reference to FIGU~ES 1 and 2. The circuit of FIGURE 1 functions to compare an input signal (VIN) against a reference level (VREF) and to produce an amplified version of the difference between VIN and VREF at the output of a inverter Il.
In operation, transmission gates TG2 and TG3 are enabled (turned-on) simultaneously. The turn-on of TG2 couples VREF to node 1 which functions as a sample and hold node. The turn-on of TG3 "auto-zero's" inverter Il which may be assumed to be a CMOS inverter. The auto-zero'ing of inverter Il causes the input and output of Il to be set at the toggle (or flip) point of the inverter. For ease of explanation, assume inverter Il to have an operating potential (VDD) of 5 volts, and to be symmetrical, whereby its toggle point may then be assumed to be 2.5 volts (i.e. VDD/2). Following the coupling ol VREF to
- 3 - RC~. 81,831 1 node 1 and the auto-zero'ing of Il, clock signals are a2plied to transmission gates TG2 and TG3 to turn them OFF. Transmission gate TGl is then enabled to couple VIN to node 1. The voltage difference between VIN and VREF is then amplified about the toggle point of inverter Il.
However, a major problem with the circuit of FIGURE 1 occurs when TG2 (or TGl~ is disabled. For then, uncompensated charge is injected onto sample and hold node 1 by the disabling clock signal transitions applied to TG2 (or TGl) and TG3 and an offset voltage is generated at node 1, which alters the true value of VREF (or VI~) previously applied to that node, and is therefore an error signal.
For example, assume that a gating signal of +5 volts is applied to the gate electrodes of NG2, NG3 and PGl and tha~ a gating si~nal o~ O volts is applied to the gate electrodes o~ PG2, PG3 and NGl. Consequently, TG2 and ~G3 are ON and TG1 is Off. Assurne also that: 1) VREF is at 0 volts whereby node 1 is charged to O volts via TG2; and 2) nodes 2 and 3 are charged to 2.5 volts due to the turn-on of TG3 and inverter Il being a complementary, symmetrical, inverter. A detailed examination of TG2 for the assumed signal condition reveals that the gate, source and drain of PG2 are at, or close to, zero volts. For this signal condition PG2 does not have a conduction channel between its source and drain and its parasitic capacitances (i.e. CGl and CG2) are set to "Low"
capacitance values. By way of example, the "low"
parasitic capacitance values may be assumed to be in the order o 0.01 picofarad (pf). On the other hand, the gate of NG2 is at 5 volts while its source and drain are at O
volts. The 5 volt differential between the gate and the source/drain ensures that NG2 is ON, that there is a conduction ch~nnel (enhancement layer) between its source and drain, and that the parasitic capacitance oE NG2 are set to "high" capacitance values. By way of example, the "high" parasitic capacitance value of each parasitic capacitor may be assumed to be in the order of 0.03 ,.. ~ . .
However, a major problem with the circuit of FIGURE 1 occurs when TG2 (or TGl~ is disabled. For then, uncompensated charge is injected onto sample and hold node 1 by the disabling clock signal transitions applied to TG2 (or TGl) and TG3 and an offset voltage is generated at node 1, which alters the true value of VREF (or VI~) previously applied to that node, and is therefore an error signal.
For example, assume that a gating signal of +5 volts is applied to the gate electrodes of NG2, NG3 and PGl and tha~ a gating si~nal o~ O volts is applied to the gate electrodes o~ PG2, PG3 and NGl. Consequently, TG2 and ~G3 are ON and TG1 is Off. Assurne also that: 1) VREF is at 0 volts whereby node 1 is charged to O volts via TG2; and 2) nodes 2 and 3 are charged to 2.5 volts due to the turn-on of TG3 and inverter Il being a complementary, symmetrical, inverter. A detailed examination of TG2 for the assumed signal condition reveals that the gate, source and drain of PG2 are at, or close to, zero volts. For this signal condition PG2 does not have a conduction channel between its source and drain and its parasitic capacitances (i.e. CGl and CG2) are set to "Low"
capacitance values. By way of example, the "low"
parasitic capacitance values may be assumed to be in the order o 0.01 picofarad (pf). On the other hand, the gate of NG2 is at 5 volts while its source and drain are at O
volts. The 5 volt differential between the gate and the source/drain ensures that NG2 is ON, that there is a conduction ch~nnel (enhancement layer) between its source and drain, and that the parasitic capacitance oE NG2 are set to "high" capacitance values. By way of example, the "high" parasitic capacitance value of each parasitic capacitor may be assumed to be in the order of 0.03 ,.. ~ . .
- 4 RCA 81,831 1 piCofarad (pf)o When the clock signal CLR makes a neg3tive going transition from ~5 volts to 0 volts and CLR makes 3 positive going transition from 0 volts to +5 volts, TG2 is disabledO For these gating conditions, it W35 expected that the ~alling edge of CLR would cancel the rising edge of CLR. However, as noted above, Applicants discovered, 3S shown in FIGURE 2, that when a VREF (or a VIN) of ~ero volts is propagated via TG2 (or TGl) to node 1 and TG2 (or TGl) is subsequently disabled, 3 negative charge is trapped at node 1 resulting in a negative voltage offset of up to 50 millivolts being produced at node 1. Applicants recogni2ed that the offset was, to a great extent, due to: a) the initial 15 differences in the parasitic capacitance of NG2 and PG2;
and b) the difference in the responses of NG2 and PG2 to the turn-off signal. The negative going t~ansition of CLR is coupled via the initially "high" parasitic capacitance Oe NG2 to node 1 while the positive transition 20 of CLR is coupled via the initially "low" parasitic capacitance of PG2 to node 1. Hence it is evident that more negative charge than positive charge will be injected into node l. But, perhaps even more important, as CLR
goes negative and CLR goes positive, and with VREF=0, 25 NG2 is driven from a high (e.g., 0.03 pf) parasitic capacitance state to a low ~e.g., 0.01 pf) parasitic capacitance state while PG2 is driven from a low (eg., 0.01 pf) parasitic capacitance state to an even still "lower" (e.g., 0.005 pf) parasitic capacitance state.
30 Thus Applicants recognized that, for certain siynal or bias levels, the complementary transistors of the transmission gate, although driven by complementary signals, do not respond in a complementary manner.
Consequently, more negative charge is injected via CG2 35 of NG2 into node 1 than positive charge is injected via the CG2 of PG2, and the negative charge trapped at node 1 produces a negative offset (error) voltage at that node.
In an analogous manner when VREF is at, or near 5 volts, and TG2 is ON, NG2 is in a low capacitance state .
and b) the difference in the responses of NG2 and PG2 to the turn-off signal. The negative going t~ansition of CLR is coupled via the initially "high" parasitic capacitance Oe NG2 to node 1 while the positive transition 20 of CLR is coupled via the initially "low" parasitic capacitance of PG2 to node 1. Hence it is evident that more negative charge than positive charge will be injected into node l. But, perhaps even more important, as CLR
goes negative and CLR goes positive, and with VREF=0, 25 NG2 is driven from a high (e.g., 0.03 pf) parasitic capacitance state to a low ~e.g., 0.01 pf) parasitic capacitance state while PG2 is driven from a low (eg., 0.01 pf) parasitic capacitance state to an even still "lower" (e.g., 0.005 pf) parasitic capacitance state.
30 Thus Applicants recognized that, for certain siynal or bias levels, the complementary transistors of the transmission gate, although driven by complementary signals, do not respond in a complementary manner.
Consequently, more negative charge is injected via CG2 35 of NG2 into node 1 than positive charge is injected via the CG2 of PG2, and the negative charge trapped at node 1 produces a negative offset (error) voltage at that node.
In an analogous manner when VREF is at, or near 5 volts, and TG2 is ON, NG2 is in a low capacitance state .
- 5 - RCA 81,831 1 and PG2 is in a high capacitance state. ~hen TG2 is subsequently turned-off: 3) the gate of PG2 is driven from 0 volts to ~5 volts with its source-drain path remaining close to ~5 volts. PG2 is then driven from a "high" parasitic capacitance (e.g~ 0.03 pf) state to a "low" parasitic capacitance (e.g. 0.0l pf) state; and b) the gate of NG2 is driven from ~5 volts to 0 volts with its source to drain path remaining at ~5 volts. NG2 is then driven from a "low" parasitic capacitance (e.g. 0.01 pf)to a still "lower" parasitic capacitance ~e.g. 0.005 pf) state~ Consequently, the positive going CLR
transition injects more positive charge into node 1 via CG2 of PG2 than the negative going CLR transition injects via CG2 of NG2. Hence a positive voltage oEfset is produced at node 1.
~ s shown in ~IGURE 2, the offset introduce~ at node 1 is a function o~ the voltage level translated along the conduction path o complementary transistor transmission gates. The offset voltage is a maximum at the extreme range ~e.g. 0 and 5 volts) of the voltages being translated and a minimum midway between the extremes.
When the voltage level (e.g. VREF, VIN or Vbias) along the conduction paths of the transmission gates is mid-way (e.g. 2~5 v) between the high ~e.g. 5 volts) and low te.g. 0 volts) levels of the clocklng signal transitions the transmission gates are operated in a very symmetrical manner. Charge trapping is then approximately compensated and the resultant offset is negligible.
Conventional complementary transmission gate operation results in voltage offsets of up to +50 millivolts over the full range of the signal input or reference voltage levels, as shown in FIGURE 2. This is unacceptable where it is desired to sample the input and reference voltages and compare them with an accuracy of 1 millivolt (0.001 volt) when using 5 volt clock signals (some 5000 times greater than the detection level) without injecting contaminating charge.
As discussed above, Applicants' invention resides, in part, in the recognition ~hat, for a variety of factors,
transition injects more positive charge into node 1 via CG2 of PG2 than the negative going CLR transition injects via CG2 of NG2. Hence a positive voltage oEfset is produced at node 1.
~ s shown in ~IGURE 2, the offset introduce~ at node 1 is a function o~ the voltage level translated along the conduction path o complementary transistor transmission gates. The offset voltage is a maximum at the extreme range ~e.g. 0 and 5 volts) of the voltages being translated and a minimum midway between the extremes.
When the voltage level (e.g. VREF, VIN or Vbias) along the conduction paths of the transmission gates is mid-way (e.g. 2~5 v) between the high ~e.g. 5 volts) and low te.g. 0 volts) levels of the clocklng signal transitions the transmission gates are operated in a very symmetrical manner. Charge trapping is then approximately compensated and the resultant offset is negligible.
Conventional complementary transmission gate operation results in voltage offsets of up to +50 millivolts over the full range of the signal input or reference voltage levels, as shown in FIGURE 2. This is unacceptable where it is desired to sample the input and reference voltages and compare them with an accuracy of 1 millivolt (0.001 volt) when using 5 volt clock signals (some 5000 times greater than the detection level) without injecting contaminating charge.
As discussed above, Applicants' invention resides, in part, in the recognition ~hat, for a variety of factors,
- 6 - RCA 81,831 complementary transmission gates do no-t provide compensation against contamination from gating signals throughout the range of input for reference signal level being translated via the complementary transmission gates.
Applicants' invention also resides in means for compensating comp~lementary transmission gates to obtain very little offset. In circuits embodying the invention, each IGFET of a complementary transmission gate has associated with it a corresponding "dummy" device of like conductivity type. Each dummy device is operated in a complementary manner to its corresponding transmission gate IGFET to provide subs-tantial cancellation of -the ga-tincJ signals which are capaci-tively coupled to -the conduc-t.ion paths o:E t.he I.GFETs.
For this reason, the circuit is illustrated in the drawing as employing such transistors and will be so described hereinafter. However, this i.s not intended to preclude the use of other suitable devices and to this end, the term "transistor", when used without limitation in the appended claims, is used in a generic sense.
~ - .
6~
Applicants' invention also resides in means for compensating comp~lementary transmission gates to obtain very little offset. In circuits embodying the invention, each IGFET of a complementary transmission gate has associated with it a corresponding "dummy" device of like conductivity type. Each dummy device is operated in a complementary manner to its corresponding transmission gate IGFET to provide subs-tantial cancellation of -the ga-tincJ signals which are capaci-tively coupled to -the conduc-t.ion paths o:E t.he I.GFETs.
For this reason, the circuit is illustrated in the drawing as employing such transistors and will be so described hereinafter. However, this i.s not intended to preclude the use of other suitable devices and to this end, the term "transistor", when used without limitation in the appended claims, is used in a generic sense.
~ - .
6~
- 7 - ~CA 81,831 1 In the FIGURES, enhancement type IGFETs of P-conductivity type are identified by the letter P
followed by 3 particular reference numeral, and enhancement type IGEETs of N-conductivity type are identified by the letter N followed by a particular reference numeral. The characteristics of IGFETs are well known and need not be described in detail. But, for a clearer understanding of the description to follow, the following definitions and characteristics pertinent to the invention are set forth:
1. Each IGFET has first and second electrodes which define the ends of its conduction path and a control electrode (gate) whose applied potential deter~nines the conductivity of its conduction path. The first and second electrode9 of an IGFET are referred to as the source and drain electrodes. For a P-type IGFET the source electrode is defined as that one oE the Eirst and second electrodes having the more positive (higher) potential applied thereto. For an N-type IGFET, the source electrode is 20 defined as that one of the first and second electrodes having the less positive (lower) potential applied thereto.
2. Conduction occurs when the applied gate-to-source potential (VGs) is in a direction to turn on the transistor and is greater in magnitude than a given value, 25 which is defined as the threshold voltage (VT) of the transistor. To turn on a P-type enhancement IGFET its gate voltage (VG) has to be more negative than its source voltage (Vs) by at least VT. To turn on an N-type enhancement IGFET its VG has to be more positive than its Vs by VT.
3. IGFETs are bidirectional in the sense that when an enabling signal is applied to the control electrode, current can flow in either direction in the conduction path defined by the first and second electrodes, i.e. the source and drain are interchangeable.
4, In the drawing and in the discussion to follow, the parasitic gate to drain/source capacitances tCG~ and CGD) are identified as C~l and CG2 since the source and drain are interchangeable, particularly when the
followed by 3 particular reference numeral, and enhancement type IGEETs of N-conductivity type are identified by the letter N followed by a particular reference numeral. The characteristics of IGFETs are well known and need not be described in detail. But, for a clearer understanding of the description to follow, the following definitions and characteristics pertinent to the invention are set forth:
1. Each IGFET has first and second electrodes which define the ends of its conduction path and a control electrode (gate) whose applied potential deter~nines the conductivity of its conduction path. The first and second electrode9 of an IGFET are referred to as the source and drain electrodes. For a P-type IGFET the source electrode is defined as that one oE the Eirst and second electrodes having the more positive (higher) potential applied thereto. For an N-type IGFET, the source electrode is 20 defined as that one of the first and second electrodes having the less positive (lower) potential applied thereto.
2. Conduction occurs when the applied gate-to-source potential (VGs) is in a direction to turn on the transistor and is greater in magnitude than a given value, 25 which is defined as the threshold voltage (VT) of the transistor. To turn on a P-type enhancement IGFET its gate voltage (VG) has to be more negative than its source voltage (Vs) by at least VT. To turn on an N-type enhancement IGFET its VG has to be more positive than its Vs by VT.
3. IGFETs are bidirectional in the sense that when an enabling signal is applied to the control electrode, current can flow in either direction in the conduction path defined by the first and second electrodes, i.e. the source and drain are interchangeable.
4, In the drawing and in the discussion to follow, the parasitic gate to drain/source capacitances tCG~ and CGD) are identified as C~l and CG2 since the source and drain are interchangeable, particularly when the
- 8 - RCA 81,831 1 IGFETs are operated as transmission gates.
In the discussion to follow, a potential at, or near ground is arbitrarily defined as a logic "0" or "low"
condition and any potential at or near +VDD or +V volts is arbitrarily defined as a logic "1" or "high" condition.
The circuit of FIGURE 3 includes complementary transmission gates TGl and TG2 and their respective associated compensatory ("dummy") transmission gates CGTl and CGT2.
. TGl is intended to selectively couple an input.
voltage, VIN, between an input terminal 11 and a sample and hold node 1. TGl is comprised of complementary IGFETs PGl and NGl having their conduction paths connected in parallel between terminal 11 and node 1. CTGl is comprised of complementary IGFETs CPGl and CNGl having their conduction paths connected in parallel bet~een node 1 and a floating node, Fl. As discussed below CPGl and CNGl need only be connected in common at node 1 to provide parasitic capacitive coupling between their respective gate electrodes and the one end (source or drain) of their conduction paths connected to node 1. The other end o~
their conduction paths may be left floating 35 shown in ~IGURES 6A and 6B. The gate electrodes of NG1 and CPGl are connected in common to line 13 and are driven by a clock signal CLI applied to line 13. The gate electrodes of PGl and CNGl are connected in common to line 15 and are driven by a clock signal CLI appl.ied to line lS~ Clock signals CLI and CLI are complementary to each other as shown in FIGURE 4.
TG2 is comprised of complementary IGFETs PG2 and NG2 having their conduction paths connected in parallel between terminal 17 and node 1. CTG2 is comprised of complementary IGFETs CPG2 and CNG2 having their conduction paths connected in parallel between node 1 and a floating 3~ node, F2. As.for CPGl and CNGl, CPG2 and CNG2 need only be connected in common at node 1 to provide parasitic capacitive coupling between their gate electrodes and the one end (source or drain) of their conduction paths connected to node 1. The other end of their conduction ~Z~63LS~
In the discussion to follow, a potential at, or near ground is arbitrarily defined as a logic "0" or "low"
condition and any potential at or near +VDD or +V volts is arbitrarily defined as a logic "1" or "high" condition.
The circuit of FIGURE 3 includes complementary transmission gates TGl and TG2 and their respective associated compensatory ("dummy") transmission gates CGTl and CGT2.
. TGl is intended to selectively couple an input.
voltage, VIN, between an input terminal 11 and a sample and hold node 1. TGl is comprised of complementary IGFETs PGl and NGl having their conduction paths connected in parallel between terminal 11 and node 1. CTGl is comprised of complementary IGFETs CPGl and CNGl having their conduction paths connected in parallel bet~een node 1 and a floating node, Fl. As discussed below CPGl and CNGl need only be connected in common at node 1 to provide parasitic capacitive coupling between their respective gate electrodes and the one end (source or drain) of their conduction paths connected to node 1. The other end o~
their conduction paths may be left floating 35 shown in ~IGURES 6A and 6B. The gate electrodes of NG1 and CPGl are connected in common to line 13 and are driven by a clock signal CLI applied to line 13. The gate electrodes of PGl and CNGl are connected in common to line 15 and are driven by a clock signal CLI appl.ied to line lS~ Clock signals CLI and CLI are complementary to each other as shown in FIGURE 4.
TG2 is comprised of complementary IGFETs PG2 and NG2 having their conduction paths connected in parallel between terminal 17 and node 1. CTG2 is comprised of complementary IGFETs CPG2 and CNG2 having their conduction paths connected in parallel between node 1 and a floating 3~ node, F2. As.for CPGl and CNGl, CPG2 and CNG2 need only be connected in common at node 1 to provide parasitic capacitive coupling between their gate electrodes and the one end (source or drain) of their conduction paths connected to node 1. The other end of their conduction ~Z~63LS~
- 9 - RCA 81,831 1 paths may be left floating. The gate electrodes of ~G2 and CPG2 are connected in common to line 19 and are driven by a clock signal CLR applied to line 19. The gate electrodes of PG2 and CNG2 are connected in common to line 21 and are driven by a clock signal CLR applied to line 21. Clock signals CLR and CLR are complementary to each other as shown in FIGURE 4O
Node 1 is connected to one plate of a coupling capacitor Cc whose other plate is connected to the input of a complementary inverter Il. The conduction path of a complementary transmission gate TG3 comprised of IGFETs PG3 and NG3 is connected between the input and output of inverter Il. The conduction paths of PG3 and NG3 are connected in parallel between nodes 2 and 3, which define the input and output nodes, respectively, of inverter Il.
In this embodiment CLR is applied to the gate electrode of NG3 and CLR is applied to the gate electrode Oe PG3 whereby TG2 and TG3 are either turned-on or turned-oef at the same time.
Transmission gate TG3 functions to "auto-zero"
inverter Il. That is, when TG3 is enabled inverter Il is driven to its toggle point with the voltage at node 2 being essentially equal to the voltage at node 3. For the case where Il is symmetrical it may be assumed that the turn-on of TG3 causes the voltage (V2) at its input node 2 and the voltage (V3) at the output of Il to go to VDD/2; where VDD volts is assumed to be 5 volts, VDD/2 is equal to 2.5 volts. The clock signals ~CLR, CLR and CLI, CLI) make transitions between 0 and Svolts. When TG3 is being disabled ti.e. turned-off), the gate voltage of PG3 goes from 0 volts to +5 volts while the gate voltage of NG3 goes from 5 volts to zero volts.
With the voltage at the drains and sources of PG3 and NG3 at VDD/2, CGl and CG2 of PG3 are approximately equal to CGl and CG2 of NG3. Hence the effect of the complementary clock transitions appliea to the gate electrodes of PG3 and NG3 is substantially cancelled at these nodes. For this reason no compensation is provided for transmission gate TG3.
~6~5g
Node 1 is connected to one plate of a coupling capacitor Cc whose other plate is connected to the input of a complementary inverter Il. The conduction path of a complementary transmission gate TG3 comprised of IGFETs PG3 and NG3 is connected between the input and output of inverter Il. The conduction paths of PG3 and NG3 are connected in parallel between nodes 2 and 3, which define the input and output nodes, respectively, of inverter Il.
In this embodiment CLR is applied to the gate electrode of NG3 and CLR is applied to the gate electrode Oe PG3 whereby TG2 and TG3 are either turned-on or turned-oef at the same time.
Transmission gate TG3 functions to "auto-zero"
inverter Il. That is, when TG3 is enabled inverter Il is driven to its toggle point with the voltage at node 2 being essentially equal to the voltage at node 3. For the case where Il is symmetrical it may be assumed that the turn-on of TG3 causes the voltage (V2) at its input node 2 and the voltage (V3) at the output of Il to go to VDD/2; where VDD volts is assumed to be 5 volts, VDD/2 is equal to 2.5 volts. The clock signals ~CLR, CLR and CLI, CLI) make transitions between 0 and Svolts. When TG3 is being disabled ti.e. turned-off), the gate voltage of PG3 goes from 0 volts to +5 volts while the gate voltage of NG3 goes from 5 volts to zero volts.
With the voltage at the drains and sources of PG3 and NG3 at VDD/2, CGl and CG2 of PG3 are approximately equal to CGl and CG2 of NG3. Hence the effect of the complementary clock transitions appliea to the gate electrodes of PG3 and NG3 is substantially cancelled at these nodes. For this reason no compensation is provided for transmission gate TG3.
~6~5g
- 10 - RCA 81,831 1 The compensation provided by the compensating ("dummy") transmission gates is now further detailed.
Assume, by way of example, that VREF is first applied Vi3 TG2 to sample and hold node 1 beginning at time tl by CLR going high and CL~ going low, as shown in FIGURE 4, and that, concurrently, inverter Il is auto-zero'ed by the turn-on of TG3. During the application of VREF tactually until time tS) CLI is low and CLI is high whereby TGl is turned-off.
The turn-on of TG3 causes V2 and V3 to go to, or near, VDD/2 volts. The turn-on of TG2 causes VRE~ which may have any value in the range between 0 volts and 5 volts, to be applied via the conduction paths of PG2 and NG2 to node 1. Thus at time t3, Vl is charged (or discharged) to VREF and V2 is set at, or close to VDD/2.
At time t3, CLR goes Erom high-to-low and C~R goes from low-to-high turning-off TG2 and TG3 and turning ON
CTG2. The response of TG2 and CTG2 will now be disc~ssed assuming VREF to have been equal to zero volts and Vl to be charged to zero volts. (a) Just prior to time t3, the gate of NG2 is at ~5 volts while its source and drain are at 0 volts. For this turn-on condition NG2 is set to a "high" parasitic capacitance condition as shown in the characteristic curve of FIGURE 5A which shows how the 2S parasitic capacitance between the gate and source/drain varies as a function of the potential between the gate and the source/drain, for an N-type IGFET. From FIGURE 5A, each one of CGl and CG2 of NG2 may be assumed to equal 0.03 pf. Between time t3 and t4 the gate of NG2 is driven from 5 volts to 0 volts, while the potential, Vl, at node 1 remains close to zero volts. With the gate-to-source potential of NG2 at zero volts, CG2 of NG2 goes to a "low" capacitance value which may be assumed to be equal to 0.01 pf. Thus from time t3 to t4, the parasitic capacitance ef NG2 goes from a "high" value to a "low"
value. (b) Just prior to time t3, the gate, source and drain of CNG2 are at 0 volts. CNG2 is then set to a "low"
capacitance value. Between time t3 and t4, the gate of CNG2 is driven from 0 volts to ~5 volts while its :: L24G~9 ~ RCA 81,831 1 source/drain remains at zero volts, setting CNG2 to 3 "high" parasitic cap3cit3nce condition. The operation of ~G2 and CNG2 is therefore highly complementary whereby their complementary gating signals tend to cancel to a 5 high degree. (c) Just prior to time t3, the gate, drain and source of PG2 are at zero volts placing PG2 in a non-conducting 'llow" parasitic capacitance state. Between time t3 and t4, the gate o~ PG2 is driven to ~5 volts while its source/drain remains at zero volts. This causes 10~ PG2 to be turned-off more, with an effective reverse bias of 5 volts, and to be placed in a still "lower"
capacitance state as shown in the characteristic curve of FIGURE 5B which shows how the parasitic capacitance of a P-type device varies as a function of gate-to-source/drain 15 voltage. Therefore, very little of the positive going transition of CLR occurring between time t3 and t4 is coupled into node 1. ~d) Just prior to time t3, the gate o~ CPG2 is at -~5 volts while its source and drain are at 0 volts. CPG2 is ~hen set to a "lower" parasitic 20 capacitance as shown in FIGURE 5B. When CLR goes from ~5 volts to 0 volts between time t3 and t4, the gate of CPG2 is driven to 0 volts and the drain and source of CPG2 remain at tha~ level. CPG2 is then placed in a "low"
parasitic capacitance state. Thus, between time t3 and 25 t4, PG2 is driven from a "low" to a "lower" capacitance state while CPG2 is driven from a "lower." to a "low"
capacitance state. The complementary gating signals applied to the gate electrode of PG2 and CPG2 then tend to cancel each other and very little offset is produced at 30 node 1 as shown in FIGURE 4.
FIGURE 4 shows how the voltage (Vl) at node 1 varies as a function of the switching transients applied to the gates of the transmission gate transistors. The waveforms of FIGURE 4 are somewhat idealized being actually 35 relatively co~plex. However, the point to be noted is that in circuits embodying the invention, there is a significant reduction in the offset with very little charge being trapped upon the turn-off of TG2 (or TGl).
The portion of FIGURE 4 labeled A depicts the idealized - 12 - RCA 81,831 1 response at Vl for VREF and VIN being at zero volts and the portion labeled B depicts the idealized response at Vl for VREF and VIN being 3 5 When VREF is ~5 volts, it can be shown that CTG2 provides a high degree of compensation for TG2, for analogous reasons to the ones disc~ssed aboveD In this instance when TG2 is being turned-off, after having sampled VREF and coupled VREF to node 1, the circuit has the following proper~ies:
(a) NG2 goes from a "low" capacitance state (its gate, drain and source were initially at ~5 volts) to a "lower" capacitance state (its gate goes to zero while its drain and source remain at ~5 volts);
(b) CNG2 goes from a "lower" capacitance state (since its gate was zero while its source and dr3in were at ~5 volts) to a "low" capacitance state (since its gate goes to +5 volts while its source and drain remain at ~5 volts;
(c) PG2 goes from a "high" capacitance state (since its gate was at zero volts while its source and drain were at +5 volts) to a "low" capacitance state (since its gate, source and drain are then at ~5 volts); and (d) CPG2 goes from a "lo~" capacitance state (since its gate, source and drain were at l5 volts) to a "high"
capacitance state (its gate goes to zero volts while its source and drain re~ain at ~5 volts).
As before, CNG2 varies in an inverse manner to NG2 and CPG2 varies in an inverse manner to PG2. The gating signals coupled via their parasitic capacitances will then tend to cancel. The high degree of compensation obtained at ~ volts with the addition of the compensating ("dummy") devices (CPG2, CNG2 and/or CPGl, CNGl) is shown in portion B of FIGURE 4.
It is evident that where a high degree of compensation 36 is obtalned `at the extreme ends of the levels being translated, an even higher degree of compensation is present within the middle range, between 0 and ~5 volts.
In the circuit of FIGURE 3, a high degree of canGellation results since reliance is now made on a ~;~46~5~
- 13 - RCA 81,831 1 P~dummy device (e.g. CPG2) to cancel the effect of 3 P-type IGFET (e.g. PG2) and on an N-dummy device (e.g.
C~G2) to cancel the effect of an N-type IGFET (e.g. NG2).
The gating signals as shown in FIGURE 4 may be designed to have relatively symmetrical rise and fall times to ensure that the gating signals comple~ent each other to a great extent. Best compensation is achieved when waveforms are symmetrical, but the present compensating scheme has considerable tolerance even where the gating signals are not exactly symmetrical.
An important aspect of the invention is that in Applicants' invention, the "dummy" devices need not be full transistors. That is, each dummy device may include connection to a single diffused region (source or drain) 16 with a gate/channel region adjacent to the diffused region. This is illustrated in FIGURES 6A and 6B. FIGURE
6A is a cross section of a compensating N device (CN) and a compensating P device (CP). The CN-device has two regions (62, 64) of N~ conductivity type separated by a channel (or substrate) region, and a gate electrode 61 overlying the channel and isolated therefrom. The CP-device likewise has two regions (66, 68) of P~
conductivity type separated by a channel region, and a gate electrode 63 overlying the channel and isolated therefrom. Complementary gating signals (clock and clock) are applied to the gate electrodes of the CN and CP
devices. Only one N~ region of CN and only one P~ region of CP are shown connected in common to node 1. Regions 64 and 68 need not be connected to anythin$ reducing the space needed to lay out the CP and CN devices. Further-more regions 62 and 68 can be made smaller than regions 64 and 66, further reducing the space required. ~IGURE 6B
shows the equivalent schematic diagram of the structure of FIGURE 6A. Note that CNGl and CPGl, or CNG2 and CPG2 could be for~e~d as shown in FIGURE 6A and/or replaced by devices having the equivalent circuit shown in FIGURE 6B.
The structure of FIGURE 6 enables very small devices to be formed. This is a distinct advantage in a high density array since it allows minimum design rule devices.
~2~6~
- 14 - RCA 81,831 1 This arrangement is also important in that it enables very small capacitances to be formed reducing the loading effect on the sample/hold node. Also, the dummy device may be made to have a comparable geometry to the IGFET
5 which it is intended to compensate. So formed, process variations tend to cancelO
Another important aspect of Applicants' invention relates to the application of the clocking signals to the transmission gates. Referring to FIGURE 4, note that 10 CLR and CLR are designed to turn-off TG2 and`TG3 before CLI and CLI turn-on TGl~ The "break" before "make" clocking arrangements ensure that the high degree of compensation produced at node 1 is not affected~by interaction between the reference voltage and input signal 15 clocking signals and by interaction between the reference voltage and the input signal voltage. Also, turnlng-off TG2 before turning-on TGl ensures that VREF is never shorted to VIN.
It would appear that turning-on TGl 3S TG2 is being 20 turned-off would obviate the need for separate compensation devices associated with each complementary transmission gate. However, Applicants discovered that the break before make arrangement is preferable to turning-on TGl as TG2 is being turned-off and provides a 25 much higher degree of, and more reliab~e, compensation.
In the circuit of FIGURE 3, compensation was provided for each one of TGl and TG2. It was found that in some applications it was s~fficient to provide a "compensatory transmission gate" for only the gate TGl coupling VIN
into the system. However in this instance, the sizings of C~Gl and CPGl had to be increased over the full compensation scheme of FIGURE 3 to provide compensation for TG2.
Assume, by way of example, that VREF is first applied Vi3 TG2 to sample and hold node 1 beginning at time tl by CLR going high and CL~ going low, as shown in FIGURE 4, and that, concurrently, inverter Il is auto-zero'ed by the turn-on of TG3. During the application of VREF tactually until time tS) CLI is low and CLI is high whereby TGl is turned-off.
The turn-on of TG3 causes V2 and V3 to go to, or near, VDD/2 volts. The turn-on of TG2 causes VRE~ which may have any value in the range between 0 volts and 5 volts, to be applied via the conduction paths of PG2 and NG2 to node 1. Thus at time t3, Vl is charged (or discharged) to VREF and V2 is set at, or close to VDD/2.
At time t3, CLR goes Erom high-to-low and C~R goes from low-to-high turning-off TG2 and TG3 and turning ON
CTG2. The response of TG2 and CTG2 will now be disc~ssed assuming VREF to have been equal to zero volts and Vl to be charged to zero volts. (a) Just prior to time t3, the gate of NG2 is at ~5 volts while its source and drain are at 0 volts. For this turn-on condition NG2 is set to a "high" parasitic capacitance condition as shown in the characteristic curve of FIGURE 5A which shows how the 2S parasitic capacitance between the gate and source/drain varies as a function of the potential between the gate and the source/drain, for an N-type IGFET. From FIGURE 5A, each one of CGl and CG2 of NG2 may be assumed to equal 0.03 pf. Between time t3 and t4 the gate of NG2 is driven from 5 volts to 0 volts, while the potential, Vl, at node 1 remains close to zero volts. With the gate-to-source potential of NG2 at zero volts, CG2 of NG2 goes to a "low" capacitance value which may be assumed to be equal to 0.01 pf. Thus from time t3 to t4, the parasitic capacitance ef NG2 goes from a "high" value to a "low"
value. (b) Just prior to time t3, the gate, source and drain of CNG2 are at 0 volts. CNG2 is then set to a "low"
capacitance value. Between time t3 and t4, the gate of CNG2 is driven from 0 volts to ~5 volts while its :: L24G~9 ~ RCA 81,831 1 source/drain remains at zero volts, setting CNG2 to 3 "high" parasitic cap3cit3nce condition. The operation of ~G2 and CNG2 is therefore highly complementary whereby their complementary gating signals tend to cancel to a 5 high degree. (c) Just prior to time t3, the gate, drain and source of PG2 are at zero volts placing PG2 in a non-conducting 'llow" parasitic capacitance state. Between time t3 and t4, the gate o~ PG2 is driven to ~5 volts while its source/drain remains at zero volts. This causes 10~ PG2 to be turned-off more, with an effective reverse bias of 5 volts, and to be placed in a still "lower"
capacitance state as shown in the characteristic curve of FIGURE 5B which shows how the parasitic capacitance of a P-type device varies as a function of gate-to-source/drain 15 voltage. Therefore, very little of the positive going transition of CLR occurring between time t3 and t4 is coupled into node 1. ~d) Just prior to time t3, the gate o~ CPG2 is at -~5 volts while its source and drain are at 0 volts. CPG2 is ~hen set to a "lower" parasitic 20 capacitance as shown in FIGURE 5B. When CLR goes from ~5 volts to 0 volts between time t3 and t4, the gate of CPG2 is driven to 0 volts and the drain and source of CPG2 remain at tha~ level. CPG2 is then placed in a "low"
parasitic capacitance state. Thus, between time t3 and 25 t4, PG2 is driven from a "low" to a "lower" capacitance state while CPG2 is driven from a "lower." to a "low"
capacitance state. The complementary gating signals applied to the gate electrode of PG2 and CPG2 then tend to cancel each other and very little offset is produced at 30 node 1 as shown in FIGURE 4.
FIGURE 4 shows how the voltage (Vl) at node 1 varies as a function of the switching transients applied to the gates of the transmission gate transistors. The waveforms of FIGURE 4 are somewhat idealized being actually 35 relatively co~plex. However, the point to be noted is that in circuits embodying the invention, there is a significant reduction in the offset with very little charge being trapped upon the turn-off of TG2 (or TGl).
The portion of FIGURE 4 labeled A depicts the idealized - 12 - RCA 81,831 1 response at Vl for VREF and VIN being at zero volts and the portion labeled B depicts the idealized response at Vl for VREF and VIN being 3 5 When VREF is ~5 volts, it can be shown that CTG2 provides a high degree of compensation for TG2, for analogous reasons to the ones disc~ssed aboveD In this instance when TG2 is being turned-off, after having sampled VREF and coupled VREF to node 1, the circuit has the following proper~ies:
(a) NG2 goes from a "low" capacitance state (its gate, drain and source were initially at ~5 volts) to a "lower" capacitance state (its gate goes to zero while its drain and source remain at ~5 volts);
(b) CNG2 goes from a "lower" capacitance state (since its gate was zero while its source and dr3in were at ~5 volts) to a "low" capacitance state (since its gate goes to +5 volts while its source and drain remain at ~5 volts;
(c) PG2 goes from a "high" capacitance state (since its gate was at zero volts while its source and drain were at +5 volts) to a "low" capacitance state (since its gate, source and drain are then at ~5 volts); and (d) CPG2 goes from a "lo~" capacitance state (since its gate, source and drain were at l5 volts) to a "high"
capacitance state (its gate goes to zero volts while its source and drain re~ain at ~5 volts).
As before, CNG2 varies in an inverse manner to NG2 and CPG2 varies in an inverse manner to PG2. The gating signals coupled via their parasitic capacitances will then tend to cancel. The high degree of compensation obtained at ~ volts with the addition of the compensating ("dummy") devices (CPG2, CNG2 and/or CPGl, CNGl) is shown in portion B of FIGURE 4.
It is evident that where a high degree of compensation 36 is obtalned `at the extreme ends of the levels being translated, an even higher degree of compensation is present within the middle range, between 0 and ~5 volts.
In the circuit of FIGURE 3, a high degree of canGellation results since reliance is now made on a ~;~46~5~
- 13 - RCA 81,831 1 P~dummy device (e.g. CPG2) to cancel the effect of 3 P-type IGFET (e.g. PG2) and on an N-dummy device (e.g.
C~G2) to cancel the effect of an N-type IGFET (e.g. NG2).
The gating signals as shown in FIGURE 4 may be designed to have relatively symmetrical rise and fall times to ensure that the gating signals comple~ent each other to a great extent. Best compensation is achieved when waveforms are symmetrical, but the present compensating scheme has considerable tolerance even where the gating signals are not exactly symmetrical.
An important aspect of the invention is that in Applicants' invention, the "dummy" devices need not be full transistors. That is, each dummy device may include connection to a single diffused region (source or drain) 16 with a gate/channel region adjacent to the diffused region. This is illustrated in FIGURES 6A and 6B. FIGURE
6A is a cross section of a compensating N device (CN) and a compensating P device (CP). The CN-device has two regions (62, 64) of N~ conductivity type separated by a channel (or substrate) region, and a gate electrode 61 overlying the channel and isolated therefrom. The CP-device likewise has two regions (66, 68) of P~
conductivity type separated by a channel region, and a gate electrode 63 overlying the channel and isolated therefrom. Complementary gating signals (clock and clock) are applied to the gate electrodes of the CN and CP
devices. Only one N~ region of CN and only one P~ region of CP are shown connected in common to node 1. Regions 64 and 68 need not be connected to anythin$ reducing the space needed to lay out the CP and CN devices. Further-more regions 62 and 68 can be made smaller than regions 64 and 66, further reducing the space required. ~IGURE 6B
shows the equivalent schematic diagram of the structure of FIGURE 6A. Note that CNGl and CPGl, or CNG2 and CPG2 could be for~e~d as shown in FIGURE 6A and/or replaced by devices having the equivalent circuit shown in FIGURE 6B.
The structure of FIGURE 6 enables very small devices to be formed. This is a distinct advantage in a high density array since it allows minimum design rule devices.
~2~6~
- 14 - RCA 81,831 1 This arrangement is also important in that it enables very small capacitances to be formed reducing the loading effect on the sample/hold node. Also, the dummy device may be made to have a comparable geometry to the IGFET
5 which it is intended to compensate. So formed, process variations tend to cancelO
Another important aspect of Applicants' invention relates to the application of the clocking signals to the transmission gates. Referring to FIGURE 4, note that 10 CLR and CLR are designed to turn-off TG2 and`TG3 before CLI and CLI turn-on TGl~ The "break" before "make" clocking arrangements ensure that the high degree of compensation produced at node 1 is not affected~by interaction between the reference voltage and input signal 15 clocking signals and by interaction between the reference voltage and the input signal voltage. Also, turnlng-off TG2 before turning-on TGl ensures that VREF is never shorted to VIN.
It would appear that turning-on TGl 3S TG2 is being 20 turned-off would obviate the need for separate compensation devices associated with each complementary transmission gate. However, Applicants discovered that the break before make arrangement is preferable to turning-on TGl as TG2 is being turned-off and provides a 25 much higher degree of, and more reliab~e, compensation.
In the circuit of FIGURE 3, compensation was provided for each one of TGl and TG2. It was found that in some applications it was s~fficient to provide a "compensatory transmission gate" for only the gate TGl coupling VIN
into the system. However in this instance, the sizings of C~Gl and CPGl had to be increased over the full compensation scheme of FIGURE 3 to provide compensation for TG2.
Claims (8)
1. A circuit wherein: a first insulated-gate field-effect transistor of first conductivity type (N) and a second IGFET of second conductivity type (P) have conduction paths thereof connected in parallel between first and second nodes for translating a signal (VIN or VREF) between said first and second nodes; said second node is coupled via a capacitor to the input of an amplifier;
and a control signal is applied to the gate electrode of said first IGFET and the complement of said control signal is applied to the gate electrode of said second IGFET; and in order to cancel any voltage offset produced at said second node due to capacitive coupling of the control signal, or its complement, there are provided:
third and fourth insulated-gate field-effect devices of said first and second conductivity type, respectively, said third device having a first region of first conductivity type and a control electrode insulated therefrom; and said fourth device having a first region of second conductivity type and a control electrode insulated from its first region; where said first regions of said third and fourth devices being connected to each other and to said second node; and said control signal is applied to the control electrode of said fourth device, and said complement of said control signal is applied to the control electrode of said third device.
and a control signal is applied to the gate electrode of said first IGFET and the complement of said control signal is applied to the gate electrode of said second IGFET; and in order to cancel any voltage offset produced at said second node due to capacitive coupling of the control signal, or its complement, there are provided:
third and fourth insulated-gate field-effect devices of said first and second conductivity type, respectively, said third device having a first region of first conductivity type and a control electrode insulated therefrom; and said fourth device having a first region of second conductivity type and a control electrode insulated from its first region; where said first regions of said third and fourth devices being connected to each other and to said second node; and said control signal is applied to the control electrode of said fourth device, and said complement of said control signal is applied to the control electrode of said third device.
2. In the circuit as claimed in claim 1 wherein said control signal is connected directly to the control electrode of said fourth device and to the gate electrode of said first IGFET; and said complement of said control signal is connected directly to the control electrode of said third device and to the gate electrode of said second IGFET.
RCA 81,831
RCA 81,831
3. In the circuit as claimed in claim 2 wherein said first conductivity type is N-conductivity type and said second conductivity type is P-conductivity type.
4. In the circuit as claimed in claim 3 wherein said third device includes a second region of said first conductivity type; and said fourth device includes a second region of said second conductivity type; and wherein said second regions of said second and third devices are unconnected to any circuit point.
5. The circuit as claimed in claim 1, wherein each of said third and fourth devices includes a second region spaced apart from said first region and of conductivity type the same as said first region.
6. The circuit as claimed in claim 1, and further including a third node for the application thereto of a signal to be compared with the signal at said first node; and fifth and sixth IGFETs of first and second conductivity, respectively, having conduction paths thereof connected in parallel between said third node and said second node;
and wherein there are further provided:
seventh and eighth insulated-gate field-effect devices of said first and second conductivity type, respectively;
said seventh device having a first region of said first conductivity type and a control electrode insulated therefrom, and said eighth device having a first region of said second conductivity type and a control electrode insulated therefrom; and wherein a second control is applied to said gate electrodes of said fifth IGFET and of said eighth device and the complement of said second control signal is applied to said gate electrodes of said sixth IGFET and of said seventh device.
RCA 81,831
and wherein there are further provided:
seventh and eighth insulated-gate field-effect devices of said first and second conductivity type, respectively;
said seventh device having a first region of said first conductivity type and a control electrode insulated therefrom, and said eighth device having a first region of said second conductivity type and a control electrode insulated therefrom; and wherein a second control is applied to said gate electrodes of said fifth IGFET and of said eighth device and the complement of said second control signal is applied to said gate electrodes of said sixth IGFET and of said seventh device.
RCA 81,831
7. In the circuit as claimed in claim 6, wherein said control signal and the complement thereof applied to respective control electrodes of said first and second IGFETs are of a polarity and magnitude to either turn said first and second IGFETs ON at the same time or OFF at the same time; and wherein said second control signal, and the complement thereof applied to respective control electrodes of said fifth and sixth IGFETs are of a polarity and magnitude to either turn said fifth and sixth IGFETs ON at the same time or OFF at the same time.
8. In the circuit as claimed in Claim 7, wherein said control signal and said second control signal are phased for turning-off said first and second IGFETs before turning-on said fifth and sixth IGFETs, and for turning off said fifth and sixth IGFETs before turning-on said first and second IGFETs.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US70119885A | 1985-02-13 | 1985-02-13 | |
| US701,198 | 1985-02-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1246159A true CA1246159A (en) | 1988-12-06 |
Family
ID=24816429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000501608A Expired CA1246159A (en) | 1985-02-13 | 1986-02-11 | Transmission gates with compensation |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH0683046B2 (en) |
| KR (1) | KR900006063B1 (en) |
| CA (1) | CA1246159A (en) |
| DE (1) | DE3604400A1 (en) |
| FR (1) | FR2577363A1 (en) |
| GB (1) | GB2170954B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3983414A (en) * | 1975-02-10 | 1976-09-28 | Fairchild Camera And Instrument Corporation | Charge cancelling structure and method for integrated circuits |
| JPS5370752A (en) * | 1976-12-07 | 1978-06-23 | Fujitsu Ltd | Transmission gate |
| JPS584491B2 (en) * | 1978-11-08 | 1983-01-26 | 日本電信電話株式会社 | semiconductor analog switch |
| JPS57166069A (en) * | 1981-04-07 | 1982-10-13 | Nec Corp | Analog switch |
| JPS584491A (en) * | 1981-06-30 | 1983-01-11 | Fujitsu Ltd | Boundary tracking circuit |
| US4467227A (en) * | 1981-10-29 | 1984-08-21 | Hughes Aircraft Company | Channel charge compensation switch with first order process independence |
| JPS5894232A (en) * | 1981-11-30 | 1983-06-04 | Toshiba Corp | Semiconductor analog switch circuit |
| JPS5994923A (en) * | 1982-11-22 | 1984-05-31 | Toshiba Corp | Analog switch circuit |
| DE3370190D1 (en) * | 1982-11-26 | 1987-04-16 | Nec Corp | Voltage comparator circuit |
-
1986
- 1986-02-06 GB GB08603004A patent/GB2170954B/en not_active Expired
- 1986-02-11 CA CA000501608A patent/CA1246159A/en not_active Expired
- 1986-02-12 DE DE19863604400 patent/DE3604400A1/en active Granted
- 1986-02-12 KR KR1019860000946A patent/KR900006063B1/en active IP Right Grant
- 1986-02-13 JP JP61030605A patent/JPH0683046B2/en not_active Expired - Fee Related
- 1986-02-13 FR FR8601977A patent/FR2577363A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| KR860006874A (en) | 1986-09-15 |
| JPS61200717A (en) | 1986-09-05 |
| GB8603004D0 (en) | 1986-03-12 |
| GB2170954A (en) | 1986-08-13 |
| FR2577363A1 (en) | 1986-08-14 |
| DE3604400C2 (en) | 1990-02-22 |
| DE3604400A1 (en) | 1986-08-14 |
| KR900006063B1 (en) | 1990-08-20 |
| JPH0683046B2 (en) | 1994-10-19 |
| GB2170954B (en) | 1988-09-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |