GB2170679A - Phase scatter detection and reduction circuit and method - Google Patents

Description

1 GB 2 170 679 A 1 SPECIFICATION It is known to detect phase scatter on an

oscillo- scope by monitoring the amplitude and phase rela Phase scatter detection and reduction circuit and tionship of the output signal from a playback equaliz method er. The oscilloscope is externally triggered by a clock 70 signal phase-locked to the output signal from the This invention relates in general to a circuit and equalizer. The thusly obtained signal on the oscillo method for detecting and reducing phase scatter in scope screen is generally referred to as an "eye information signals transmitted over a channel, in- pattern", because of its shape resembling a human cluding digital signals recorded on and reproduced eye. The equalizer is then manually adjusted for from a magnetic recording medium. 75 minimum phase scatter, that is to obtain zero axis Information signals transmitted over a channel are crossings of the eye pattern with the least amount of subjectto distortion due to the well known non- time spread. When the "sharpest" image of the eye constant amplitude response and non-linear phase pattern atzero axis crossings is obtained bythe responsewith frequency inherentto such channels. manual setting, it corresponds to a minimum phase When transmitting a digital data stream it may 80 scatter.

become distorted and attenuated cluetothe above- It is seen from the above description that che indicated non-uniform frequency response to such foregoing method of minimizing phase scatter is extentthatthe original information content may be inaccurate and subjectto operator error. In addition, seriously degraded or even lost. the above-described method is not useful in systems One example of such signal transmission channel is 85 with low signal-to- noise ratio, where the eye pattern is a magnetic recorder/reproducer, where the playback difficultto distinguish from noise. Furthermore, that amplitude response decreases at higher frequencies, method is notsuitablefor phase scatter adjustment by cluetothe combined effects of transducer-to-record- automatic control.

ing medium separation, thickness of the medium, In dig ital magnetic recording/playback systems it is transducing gap length losses, and otherwell known 90 known to utilize a so-called bit synchronization circuit, factors. A basic requirement for an ideal magnetic generally referredto as a "bitsync" circuit. Itemploys recording/reproducing channel is the abilityto trans- a voltage controlled oscillator and a digital phase mitsignals of all frequencies without introducing cletectorwhich are connected togetherto form a amplitude or phase changes dependent on frequency phase-locked loop. The phase detector receives an to avoid signal distortion. Therefore, it has been a 95 equalized digital data stream from a playback equaliz common practice to use playback amplitude equaliz- erand an output signal from the oscillator and it ers which provide an equalization response compen- provides a clocksignal synchronous with that data sating forthe above-indicated amplitude response so stream. The applicant has discovered that a minimum that a resulting relative flat response can be obtained phase scatter of the equalized signal is obtained when within a desired frequency range. However, these 100 the output signal frequency of the digital phase equalizers, togetherwith a playback head and pream- detector is at a minimum. Consequently, in accord plifier, which are commonly utilized in playback ance with the present invention the amount of phase circuits, may introduce phase shift. Such phase shift is scatter is detected by monitoring the switching particularly undesirable in digital recording/reproduc- frequency atthe output of the digital phase detector.

ing systems because it obscures accurate detection of 105 By adjusting the equalizerto obtain a minimum output signal transitions of the reproduced signal. Therefore signal frequencyfrom the phase detector, the phase amplitude equalizers are often followed by phase scatter is minimized.

equalizers providing an equalization response com- It is a particular advantage of the phase scatter pensating forthe phase shift. detection apparatus and method of the present In some instances, it may be desirable to compen- 110 invention that it is not dependent on a subjective sate for a previously mentioned non-li near phase evaluation by an operator, such as by observing an response of a channel, by utilizing phase equalizers, eye pattern as has been done in the prior art.

withoutthe use of amplitude equalizers. Furthermore, the present invention allows for auto When high density digital signals aretransmitted matic adjustment of the equalizer-for minimum phase over an essentially analog communication channel, 115 scatter.

such as may occurwhen they are reproduced from a It is a further important advantage of the present pre-recorded magnetic medium, the equalizer hasto invention that it provides repeatable measurement of be carefully adjusted for minimum phase scatter. phase scatter. That measurement may be used to Phase scatter occurs when the delay of the transmitted evaluate the quality of a communication channel or of digital data stream is non-uniform overthe frequency 120 portions thereof, such as a record and reproduce response band. As a result some signal transitions system.

occu r earlier and some others later with respect to Tests performed on the gap scatter detection and signal transitions of a reference clock signal which is reduction circuit of the present invention revealed up synchronous with the original data. This diminishes to a ten fold reduction in a bit error rate in data played the abilityto accurately distinguish between "zeroes" 125 back from a magnetic medium, in comparison with the and "ones" of the transmitted digital signal. For reduction obtained by prior art.

example, when self-clocking digital signals are trans- Theforegoing objects, advantages and features of mitted or recorded, phase scatter obscures the zero the present invention will become apparentfrom the axis crossings upon receipt of reproduction, thereby following detailed description and accompanying increasing the bit error rate of the signal. 130 drawings.

2 GB 2 170 679 A 2 Brief Description of the Drawings playback data stream. Particularly, the bit synchro-

FIGURE I isa blockdiagram illustrating a preferred nization circuit28, generally referredto as"bitsync" embodimentof a phase scatter detection circuitof the circuit, generates a reference clocksignal on line36 invention. which is phase lockedtothe outputsignal of limiter26 FIGURE 2 is a more detailed diagram corresponding 70 and which clock signal is generally referred to as to a portion of FIGURE 1. reproduce clock signal. In accordance with the present FIGURE 3 is a block diagram illustrating a preferred invention a frequency detector44 is coupled to an embodiment of a phase scatter reduction circuit of the output line 40 from a phase detector included in the bit invention. sync circuit 28 to monitor the rate of binary transitions, FIG URE 4 is an alternative embodiment correspond- 75 also referred to as switching frequency, on output line ing to a portion of FIGURE 2. 40. As it has been previously mentioned, the rate of FIGURES 5A and 513 are consecutive parts of a binarytransitions on the output line 40from the phase detailed schematic circuit diagram corresponding to a detector corresponds to the amount of phase scatter portion of FIGURE 1; of the equalized playbackdata on line 34.The FIGURE 6 shows an example of an outputsignal 80 equalizer 24 maybe adjusted atthe control inputs 25, characteristic from a phase-scatter detection circuitof 27to obtain a minimum rate of transistions on line40 the invention,as being dependentonthe equalizer as itwill be described laterin more detail.

adjustment; and FIGURE 2 shows an example of a more detailed FIGURE 7 is a flow chart of the operation performed circuit diagram of the bit sync circuit 28 and frequency by a portion of the circuit shown in FIGURE 3. 85 detector44 of FIGURE 1. The bit sync circuit 28 Detailed Description comprises a reference clocksignal generator, prefer

In thefollowing description like reference numerals ably implemented bya voltage controlled oscillator will be utilized to designate like elements in all the (VCO) 30 whose output is coupled via line 36 to a drawing FIGURES to facilitate comparison. digital phase detector 32. In the preferred embodi- FIGURE 1 shows an example of a portion of a 90 ment a type D flip-flop is utilized as the digital phase conventional magnetic recording/reproducing chan- detector32.

nel, including a reproduce head 20 and a preamplifier The bit sync circuit 28 operates as a well known 22, utilizing the phase scatter detection circuit of the phase locked loop as follows. The equalized digital invention. The reproduce head has a playbackwind- signal from the limiter 26 of FIG. 1 is received on line 34 ing 21 coupledto a preamplifier22, as well known in 95 and it is applied to the clock input of flip-flop 32. The D the art. The reproduce head 20 detects magneticflux inputof flip-flop 32 receives, via line 36, an output patterns recorded on a magnetic medium (not signal from theVCO 30. The outputsignal from the shown), such astape, disk, drum, etc. In this example output of theflip- flop 32 is applied via line 42 as a D.C.

the signal is recorded in the form of a digital data feedbacksignal to a control input4l of the VCO 30 as stream, such as utilizing Millersquare code, non- 100 follows. At every rising edge of the digital data on line return-to-zero code orany otherwell known digital 34which coincideswith a high level signal on line 36 code. The outputsignal from the head 20 is amplified from the VCO there is a high level output signal bythepreamplifier22. provided on line 42 from the flip-flop 32. Analogously, An amplitude and phase equalization circuit 24 is at every rising edge ofthe signal on line 34which is coupled to an output 31 or preamplifier22. As it has 105 coincidentwith a low level signal on line 36frorn the been mentioned previously, the circuit24 compen- VCO 30 there is a low output level signal on line 40. As satesfora non-constant amplitude response and/or a it iswell known from the operation bit sync circuits, non-linear phase response inherentto the recording/ whenthe feedback signal on line 42 is positive,the playback channel, so that a desired amplitude re- frequency of the VCO output signal on line 36 is sponsewhich substantially does not change with 110 reduced. Analogously, the frequency of the signal on frequency and a desired phase response which line 36 increases when the signal on line 42 is changes substantially linearly with frequency are negative.

respectively obtained. The equalizer 24 may be of a The resulting output signal on line 36 from VCO 30 is well known conventional design. However, preferably the previously described reproduce clock signal, that a voltage controlled amplitude equalizer of a novel 115 is, an internal system reference clockwhich is phase design is utilized which isthe subject matter of the locked to the equalized playback data stream on line copending patent application concurrently filed with 34.As itiswell known, the reproduce clocksignal is this application. The preferred embodimentofthe utilized in conventional signal transmission circuits, equalizer 24 of FIGURE 1 will be described in more including magnetic recording/reproducing circuits,to detail with reference to FIGURES 5A and 513. 120 restore and reclockthe reproduced digital data, so that The equalized signal obtained atthe output of a reproduced signal results which substantially dupli- equalizer circuit 24 is an analog signal. The amplitude catesthe originally recorded signal waveform.

of that signal is limited by a limiter 26 to obtain a digital It has been discovered bythe applicant in accord playback data stream corresponding to the recorded ance with the present invention that the frequency of data, as it is well known in the art. The output signal 125 switching provided bythe phase detector output on from the limiter 26 is applied via line 34to a bit line 40 is proportional to the amount of phase scatter synch ronizatio r, circuit 28. Circuit 28 is of a conven- of the digital signal on line 34. In the preferred tional design and it is known to be utilized with embodimentthat switching frequency correspondsto playback equalizers to obtain an internal system the rate of transitions of the bistable signal atthe reference clock signal which is synchronized to the 130output 40 from flip-flop 32. Consequently in accord- 3 GB 2 170 679 A 3 ance with one aspect of the present invention the signal on line 63, which in turn is proportional to the frequency of the output signal on line 40 is monitored rate of binary transitions or switching frequency, at to cletectthe amount of phase scatter in the data on the output 40 from phase detector 32.

line 34. In accordance with another aspect of this As an example, in the preferred embodiment of the invention, the equalizer 24 FIGURE 1 is adjusted to 70 invention the frequency of the output signal on line 36 minimize that monitored switching frequency thereby from the VCO 30 has been selected as 66 MHz and the minimizing the phase scatter. output signal frequency on line 40 from the phase In the preferred embodiment of FIGURE 2 an analog detector 32 has been typically 1.3 MHz.

frequency detector circuit 44 is utilized to monitor the In accordance with the preferred embodiment of switching frequency as follows. The frequency detec- 75 FIGURES 1 and 2 the output signal from the integrator tor44 is preferably implemented by a constant area 50, which corresponds to the rate of transitions of the pulse generator48, and an integrator 50. A differential bistable signal on line 40, is monitored bythe voltmeter46 is coupled to an output of the integrator differential voltmeter46. The equalizer 24 of Figure 1 50. The constant area pulse generator 48 comprises May be adjusted via its control lines 25 and 27 to two transistors 52,53 for example type 2N2222 which 80 minimize the monitored signal. As it has been are connected to operate as a current mode switch as previously described, a minimum value of the moni follows. The emitters of transistors 52,53 are con- tored signal correspondsto minimum phase scatter nected to a negative DC voltage source via a resistor and thus minimum bit error rate of the equalized 55. The collectorof one transistor52 is grounded, and playback data stream on line 34.

the collector of the othertransistor 53 is connected to 85 The foregoing operation is illustrated bytheway of oneterminal of an inductor54whose otherterminal is example in FIGURE 6 showing a characteristic 65 of grounded. The base of transistor 52 receives the signal values monitored bythe differential voltmeter previously described outputsignal on line 40from 46 of FIGURE 2 as being dependent on the adjustment flip-flop 32. The base of transistor 53 is connected to a of the equalizer 24 of FIGURE 1. PointA on the DC bias voltage which is midpoint in the logic level 90 characteristic 65 corresponds to minimum voltage range of the flip-flop 32. That mid point is obtained as a displayed on the voltmeter 46 and thus to a minimum junction between two series resistors 95,96 con- phase scatter of the equalized signal on line 34.

nected between the DC bias voltage and ground. The Itfollows from the foregoing description that in the junction 58 between the collector of transistor 53 and preferred embodiment of FIGURES 1 and 2 the bit inductor 54 is connected to an input of a diode 57. 95 error rate is minimized by monitoring the rate of In operation the constant area pulse generator 48 binary transitions atthe output of the phase detector receives the output pulses on line 40 from the flip-flop 32 bythe frequency detector44 and by adjusting the 32. When the voltage on line 40 is negative, the equalizer 24 accordinglyto keep that rate at a transistor 52 is not conducting and the inductor 54 is minimum. As an example, in the preferred embodi charged to a current via transistor 53. When the 100 ment a typical voltage range obtained between a voltage on line 40 is positive, transistor 52 conducts maximum and minimum voltage value B and C of the while transistor 53 is non-conducting. The current characteristic 65 is ten milivolts.

stored in inductor 54 is then discharged through diode An example of a detailed circuit diagram including 57 into the integrator 50. Consequently every time the equalizer 24, limiter 26, bit sync circuit 28 and there is a voltage change online 40 from negative to 105 frequency detector 44, is shown inconsecutive positive, a positive voltage spike is formed atiunction FIGURES 5A and 5B and will be described below. In 58, corresponding to the discharging of inductor 54. the preferred embodiment of FIGURES 5A, 5B the These voltage spikes represent constant area pulses. equalizer24 comprises a voltage controlled cosine The diode 57 rectifies the signal atjunction 58 so that amplitude equalizer 152 and an adjustable phase onlythe positive voltage spikes are applied to the 110 equalizer 171. The voltage controlled amplitude integrator5O. equalizer is the subject matter of the above-referenced The integrator 50 has a series resistor 61 connected concurrently filed copending patent application and it between a parallel resistor 60 and a parallel capacitor is described therein in detail.

62. The otherterminals of the resistor 60 and capacitor The circuit of FIGS. 1A and 1 B operates as follows.

62, are grounded. The junction between resistors 60, 115 An input terminal 31 in FIG U RE 5A, corresponding to 61 is connected to an output of diode 57. The line 31 of FIGURE 1, is coupled to receive an output integrator 50 receives the above-described constant signal from the preamplifier 22 of FIGURE 1, obtained area output pulses via the diode 57 and it provides on as a playback signal from a magnetically recorded line 63 a D.C. output signal whose magnitude is digital signal as previously described. The input signal proportional to an average area of these constant area 120 online 31 is buffered bya conventional buffer pulses per unit of time. Because each pulse has a amplifier 155, comprising transistors 156,157,to constant area, the amplitude of the output signal on obtain a low driving impedance forthe following line 63 is proportional to the number of occurrences of amplitude equalizer 152.

these pulses per unit of time, that is, to thefrequency The voltage controlled cosine equalizer 152 com- of these pulses, as it is well known. To detectthe 125 prises a delay line 126 and a differential amplifier 122 magnitude of the output signal online 63 from implemented by transistors 136,137 whose collectors integrator 50 a conventional differential voltmeter46, are coupled to a positive voltage supply via respective for example type 825A made by Fluke Manufacturing resistors 201 and 138. These collectors represent Company, is preferably utilized. The voltmeter pro- differential outputs 144,244 of the equalizer. The vides a voltage corresponding to the amplitude of the 130 emitters of transistors 136,137 are each connected via 4 GB 2 170 679 A 4 aseries resistor 139,140 to one terminal of a current delay line 126 is implemented by a 15 nanosecond source 142. The otherterminal of the current source delay line, type MD01 5Z1 00 and the transistors 136, 142 is coupled to a negative DC voltage supply. The 137,148,149,150 and 160 are type 2N4259.

base of transistor 136 forms a non-inverting input 124 The voltage controllable range of adjustment of the while the base of transistor 137 forms an inverting 70 equalization circuit of FIGURE 5A is set by proper input 134 of the differential amplifier 22. selection of resistor values 200,132, 151 and 153.

The current source 142 is implemented in a well Decreasing the ratio of resistance values R2/Rl, where known manner by a transistor 160 having its collector R1 is the combined value of resistors 132,200 and R2 is connected to the emitters of transistors 136,137, via the value of resistor 153, or alternatively, decreasing respective resistors 139,140. The emitter of transistor 75 the value R3 of resistor 151 will increase the voltage is connected to a negative D.C. voltage supply via controllable range. However, in most applications itis a series resistor 163. The base of transistor 160 is desirableto limitthat rangeto avoid harmonic connected tothatvoltage supplyvia a voltage divider distoration caused bythe voltage controlled amplifier comprising series resistors 161 and 162 of which 146. Limiting the voltage controllable range also resistor'161 isgrounded. 80 prevents the system from being accidentally adjusted The delay line 126 is connected to the non-inverting toofarfrom its proper setting.

input 124 of the differential amplifier 122. A voltage In operation the boost of the cosine equalizer 152 divider comprising resistor 200 in series with potentio- can be remotely controlled by varying the voltage Vc meter'132and resistor 153 is connected to the input of atthecontrol input25. In addition to the remote the delay line 126. The inverting input'134ofthe 85 control, the boost maybe controlled also manually by differential amplifier 122 is connected to an adjustable the potentiometer 132. For example,the potentio wiper contact of the potentiometer 132. meter 132 may be adjusted to obtain a coarse value of Avoltage controlled amplifier 146 is connected in a desired boost and a fine boost adjustment may be parallel with the signal path provided between the obtained bythe control voltage at 25. The coarse inverting input 134 and output 144,244 of the 90 range of boost adjustment may be selected an order of differential amplifier 122. The voltage controlled a magnitude greaterthan thefine range. It is seen amplifier has two transistors 148,149which havetheir from the foregoing description that the gain of the emitters connected together to a negative D.C.voltage voltage controlled amplifier 146 is dependent on the supplyvia a control transistor 150. The base of current supplied bytransistor 150 which is in turn transistor 149 is connected to thevoltage divider 132, 95 controlled by its base voltage Vc.

153. The base of the transistor 148 is grounded. The The previously mentioned phase equalizer 171 is collectorof transistor 148 is connected to the collector connected to the amplitude equalizer 152via lines 144, of transistor 136. The collector of thetransistor 149 is 244, each connected to the collectorof one transistor connected to the collector of transistor 137. The 136,137 of the voltage controlled amplifier 122, as collectors of transistors 136,148 and 137,149 repre- 100 previously described. The phase equalizer 171 is of a seritthe previously mentioned differential output 144 well known type. The phase versusfrequency charac and 244 of the equalizer 152. The collector of the teristic of the phase equalizer is adjusted by varying control transistor 150 is connected to interconnected the control voltage at input 27, which in turn varies the emitters of transistor 148,149 and its emitter is bias voltage and thusthe capacitance of varactor connected via a current setting resistor 151 to the 105 diodes 204,205.

negative D.C. voltage supply. The resulting amplitude and phase equalized output The base of the control transistor 150 provides a signal on line 182 from the equalizer 24 of FIGURE 5A control input25for receiving a control voltage Vc. By is applied to a buffer amplifier 183, comprised of varying the control voltage Ve applied to control input transistors 184, 185 and 186 connected in series.

25 the amount of currentflowing through the transis- 110 Buffer amplifier 183 provides a stable impedance to tors 148 and 149 of the voltage controlled amplifier drive a low pass filter 188.

146 varies. The gain of amplifier 146 is thus controlled The output signal online 187 from the buffer bythat control voltage. The respective differential amplifier 183 is applied to the low pass filter 188, outputs from the differential amplifier 122 and voltage which is of conventional design and includes a controlled amplifier 146 are summed atthe outputs 115 number of consecutive filter stages for removing 144,244from the voltage controlled amplitude frequencies above the useful signal rangefrom the equalizer 152. The thusly obtained output signal from equalized signal, as it is well known in the art.

the equalizer 152 on lines 144,244 has a variable boost With further referenceto FIGURE 513, thethusly of thefrequency response characteristic in response filtered signal from low pass filter 188 is applied via tothe control voltage at 25.The control voltage on line 120 line 189to the limiter 26 which has a conventional may be applied from a remote location orfor design. The limiter 26 comprises a differential ampli example, automatically by computer control, as it will fier 190 having one input coupled to receive the be described further. The transistors 136,137 and 148, equalized signal on line 189 and another input 149 are selected such thatthe signal delays in the connected to a predetermined reference voltage. The respective signal pathsthrough transistors 136,137 125 resulting amplitude-limited signal on line 34from are substantially equal to the delays provided bythe limiter 26 is applied to the clock input of theJlip-flop 32 parallel path through transistors 148 and 149. A as previously described with reference to FIGURE 2.

resulting propertiming of the respective signals FIGURE 5B also shows the voltage controlled summed atthe outputs 144,244 is thereby obtained. oscillator 30, further referred to as VCO 30, of FIGURE In the preferred embodiment of FIGURE 5Athe 1302 in more detail. The VCO 30 is part of the phase locked GB 2 170 679 A 5 loop28 shown in FIGS 2 and 4. within a selected control voltage rangearestored by FIGURE3 showsan example of a phase scatter circuit70 and applied therefrom via line25to the reduction circuitof the invention in which a control equalizer24. Thevoltage on line25 is received bya circuit70 is utilized to provide an optimum adjustment control input of a voltage controlled amplitude of the equalizer 24 to obtain minimum phase scatter. 70 equalizer, such as has been previously described and The control circuit70 is preferably implemented by a shown at 152 in FIGURE 5A. The corresponding output microprocessor and memory circuit. It has an input signal from the frequency detector44 or 71 foreach which receives via line 74an output signal from the control voltage value on line 25 is detected and the frequency detector44. This frequency detector maybe detected value is applied via line 74 and stored in a implemented byan analog circuit, such as44 of 75 memory ofthe microprocessor and memory circuit FIGURE 2. Alternatively, it maybe implemented bya 70.As shown by block221 of the flowchart, The stored digital circuit, as shown at7l in FIGURE 4and as itwill output signal values are compared with each other be described below. and a minimum stored value is found. If a valid The digital frequency detector 71 of FIGURE 4 minimum stored value is found, corresponding to an receives an outputsignal on line 40 from the 80 inflection pointshown atA in the characteristic curve previously described digital phase detector32 whose 65 of FIGURE 6, as depicted by block 222 of the flow switching frequency is to be detected. The signal on chart, an optimum control voltage value which line 40 is applied to one input of an AND gate 75. The corresponds to the valid minimum stored value isthen other input ofAND gate 75 is coupled to receive a applied via line 25 to adjustthe equalizer 24. If such a control signal on line 76. The control signal is applied 85 valid minimum value is notfound, the above-de to turn on the gate 75 for a predetermined time scribed operation is repeated for a differentset of interval,for example 100 miliseconds. During that control voltage values Vc within a different range, as interval the transitions of the bistable signal on line 40 shown by block 223, until the valid minimum value is pass to the output78 of theAND gate 75. The signal on determined. line 78 is applied to a digital counter72, which 90 Preferablythe

microprocessor is programmed in a provides a count corresponding to the total number of well known mannerto perform the above-described transitions obtained during the predetermined time operation. After determining an optimum valueforthe interval. equalizer adjustment, the microprocessor automati The output signal on parallel output lines 74 from cally sets the equalizer 24via control input 25tothat the counter 72 correspondsto the switching frequency 95 optimum value, as shown by block 224 of FIGURE 7.

of the digital phase detector32. Thus, the signal on In casethe equalizer has more than one adjustable lines 74 corresponds to the amount of phase scatter of control input, such as an additional control input 27 the equalized signal. shown in FIGURE 3, corresponding to the adjustable With further referenceto FIGURE 3, the output input of the phase equalizer 171, the above-described signal from the counter 72 on lines 74 is applied to the 100 operation is repeated foreach additional control input microprocessorand memory circuit 70. The counter as it is indicated by block 225.

72 isthen resetto zero via line 80 shown in FIGURE 4 Itfollows from the foregoing description that in the and it is readyto be turned on foranother predeter- embodiment of FIGURE 3 the microprocessor is mined interval in response to a control signal on line programmed to detect an optimum control signal 76. Theforegoing operation cycle may be continuous 105 value for adjusfing the equalizerto obtain a minimum or maybe repeated intermittently. phase scattervalue. The equalizer is than automatical Alternatively, when the analog frequency detector ly adjusted by the microprocessorto that detected 44is utilized, circuit70 may include a known value.

analog-to-digital converter (not shown) to convertthe Alternatively, the control circuit 70 of FIGURE 3 may analog signal on line 74 into a digital signal in a well 110 be deleted as it is shown in FIGURES 1 or2, and the known manner. output signal of the digital frequency detector 71 may Becausethe characteristic of the outputsignal be monitored on a visual or audible display. The frequency from the phase detector 32 as being equalizer 24 may then be adjusted manually via lines dependent on the equalizer adjustment is not a 25,27 as it has been previously described with respect monotonic function, as it is shown in FIG URE 6, it is 115 to FIGURE 1.

necessaryto provide a number of trial adjustment Reference should be madeto ourcopending ap values, sothatan optimum adjustmentvalue may be plication of even date, entitled "Voltage Controlled determined which corresponds to a minimum phase Equalizer" forfurther details of a preferred form of scatter. The foregoing may be obtained by applying in equalizer24.

Claims (1)

1. sequence a number of discrete adjustment signal 120 CLAIMS values to

   control inputs 25,27 of equalizer 24 in a 1. Apparatus for detecting phase scatter in a digital selected range of adjustment values, so that a desired signal transmitted over a channel, comprising a phase optimum adjustment may be determined. That opti- locked loop comprising a variable frequency signal mum adjustmentvalue corresponds to pointA of the generator arranged to provide a clock signal, a characteristic in FIGURE 6 as it has been described 125 bistable phase detector means coupled to receive, and previously. provide a bistable output corresponding to a phase An example of operation of the circuit of FIGURE 3 is difference between, said clock signal and said digital described belowwith reference to a flow chart shown signal, the frequency of the signal generator being in FIGURE 7. As it is depicted by block 220 of FIGURE 7, controlled by said outputof the phase detector; and a predetermined trial adjustment control voltage values 130 frequency detector means coupled to monitorthe rate 6 GB 2 170 679 A 6 of switching transitions of said bistable output. equalization circuitfurther has a control input coupled 2. Apparatus for detecting phase scatter in a digital to receive a control signal for adjusting said amplitude signal transmitted over a channel, having a nonor phase response thereof to obtain a minimum rate of constant amplitude response andlor non-linear phase said transitions of said bistable signal monitored by response, comprising: 70 said frequency detector means.

   an equalization circuit having an input coupled to 8. Apparatus according to claim 7 wherein said receive said transmitted signal and an output, said equalization circuit comprises a voltage controlled equalization circuit being coupled to provide an amplifier means having a control input corresponding equalized signal and having a response which corn- to said control input of said equalization circuit and pensates for said channel response; 75 wherein said control signal is applied to adjust again a phase locked loop coupled to provide a reference of said voltage controlled amplifier means, thereby signal synchronous with said equalized signal, said adjusting said amplitude response provided by said phase locked loop comprising a reference clock signal equalization circuit.

   generatormeans having an outputcoupled to provide 9. Apparatus according to claim 8furthercompris a reference clock signal, and a phrase detector means 80 ing a control means having an input coupled to receive having a first input coupled to receive said reference an output signal of said frequency detector means and clock signal and a second input coupled to receive said having an output coupled to said control input of said equalized signal, said phase detector means having an equalization circuit, said control means being coupled output providing a bistable output signal correspond- to apply respective control signal valuesto said ing to a phase difference between said input signals 85 control input of said equalization circuit and to detect thereof, said output of the phase detector means an optimum control signal value corresponding to a being coupled to a control input of said signal minimum signal value obtained from said frequency generator meansto control the frequency of said detectormeans.

   reference clock signal provided thereby; and 10. Apparatus according to claim 9 wherein said frequency detector means coupled to said output of 90control means is further coupled to apply said said phase detector means for monitoring a rate of detected optimum control signal valueto said control transitions of said bistable outputsignal. input of said equalization circuit.

   3. Apparatus according to claim 2 wherein said 11. A method of detecting phase scatter in a digital equalization circuit has a control input coupled to signal transmitted over a channel having a non- receive a control signal for adjusting said amplitude or 95 constant amplitude response andlor non-linear phase phase response thereof, said apparatus further corn- response, comprising the steps of:

   prising a control means having an input coupled to equalizing said transmitted signal to compensate receive an output signal of said frequency detector forthe response of said channel; means and having an output coupled to said control generating a reference clock signal synchronized input of said equalization circuit and wherein said 100 with said equalized signal, while detecting a phase control means is coupled to detect an optimum difference between said reference clocksignal and control signal value corresponding to a minimum said equalized signal and providing a bistable control inputsignal value obtained from saidfrequency signal corresponding to a polarity of said phase detector means and to apply said optimum valueto difference, and applying said bistable control signal as said control input of the equalization circuit. 105 a D.C. signal to control the frequency of said reference 4. Apparatus according to claim 3 wherein said clock signal; and control means is a programmable microprocessor monitoring the rate of transitions of said bistable and memory means. signal, thereby monitoring the amountof phase 5. Apparatus according to any of claims 1 to 4 scatter.

   wherein said frequency detector means comprises a 110 12. A method of reducing phase scatter in a digital constant area pulse generator means having an input signal transmitted over a channel having a non coupled to said output of the phase detector means for constant amplitude response andlor non-linear phase providing constant area pulses corresponding to said response, comprising the steps of:

   signal transitions obtained from said phase detector equalizing said transmitted signal to provide an means, an integrator means having an input coupled 115 equalization response compensating forthe response to receive said constant area pulses, said integrator of said channel; means coupledto provide an outputsignal prop- generating a reference clocksignal synchronized ortional to afrequencyof said constantarea pulses. with said equalized signal,while detecting a phase 6. Apparatus according to any of claims 1 to 4 difference between said reference clock signal and wherein said frequency detector means comprises a 120 said equalized signal and providing a bistable control gate means and counter means, said gate means signal corresponding to a polarity of said phase having a first input coupled to receive said bistable difference, and applying said bistable control signal as output signal of said phase detector means and a a D.C. signal to control the frequency of said reference second inputcoupled to receive a control signal, said clocksignal; gate means having an output coupled to an input of 125 monitoring the rate of transitions of said bistable said counter means, and wherein said gate means is signal, thereby monitoring the amount of phase coupledto appiy said bistable output signal to said scatter; and counter means in responseto a control signal applied applying a variable control signal to vary said to said control input. equalization response to minimize said monitored 7. Apparatus according to claim 2 wherein said 130rate of transitions of said bistable signal.

   7 GB 2 170 679 A 7 13. A method of reducing phase scatter in a digital signal transmitted over a channel having a nonconstant amplitude response and/or non-linear phase response, comprising the steps of:

   equalizing said transmitted signal to provide an equalization response compensating forthe response of said channel; generating a reference clock signal synchronized with said equalized signal, while detecting a phase difference between said reference clock signal and said equalized signal and providing a bistable control signal corresponding to a polarity of said phase difference, and applying said bistable control signal as a D.C. signal to control the frequency of said reference clocksignal; monitoring the rate of transitions of said bistable signal, thereby monitoring the amount of phase scatter; applying variable control signal values to vary said equalization response and monitoring, said transition rates obtained in response to said control signal values; and selectingan optimum control signal valuewhich correspondsto a minimum monitored transition rate and applying said optimum control signal valueto adjust said equalization response.

   14. A method according to claim 13 wherein the step of applying control signal values includes storing in a memory means said control signal values and said transition rates obtained in response to said values andwherein said step of selecting an optimum control signal value comprises comparing said stored transition rates and,selecting said optimum control signal value as corresponding to a minimum stored transition rate.

   Printed in the United Kingdom for Her Majesty's Stationery Office, 8818935, 8/86 18996. Published at the Patent Office, 25 Southampton Buildings, London WC2A 1AY, from which copies may be obtained.