GB2169479A - Display processor - Google Patents

Abstract

A display processor comprises several interconnected units, such as units (1) and (2) for comparing the assigned and current X and Y coordinates, a Y coordinate searching unit (6), an address multiplexer (7) coupled with a pattern line incrementing unit (21) connected in series with a pattern line display sequencing unit (13 and a pattern display sequencing unit (19), a random-access memory (15), a multichannel switch (17), and a video adder (5). The multichannel switch (17) is connected to the unit (2), to the pattern line display sequencing unit (13), to the pattern display sequencing unit (19), and to the pattern line incrementing unit (21) and the video adder (5), the two latter being connected to each other. The data input is to the switch (17), the address input to multiplexer (7) and the video output is taken from adder (5). Control inputs enter at (42), (46), (50). <IMAGE>

Description

SPECIFICATION Display processor This invention relates to computertechnology and is particularly concerned with display processors This invention can be used to display static and dynamic information including alphanumeric, graphic and pattern information.

Described is a display processor which comprises a unitfor comparing the assigned and current X coordinates, and a unit for comparing the assigned and current\/ coordinates, some inputs thereof being respective control inputs ofthe processor and which are electrically connected to a random-access mem ory connected in series with a multichannel switch whose one input is an information input ofthe processor, and a video adder whose one input is a control input of the processor whose one input is a control input of the processor and whose output is the output of the processor, and which additionally comprises, according to the invention, a unit for searching the Y coordinate, whose one input is connected to the unitforcomparing the assigned and currentY coordinates, while the other input is one of the control inputs of the processor, a pattern line sequencing unit whose one input is connected to the outputofthe multichannel switch and otherthree inputs are respective control inputs ofthe processor, an address multiplexer whose one input is an address input of the processor, next two inputs are connected to the unit for searching the Y coordinate, two other inputs are connected to the pattern line sequencing unit, one more input is connected both to the Y coordinate searching unit and to the pattern line sequencing unit, while the output is connected to the random-access memory, a pattern line incrementing unitwhose input is connected to the output of the multichannel switch, one output is connected to one more input of the pattern line display sequencing unit, another output is connected to the input ofthe multichannel switch, and the last output is connected to the video adder and to inputs ofthe multichannel switch and the address multiplexer, and a unitfor sequencing the display of patterns whose one input is a control input ofthe processor, two other inputs are connected, respectively, to the multichannel switch and to the pattern line display sequencing unit, while the output is connected to the last input ofthe address multiplexer, the multichannel switch being coupled to inputs of such units as the unitfor comparing the assigned and current X coordinates, the unit for comparing the assigned and current Y coordinates and tothevideo adder, while the outputofthe unitfor comparing the assigned and currentXcoordinates being connected to one more input ofthe video adder.

This invention provides a capability for displaying a larger volume ofany static or dynamic information in any point of the screen with a lesser storage capacity, which makes the processor simpler.

Besides, this invention provides a capability of programming specific patterns and concurrentprogramming of the pattern vertical size, which expands the field of application ofthe processor.

Moreover, this invention provides a capability of changing the horizontal and vertical size of a pattern, which also expands the field of application of the processor.

In addition, this invention provides a capability of changing the color ofthe screen background, which also contributes to widening of the processor field of application.

The invention will now be described with reference to a specific embodiment thereof, taken in conjunction with the accompanying drawings, wherein: Fig. 1 illustrates a general block diagram of a display processor, according to the invention; Fig. 2 illustrates a block diagram of a unit for sequencing the display of patterns, according to the invention; Fig. 3 illustrates a block diagram of a pattern line incrementing unit, according the invention; Fig. 4 illustrates a block diagram of a unit for sequencing the pattern line display, according tothe invention; Fig. 5 illustrates a block diagram of a video adder, according to the invention; Fig. 6 shows a screen with a pattern.

A display processor comprises a unit 1 (Fig. 1 ) for comparing the assigned and current X coordinates and a unit 2 for comparing the assigned and currentY coordinates, the outputs of these units being connected to inputs 3 and 4 of, respectively, a video adder Sand a unit 6for searching theY coordinate (referred to as the counter 6 hereinafter). The output of the counter 6 is connected to an addressmultiplexer7 by means of its inputs 8,9 and 10. Inputs 10,11 and 12 of said address multiplexer7 are connected to a unit 13 for sequencing the display of pattern lines. An input 14 of the multiplexer 7 is an address input 1 4 of the processor. The output ofthe address multiplexer7 is connected to a random-access memory 15 via the input 16 thereof.The random-access memory 15 is connected to a multichannel switch 17 whose input 18 is the information input 18 of the processor. The outputofthe multichannel switch 17 is connected to an input 20 of a unit 19 for sequencing the display of patterns and to an input 22 of a pattern line in crementing unit 21, as well asto inputs 23,24,25 and 26 of respective units 1,2,13 and video adder 5. Inputs 27 and 28 ofthe multichannel switch 17 are connected, respectively, to outputs 29 and 30 ofthe unit 21. An output 29 of the unit 21 is connected to inputs 31 and 32 of, respectively, multiplexer 7 and video adder 5. An input 33 and the output ofthe unit 13 are connected, respectively, to an output 34 of the unit 21 and an input 35 ofthe unit 19. One more output 36 ofthe unit 19 is connected to one more input 37 ofthe multiplexer 7.

Inputs 38, 39, 40 and 41 of respective units 1,2,13 and 19 are joined together and constitute a control input 42 of the processor. Inputs 43, 44 and 45 of, respectively, unit 1,video adder 5 and unit 13 are also joined together and constitute a control input 46 of the processor. Inputs 47, 48 and 49 of respective units 2,6 and 13 are also joined together and constitute a control input 50 ofthe processor. An output 51 of the video adder 5 is the output 51 of the processor.

The random-access memory 15 comprises several data files: a Y coordinate information data file 52, an X coordinate information data file 53, a pattern arrange ment data file 54, a picture frame data file 55, a pattern address data file 56, and a pattern data file 57. Each data file 52,53,54,55,56 and 57 is composed of a number of locations (not shown).

The pattern display sequencing unit 19 comprises a pattern search register 58 (Fig. 2) and a pattern display control multiplexer 59 which are connected to each other.

The pattern line incrementing unit21 (Fig. 1) comprises a pattern current information register 60 (Fig. 3) and an incrementor61 which are connected to each other.

The pattern line display sequencing unit 13 (Fig. 1) comprises a pattern search register 62 (Fig.4) whose output is connected to an input640f OR or circuit 63 for dig it-by-digit addition of information. The output ofthe OR circuit 63 is connected to an input66 of an AND circuit 65 for digit-by-digit multiplication of information, whose another input 67 is coupled to a decoder 68 which features one more input 69 which is the input 33 ofthe unit 13 (Fig. 1). The output ofthe AND circuit 65 (Fig. 4) is connected to a main register 70 for parallel code reception and transmission of information, whose output is connected to one more input 71 ofthe OR circuit 63 and to an input 73 of a multiplexer 72.Another input 74 and an output 75 of the multiplexer72 are connected to an output77 and input 78, respectively, of a counter 76.The output 77 of the counter 76 is connected to an input 80 of an additional register79for parallel code reception and transmission of information. The output ofthe register 79 is connectedto an input 81 ofthe decoder 68. Inputs 82 and 83 of respective registers 62 and 70 are joined together and constitutethe input 49 ofthe unit 13 (Fig.

1). Inputs 84 and 85 (Fig. 4) ofthe counter76 are, respectively, inputs 40 and 45 ofthe unit 13 (Fig. 1).

The video adder 5 comprises a shift register 86 (fig.

5), a screen background color register 87, and a pattern color register 88, the outputs of said registers being connected to inputs 90,91 and 92, respectively, ofthe multiplexer 89.

An input 93 ofthe register86 is connected to a pattern line code register 94. Inputs 95 and 96 of respective registers 94 and 87 are joined together and constitute the input 26 (Fig. 1) ofthe video adder 5.

Referring to Fig. 6, an example of a pattern 97 is shown on a television screen 98 where it has assigned coordinates: X0 = 2, Y0 = 3. The screen 98 is divided into a 256 by 256 point array, while the pattern 97 has 16 points horizontally and from 1 to 16 vertically. In this example, the pattern 97 has six lines displayed. Of the 16 possible colors the pattern 97 is white and the screen 98 black.

The central processor (not shown) uses the address input 14and information input 1 8to enter, via the address multiplexer7 and multichannel switch 17, respectively, to the random-access memory 15 the following information: -to the first location ofthe Y coordinate data file 52: the binarycode (YO =3) which determinesthe vertical position ofthe pattern 97-- 0000 00112; -tothefirst :ocation ofthe data file 53 containing informationoftheXcoordinates: the binary code (XO = 2) which determines the horizontal position of the pattern 97--0000 00102; Data files 52 and 53 are ascending ordered binary code files of Y and X pattern modes, respectively.The node of a pattern hereinafter is the upper leEt-hand corner ofthe matrix ofthe pattern 97.

-to the first location ofthe pattern arrangement data file 54: code 000116; -to a location of a respective address in the picture frame data file 55-code 000000000100 10102; The data files 54 and 55 store information on the arrangement of patterns within a given frame. To match the array ofthe pattern 97(16 by 16 points) and the screen 98 (256 by 256 points), the data file 54 contains 16 locations, whereas the data file 55 contains 256 locations.Each match ofthe assigned coordinates Yj and Xi nodes of patterns on the screen 98 corresponds one bit in the data file 54 and one location in the data file 55, in otherwordsthey correspond to each Yi and Xi pair. If some crosspoint ofthe Y and X coordinates is the beginning of a pattern, that is the pattern node matched the Yj-Xj pair, a "1 " should be entered to the respective bitofthe data file 54 as the pattern availability flag indicating the presence of a pattern in a given coordinate crosspoint.A respective location ofthe data file 55 should receive pattern information: the code ofthe pattern number, which is the address ofthe pattern beginning in the data file 57, the code ofthe pattern beginning in the data file 57, the code ofthe pattern colorandsize,which iscontainedinthehigherorder 12 bits (code 0000 0000 01002), and the code of the initial line number, which is contained in the lower orderfour bits (code 10102), The abscence of a pattern in a given crosspoint of Y and X coordinates is indicated by a "zero" in the respective bit ofthe data file 54. To summarize, the data file 54 stores information on the availability of patterns on given Y coordinates.

-to all locations of the pattern address data file 56: zero information.

The colorand size of a pattern is stored in the data file 56, as well as a complete address for accessing the file 57. This complete address is a pattern number and the number of the pattern current line. The information entered by the processorto respective locations ofthe data file 56 in the course of pattern formation are required fortheirdisplay on the screen 98.

-to a specific plurality of locations in the pattern data file 57: codes representing the structure ofthe pattern 97 within the 16 by 16 point matrix.

Atthe beginning oftheforwardtelevision scan, an address (code 00002) determined by the state ofthe counter 6 is supplied to the input8 ofthe address multiplexer 7. A reference to the data file 52 ofthe random-acess memory 15 is produced. The counter6 is reset atthe beginning ofthetelevision scan, since it is reset by the flyback ofthe television sweep. The information obtained from the zero location ofthe data file 52 (code 0000 00112), which determines the television line from which the display ofthe pattern 97 should be started on the screen 98, is delivered via the multichannel switch 17 to the input 24 ofthe unit 2for comparing the assigned and currentY coordinates.

Further operation ofthe processor depends on the availability or absence of patterns in a given television line. The absence of patterns, like in ourexample, where the pattern 97 is to be displayed on the screen 98 from the third line (code 000000112) and no patterns are present in the zero, first and second television lines, is determined by the pattern line display sequencing unit 13 during the retrace of television lines. The unit 13 holds the processor sequence until the television line on which the pattern 97 isto be displayed.

On the third television line (code 0000 00112) from the beginning ofthe retrace, the unit 2 for comparing the assigned and current Y coordinates comes into action and a reference to the data file 54 is formed with the code also determined by the state ofthe counter 6.

The information (code 000116) read from the zero location ofthe data file 54 is fed to the unit 13 and unit 19to be stored therein. The unit 13 determines, from the code received, whether or not the pattern 97 is present on a given television line and generates a binary code ofthe lower order "one" number in the received code. In this case, the number code of the lower order "one" is 00002 because the pattern presence flag is contained in the zero bit of the information on the pattern position on theY0 = 3 coordinate.

Further sequence of operations performed by the processortoform each line of each pattern can be divided into four steps. The processor realizes this four-step sequence during the sweep retrace or on a signal fed from the unit 1 forcomparing the assigned and current X coordinates providing no disable signal is coupled from the unit 13.

During the first step, the data file 53 ofthe random-access memory 15 is accessed via the input 11 ofthe multiplexer 7 to the address determined by the code (00002) supplied from the unit 13. Code 0000 00102 representing the XO = 2 coordinate from which the pattern 97 is to be displayed on the screen 98 is applied to the input 23 ofthe unit 1 from the random-access memory 15 via the multichannel switch 17.

During the second step, either data file 55 or data file 56 is addressed depending on whose line is to be displayed, ofthe old pattern or the new one. In this example. where displayed is a line of a new pattern whose display is just starting, the data file 55 is accessed via the input 10 ofthe multiplexer 7 to the address determined by the atate ofthe counter 6 and the code coupled from the unit 13. When a next line of the pattern 97 is to be displayed on a given television line, the data file 56 is accessed via the input 12 of the multiplexer7 to the address determined by the code coupled from the unit 13. This is achieved by the pattern display sequencing unit 19 which determines whetherthe lines of a new or the old pattern areto be displayed.If the initial line of a new pattern isto be displayed, a logical "zero" is produced by the output 36 of the unit 19. If, on the contrary, a next line ofthe old pattern is to be displayed, a logical "one" is producedbythe unit 19. The output 36 ofthe unit 19 is coupledtotheinput37ofthemultiplexer7andsaid multiplexer7 is switched overto a respective input, which is input 10 forthe new pattern or input 12 for the old pattern. In this manner a respective file is addressed, the data file 55forthe new pattern and data file 56forthe old pattern. The information on the pattern 97 read off during this operation contains codesforthe color number, size and line number and is supplied to the input 22 ofthe pattern line incrementing unit 21.

During the third step, the data file 57 of the random-access memory is accessed via the input 31 of the multiplexer7 to the address fed from the output 29 ofthe unit 21. The reference address (code 000 01000 10102) is composed of two portions: -four lower order bits are determined by the code of the number of the pattern line to be displayed. In this example, these bits represent the code (10102) of the initial number of the pattern line, which is stored in respective locations of the data file 54 wherefrom the information has been read off in the previous step; - other bits (000 01002) determined by the number code of the pattern to be displayed, which has also been read off in the previous step from a respective location of the picture frame data file 54.

The initial (tenth) line ofthe pattern 97 is supplied at the end ofthe third step to the input 26 ofthevideo adder 5.

During the fourth step, binary codes for color, size and number of the pattern 97, which are supplied from the output 29 of the unit 21 via the input 27 of the mu Itichannel switch 17, are coupled to respective bits in a location ofthefile 56, whose address is determined by the code furnished from the unit 13. In addition, code 10112 corresponding tothe incremented number of the pattern line is supplied from the output 30 ofthe unit 21 via the input 28 of the multichannel switch 17 and placed into the four lower order bits of the same location. In the fourth step, information on color and size of the pattern 97 is furnished from the output 29 of the unit 21 to the input31 of the video adder5.

Concurrently with the processor performing its four-step sequence of operations, the unit 13 con tinues to function. Having found that no more patter availability flags can be detected in the code 000116 and, consequently, no other patterns are going to be displayed on this television line, unit 13 forbids the processor to perform other four-step sequences.

During the forward motion of the television sweep on a given line, the unit 1 produces, when a current X coordinate coincides with the assigned X coordinate, X0 = 2 (code 0000 00102), an output signal supplied to the input3 ofthevideo adder5, thus enabling the display of the initial line of the pattern 97 on the screen 98 in synchronism with the frequency ofthe synch pulses supplied to the input 44 of the video adder 5.

As the retrace of the next, fourth, television line is started, the output of the unit 2 is reset and the counter 6 is flipped over to the next state (000012). The datafile 52 is again addressed for the next Y coordinate as has been described above, this being true only when more than one pattern is displayed.

During the first step of the nextfour-stepsequence the processor operates as described above.

During the second step, when the display of the pattern 97 is continued on a given television line, that is the next line of the now old pattern is to be displayed, a logical "0" is produced at the output 36 of the unit 19 to changethe muitiplexer7 overto the input 12. In consequence, the data file 56 is accessed to the address determined by the code furnished from the unit 13 (code 00002). The information read therefrom (code 0000 0000 010010112),which contains the full address ofthe pattern 97 for access to the data file57, including the number code of the pattern 97, the color code and the size code of this pattern 97, is applied to the input 22 ofthe unit 21.

During the fourth step,the processor operates as described above, exceptthat code 11002 representing the incremented code of the line number ofthe pattern 97, which has been read off during the second step, is supplied from the output 30 ofthe unit 21 to the input 28 ofthe multichannel switch 17. The next line of the pattern 97 is displayed exactly as the initial line line of this pattern 97.

The display ofthe lastfour lines of this pattern 97 is performed by the processor as described above.

Termination ofthe display ofthe pattern 97 on the acreen 98 is done as follows.

The pattern availability flag stored in the unit 13 is deleted during thefourth step, asthe last line ofthe pattern 97 is being prepared for display, by a signal furnished from the output 34 ofthe unit 21 to the input 33 ofthe unit 13. As a result, the processorfurther operates like on the zero orfirst or second television lines where no patterns are available.

The pattern display sequencing unit 19 (Figs. 1,2 and 6) operates as follows.

As previously discussed, the information on the arrangement of patterns on a given Y0 = 3 coordinate (code 000116), which has been read to access the data file 54, is supplied to the input 20 of the pattern search register 58 ofthe unit 19. The pattern display control multiplexer 59 has its input connected to the output of the register 58. Depending on the code applied to the input ofthe multiplexer 59, that is the input 35 ofthe unit 19, said multiplexer 59 transmits the code stored in the respective digit ofthe register 58 to the output 36 ofthe unit 19. In this example, the code applied to the input 35 ofthe unit 19 is 00002 and taken from the unit 13. The output ofthe multiplexer59 receives a " 1 " stored in the zero bit ofthe register 58.In this manner a logical "1" is produced atthe output 36 ofthe unit 19, which indicatesthatthe pattern 97 has started to be displayed. The information in the register 58 is retained unaltered until the beginning ofthe next television line, when the register 58 is reset. The register 58 is reset bythe line scanning signal coupled to the input 41 ofthe unit 19. As a result, the logical "0" code is supplied to the output ofthe multiplexer 59 on the subsequenttelevision lines, since it is stored now in the zero bit ofthe register 58 and in all other bits as well. This predetermines the logical "O" as the output 36 ofthe unit 1 9,which confirms the lines ofthe old pattern are still being displayed, the "old" pattern being the one whose lines continue to be displayed.

The pattern line incrementing unit 21 (Figs. 1,3 and 6) operates as follows.

The pattern current information register 60 receives information, containing codes ofthe pattern number, size, color and line number, which is read offduring the second step and applied to the input 22 ofthe unit 21. The register 60 stores this information and feeds it to the output 29 ofthe unit 21. In addition, the code of the line number ofthe pattern 97 is supplied to the input of the incrementor 61 which adds "1 " thereto or increments the code. The incremented code is deli vered to the output 30 ofthe unit21.

As the last line (code 11112) of the pattern 97 is being prepared for display, a carry over signal is produced at the output 34 ofthe incrementor 61, since 11112 + 12 00002.

The pattern line display sequencing unit 13 (Figs. 1, 4 and 6) operates as follows.

The vertical retrace signal furnished from the input 49 ofthe unit 1 3to the inputs 82 and 83 resets the registers 62 and 70. Thus, atthe beginning ofthe forward scan, the registers 62 and 70 store zero information until a reference is made to the zero location ofthe data file 54, that is until the third television line. During the retrace of each television line providing a count enable signal forthe input 84 of the counter 76, taken from the control input 42 ofthe processor, the counter 76 starts counting clock pulses furnished to the input 85 from the processor control input 46. In this case the output code ofthe counter 76 is taken from the output 77 thereof to be appliedto the input 74 ofthe multiplexer72.Information stored in the register70 (which is zero until now) istransferred in parallel codetothe input 73 ofthe multiplexer72.

The output 75 ofthe multiplexer72 receives information stored in one ofthe bits ofthe register 70. The code furnished by the counter76 determines the number ofthe bit coupled, at this instant, to the output 75 ofthe multiplexer 72. The counter76 performs bit-by-bit scanning ofthe bits in the register 70, from lowerto higher orders, and transmits their contents to the output ofthe multiplexer 72.

In case a "1 " is detected in one ofthe bits ofthe register 70, it is furnished, when an enable code is available atthe output 77 ofthe counter76,from the output 75 ofthe multiplexer 72 to the input78 of the counter 76. A "1" atthe input78 terminates operation of the counter 76 which retains,atthe output77, a code equal to the number ofthe bit ofthe register70, which stores this "1". Since the "1 of stored in this bit is the first detected from the beginning of the counting by the counter 76, it is, consequently, the least significant bit fall. In this manner, the smultiplexer 72andthecounter76 perform searching ofthe next least significant "1" stored in the register 70 and formation of its binary code number. But, until now, the register 70 stored zero information.ln this case the counter 76 counts until overflowed and the counting is terminated until the end ofthe nexttelevision line. the overflow signal ofthe counter 76 forbids the display processorto perform the four-step sequences, which means that no patterns 97 can be displayed on the screen 98. On the third television line, as discussed above, code 0001,6 which signifies that a pattern is to be displayed on this television line is furnished to the input 25 ofthe unit 13 from the zero location of the file 54. The information (code 000116) is coupled to the register 62 and then, via the OR ci rcuit 63 for digit-by-digit addition of information and the AND circuit 65 for digit-by-digit multiplication of information, is applied to the register 70.

The OR circuit 63 performs digit-by-digit addition of codes delivered to the inputs 64 and 71 thereoffrom the registers 62 and 70, respectively. This is done to add the pattern availability flags (the "ones" stored in theregister62)forthosepatternswhich are be displayed on a given television line to the availability flags of patterns whose displayed is not yet over (the "ones" stored in the register 70).

The AND circuit 65 performs digit-by-digit multiplication of the code suppled from the output of the OR circuit 63 to the input 66 and the code supplied from the output ofthe decoder 68 to the input 67. This is done to delete the availability flags of patterns whose display is terminated on a given television line.

In this example, information supplied tothe input 71 from the register 70 is zero information (000016), while information supplied to the input 67 from the decoder 68 is unit information (FFFF16), since the pattern 97 is only starting to be displayed on a given line. The code 000116 is furnished to the register 70 without changes and the register 62 is reset. Afterthe information has been received by the register 70, the search for the least significant bit starts and is immediatelyterminated because the least significant "1" is in the zero bit.

The counter 76, consequently, retains its zero state. At the beginning ofthefirststep ofthefour-step sequence, the code ofthe state ofthe counter 76 is furnished to the input 80 ofthe register 79 and stored therein. From the register 79, the code is supplied to the output ofthe unit 13 to be used in further processor operations.

The start ofthe first step, in addition, causes the counter 76 go on with the counting, but, since no more "ones" are available in the register70, the counter 76 counts to overflow and, consequently, forbids execution of otherfour-step sequences.

The unit 13 operates similarly on subsequent five television lines.

To prepare the display of the last line ofthe pattern 97, a carry-over signal is furnished in the fourth step of the sequence from the incrementor 61 (Fig. 3) ofthe unit 21 to the input 69 of the decoder 68. As a result, a "logical zero" signal is produced by one of the locations of the decoder 68, whose number is determined by the code supplied to the input 81 ofthe decoder 68from the outputofthe register 79. In this example,the "zero" code is produced in the lower order location in accordance with the code 00002 stored in the register 79.The information stored in the register 70 is then rewritten so that the code fed from thedecoder68(FFFF6) deletestheavailabilityflag of the pattern 97 in the code 000118 supplied from the register 70 during the digit-by-digit multiplication in the AND circuit 65. As a result, the zero code 000016 is written into the register 70 and the display ofthe pattern 97 on the screen 98 is terminated.

During rewriting the OR circuit 63 has no effect on the code 000116 at the input71 since the register 62 has been reset and contains zero information.

The video adder 5 (Figs. 1,5 and 6) forms, atthe output 51 ofthe processor, a sequence of codes for color information in orderto control the R, G and B channels ofthe television set as follows.

Information (a line of the displayed pattern 97) supplied to the video adder 5 during the third step is fed to the input 95 of the register 94 and stored therein until a march occurs of the current X coordinate with the assigned X coordinate (XO = 2). When this match occurs, the information from the register 94 is fed in parallel codetotheinput93oftheshiftregister86 which shifts the information thus received in synchronism with the frequency ofthe sync pulses supplied to the input 44 of the video adderS. The serial code of a line of the pattern 97 is produced atthe output ofthe register 86 and furnished to the input 90 of the multiplexer 89.

Information (color code and size of the pattern 97) is supplied to the pattern color register 88 from the input 32 during the fourth step. The screen background color register 87 receives information concurrently with the unit 2. Information is further supplied from the registers 87 and 88to respective inputs 91 and 92 ofthe multiplexer 89 and, depending on the code of the signal applied to the input 90 thereof, is fed to the output 51.In summary, the multiplexer 89 transmits, if the input 90 is "0", information from the register 87 to the output 51 and in this manner provides appropriate matrix points with the color determined by the screen background color code. lithe input 90 is " 1 ", the output 51 receives information from the register 88 and provides appropriate matrix points ofthe pattern 97 with the color determined by the code of the pattern color.

According to the invention, if the size of the pattern 97 isto be changed and "1" is present in the bits of the scale code, the processor operates as described above, exceptthat: During thefourth step the data file 56 is addressed only on even television lines so that the vertical size of the pattern 97 on the screen 98 is doubled; - information shift in the register86 (Fig. 5) of the video adder 5 is performed with the half-frequency of the synchpulses and the horizontal size ofthe pattern 97 (Fig. 6) on the screen 98 is doubled.

This invention can be used to make the processor smaller.

Another advantage of this invention consists in that the picture memory capacity can be reduced while the functional capabilities ofthe processor are expanded.

Claims (2)

1. A display processor comprising a unitfor comparing the assigned and current X coordinates and a unit for comparing the assigned and current Y coordinates, some inputs of said units being control inputs of the display processor, each said unit being connected to an output of a multichannel switch whose one input is an information input ofthe display processor; a Y coordinate searching unit whose one input is a respective control input of the display processor, while another input thereof is connected to the unitforcomparing the assigned and currentY coordinates; a pattern line display sequencing unit whose one input is connected to a multichannel switch, while other inputs are respective control inputs ofthe display processor; an address multiplexerwhose one in put is an address input of the display processor, next two inputs are connected to the Y coordinate searching unit, two other inputs are connected to the pattern line display sequencing unit, one more input is connected both to the Y coordinate searching unit and to the pattern line display sequencing unit; a random-access memory connected to the multichannel switch and address multiplexer; a video adder whose one input is a respective controt input of the display processor, another input is connected to the multichannel switch, one more input is connected to the unitfor comparing the assigned and current X coordinates, while the output is the output of the display processor; a pattern display sequencing unit whose one input is a control input of the display processor, another input is connected to the pattern line display sequencing unit, one more input is connected to the multichannel switch,whilethe output is connected to one or more input ofthe address multiplexer; a pattern line incrementing unit whose input and one output are connected with the multichannel switch, anotheroutput is connected to one more input ofthe pattern line display sequencing unit, while the last output is connected to other inputs ofthe address multiplexer, multichannel switch and video adder.

2. A display processor substantially as setforth in any one ofthe preceding claims and as described herein above with reference to the accompanying drawings.