GB2167228A - Integrated circuit package - Google Patents
Integrated circuit package Download PDFInfo
- Publication number
- GB2167228A GB2167228A GB08425708A GB8425708A GB2167228A GB 2167228 A GB2167228 A GB 2167228A GB 08425708 A GB08425708 A GB 08425708A GB 8425708 A GB8425708 A GB 8425708A GB 2167228 A GB2167228 A GB 2167228A
- Authority
- GB
- United Kingdom
- Prior art keywords
- integrated circuit
- package
- resilient
- ports
- connectors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Packaging Frangible Articles (AREA)
Abstract
In an integrated circuit package, particularly suitable for a whole wafer integrated circuit, including separable upper and lower portions and an internal resilient gasket for holding an integrated resiliently in position within the package, resilient conductors consisting of alternate conductive and insulating layers are pressed on to the electrical ports of the integrated circuit and output connectors of the package to provide electrical connections from outside the package to the integrated circuit. The conductors may be of silicone rubber or silver stripes on a polymer tape. <IMAGE>
Description
SPECIFICATION
Integrated circuit package
The present invention relates to the packaging of an integrated circuit, particularly a whole wafer integrated circuit.
The packaging of an integrated circuit is an important part of integrated circuit manufacture since the package should not damage the integrated circuit or impair its operation, and a defective package will lead to rejection of the final product or its failure in service.
Integrated circuit packages available at present are satisfactory in that the reject rate of packaged integrated circuits due to package or packaging problems falls within acceptable limits. Nevertheless, a proportion of integrated circuits which are rejected at the final stages of manufacture are damaged by the packaging process or are rejected because of defective packages, and this situation may become unacceptable with future developments of integrated circuits notably the introduction of whole wafer integrated circuits because of their high cost.
The present invention provides advantages over known packaging arrangements in the area of avoiding undesirable influences of an integrated circuit package on its integrated circuit in particular, avoiding, or at least reducing shear forces experienced by an integrated circuit because its temperature coefficient of expansion differs from that of its package.
The present invention is particularly suitable for the packaging of whole wafer integrated circuits but may be applied to smaller-thanwafer integrated circuits, for example, integrated circuits chips.
In accordance with a first aspect of the present invention, a method of packaging an integrated circuit includes housing the integrated circuit in a sealed package, providing means holding the integrated circuit resiliently in position, and providing non-rigid electrical connections between the integrated circuit ports and electrical connectors of the package.
Holding the integrated circuit resiliently in position and providing non-rigid electrical connections, as set out above, permits expansion and contraction of the integrated circuit independently of the package.
In accordance with the first aspect of the present invention, a method of packaging an integrated circuit includes supporting a face of the integrated circuit by means of a plane surface, holding the integrated circuit resiliently against the plane surface and in directions orthogonal to the plane surface, sealing the integrated circuit within the package and connecting the ports of the integrated circuit nonrigidly to output connectors.
Non-rigid connection may include pressing resilient electrically conductive members into contact with the ports of the integrated circuit and the output connectors.
Sealing the integrated circuit within the package may include pressing a resilient sealing member around the periphery of the active surface of the integrated circuit by means of a cover member of the package. The holding of the integrated circuit resiliently against the plane surface and the sealing of the integrated circuit within the package may be done by the same component.
In acccordance with a second aspect of the present invention, a method of packaging an integrated circuit includes securing the integrated circuit releasably between upper and lower portions of a package sealable by closure members and a resilient sealing member between the portions, and connecting the ports of the integrated circuit releasably to electrical connectors of the package.
Securing the integrated circuit releasably and connecting the ports of the integrated circuit releasably, as set out above, permits replacement of either a package or an integrated circuit, by release of the closure members, which may be screws, and the separation of the portions of the package.
Connecting the integrated circuit releasably may include pressing resilient electrical connectors on to the integrated circuit ports. Alternatively, connection may be by means of conductive stripes, each with a conductive adhesive coating, spaced regularly on a polymer backing to form a connection tape. The conductive stripes may be silver stripes.
In accordance with the second aspect of the present invention, a method of packaging an integrated circuit includes securing the integrated circuit releasably against a plane surface of one of upper and lower portions of a package sealable by closure members and an internal resilient sealing member, and securing resilient electrical connectors between the ports of the integrated circuit and electrical connectors of the package by pressing the resilient electrical connectors between the portions of the package and against the ports of the integrated circuits.
Securing the integrated circuit releasably may include pressing the integrated circuit between the portions of the package and the resilient sealing member. The ports of the integrated circuit may lie adjacent to either the upper or the lower portion of the package, and either portion of the package may have electrical connectors.
In accordance with the first aspect of the invention referred to above, a package for an integrated circuit includes means for securing the integrated circuit resiliently within the package, means for sealing the package, and electrical connection means for effecting nonrigid electrical contact between the ports of the integrated circuit and the electrical connectors of the package.
The means for securing the integrated circuit may include a plane surface for supporting a surface of the integrated circuit, formations upstanding from the plane surface for contacting edges of the integrated circuit, and resilient means for pressing the integrated circuit against the plane surface and the formations.
The electrical connection means may include resilient electrical connectors for establishing electrical contact, under pressure, between the integrated circuit and the electrical connectors of the package.
The package may include upper and lower portions and a resilient member, which, when pressed between the upper and lower portions, may secure an integrated circuit resiliently and seal the package.
In accordance with the first aspect of the invention, referred to above, a package for an integrated circuit includes rigid and resilient support means for supporting an integrated circuit resiliently within the package, means for sealing the package, and resilient electrical connection means for effecting electrical contact between the ports of the integrated circuit and the electrical connectors of the package.
In accordance with the second aspect of the present invention, referred to above, a package for an integrated circuit includes separable upper and lower portions, means for securing the integrated circuit releasably within the package, means for sealing the package when the portions are secured together, means for securing the portions together releasably, and releasable connection means for connecting the ports of the integrated circuit electrically to the connectors of the package.
The releasable connection means may be resilient electrical connectors arranged to be pressed into contact with the ports of the integrated circuit when the upper and lower portions of the package are secured together.
A resilient gasket may perform part of the function of securing the integrated circuit releasably by being arranged to be pressed with the integrated circuit between the portions of the package, and the resilient gasket may also perform the function of sealing the package.
A plane surface on the lower portion of the package and formations upstanding from the plane surface, with associated resilient members, may assist in the function of securing the integrated circuit releasably within the package.
A method of packaging an integrated circuit may include securing the integrated circuit resiliently between releasable upper and lower portions of a package, and connecting the ports of the integrated circuit resiliently and releasably to electrical connectors of the package, and, a package for an integrated circuit may include separable upper and lower portions with means for securing the portions together releasably, resilient securing means for securing the integrated circuit within the package, and resilient and releasable electrical connection means for connecting the ports of the integrated circuit to electrical connectors of the package.
An integrated circuit package in accordance with either aspect of the present invention may include a chamber for accommodating additional interconnected electrical components, and electrical connectors extending between the region of the package for securing an integrated circuit and the chamber.
An integrated circuit package, in accordance with both aspects of the present invention, will now be described by way of example only and with reference to the accompanying drawings, in which:
Fig. 1 represents a sectional elevation, taken along the line A-A of Fig. 2, of an integrated circuit package in which a whole wafer integrated circuit is secured releasably and resiliently, including a chamber with additional components, and,
Fig. 2 is a part plan view representation of the package of Fig. 1 with its upper portion removed to show the whole wafer integrated circuit, a gasket, resilient electrical connectors, a spring member, and rigid support members belonging to the lower portion of the package of Fig. 2.
Referring to Fig. 1, a package for a semiconductor wafer includes a lower portion 1 and an upper portion 2 attachable together by means of screws 3 and 4. The lower and upper portions 1 and 2 together form an enclosure in which a wafer 5 is housed. The lower surface of the wafer 5 lies on the lower portion 1 and is held against the lower portion 1 by a gasket 6 which is pressed by the upper portion 2 on to the upper surface of the wafer 5. Electrical contact elements 7 and 8 are also pressed by the upper portion 2 on to the upper surface of the wafer 5 at edge regions of the wafer 5 and extend beyond the wafer 5 on to the inner surface of the lower portion 1 against which they are also pressed by the upper portion 2. The package includes a space 9 above the wafer 5.
Referring now to Fig. 2, the periphery of the generally circular wafer 5 includes a straight portion 20 which lies against a ledge 21 included in the lower portion 1 of the package.
A part of the circular periphery lies against a pin 22, the wafer 5 being held against the ledge 21 and the pin 22 by means of a spring member 23. The pin 22 is so positioned on the lower portion 1 of the package that the wafer 5 is squeezed between the pin 22 and the ledge 21 by the action of the member 23.
The gasket 6 has a circular inner periphery and an outer periphery which is generally that of a regular octagon but which has a cut-out portion at the position of the spring member 23 so that the gasket 6 does not overlie the spring member 23. The gasket 6 includes further cut-out regions which accommodate the electrical contact elements 7 and 8.
The wafer is positioned face up (active circuits and metallisation uppermost) on the lower portion 1 of the package. The metallised areas providing communication and supply ports to the wafer are held in contact with conductive tracks provided at the underside of the electrical contact elements 7 and 8, and the conductive tracks at the underside of the electrical contact elements 7 and 8 are held in contact with metal tracks provided on the upper surface of the lower portion 1 of the package. The metal tracks of the lower portion 1 of the package extend to a connector, moulded socket, pins, or the like, located outside the package.
The material of the lower portion 1 of the package may be a conventional printed circuit board material or may be a mouldable plastics material, for example, the material sold by ICI under the Trade Mark "Victrex".
The material of the gasket 6 is a silicone rubber and the electrical contact elements 7 and 8 include a plurality of alternating layers of conductive and non-conductive silicone rubber. The layered elastomeric connectors include redundant contacts, that is, several conductive elastomeric layers contact each device pad in any position, eliminating the need for precise positioning of the connector while ensuring- effective contact. The gasket 6 may be preformed or constructed in situ in the package. The gasket 6 and the contact elements or connectors 7 and 8, both being of silicone rubber material, may be provided as a single item. Connection tape consisting of conductive silver stripes, each with a conductive adhesive coating, spaced regularly on a polymer backing may be used to connect the integrated circuit electrically to the package contacts.
The upper portion 2 of the package is arranged to apply pressure to the gasket 6 causing controlled dimensional deformation of the gasket 6 which provides a gas tight seal around the wafer 5.
An alternative electrical contact arrangement is the provision of metal tracks on the upper portion 2 of the package, and suitably modified electrical contact elements which make electrical contact with the metal tracks on the upper portion 2, for establishing electrical contact from outside the package to the wafer 5.
A zinc-loaded paste may be introduced between the lower surface of the wafer 5 and the inner surface of the lower portion 1 of the package in order to improve the thermal contact between the wafer and the package. In addition, the lower portion 1 of the package may include ribs or the like for better heat transfer characteristics.
The zinc paste, referred to above, provides the added benefit of holding the wafer in place during the assembly process. Alternatively, an electrically conductive paste may be used to permit electrical contact with the wafer bulk, zinc paste being nonconductive.
The spring member 23 is so designed and positioned as to allow the wafer 5 to move freely over the inner surface of the lower portion 1 of the package as the wafer 5 and the package expand and contract by different amounts.
The space 9 above the wafer 5 may hold an inert gas at reduced pressure, or may be evacuated, in order to provide an increased force holding the upper and lower portions of the package together. The reduced-pressure space may be provided by assembling the package in a reduced-pressure environment.
The package may include an auxiliary enclosure, shown as 10 in Fig. 1, into which the metal tracks extend to make contact with additional components housed in the auxiliary enclosure. The lower surface of the auxiliary enclosure 10 may include printed circuit conductors to which the additional components are attached by solder.
It will be evident that the package described above imposes little or no mechanical stress on the wafer during deformation of the package or temperature cycling and permits reworking in the event of faulty components being included during manufacture of a product or components failing during the life of a product.
Although the package, described above, is particularly suitable for mounting an integrated circuit occupying a wafer, it may be applied to integrated circuit chips, without the loss of any of the advantages mentioned above, by suitable modification, including, for example, the use of two pins in a line generally orthogonal to a ledge for meeting two adjacent edges of a rectangular chip, and a spring member arranged for exerting a force on the corner of the chip opposite that between the adjacent edges referred to.
Claims (25)
1. A method of packaging an integrated circuit, including housing the integrated circuit in a sealed package, providing means holding the integrated circuit resiliently in position, and providing non-rigid electrical connections between the integrated circuit ports and electrical connectors of the package.
2. A method of packaging an integrated circuit, including, supporting a face of the integrated circuit by means of a plane surface, holding the integrated circuit resiliently against the plane surface and in directions orthogonal to the plane surface, sealing the integrated circuit within the package, and connecting the ports of the integrated circuit nonrigidly to output connectors.
3. A method of packaging an integrated circuit, as claimed in claim 1 or claim 2, including the pressing of resilient electrically conductive members into contact with the ports of the integrated circuit and the output connec tors.
4. A method of packaging an integrated circuit, as claimed in claim 2, including the attachment of adhesive tape connectors to the integrated circuit ports and the output connectors with the ports of the integrated circuit and the output connectors.
5. A method of packaging an integrated circuit, as claimed in claim 2, or claim 3 as dependent on claim 2, or claim 4 as dependent on claim 2, including the pressing of a resilient sealing member around the periphery of the active surface of the integrated circuit by means of a cover member of the package to hold the integrated resiliently against the plane surface.
6. A method of packaging an integrated circuit, including the securing of the integrated circuit releasably between upper and lower portions of a package sealable by closure members and a resilient sealing member between the portions, and the connecting of the ports of the integrated circuit releasably to electrical connectors of the package.
7. A method of packaging an integrated circuit, as claimed in claim 5, including the pressing of resilient electrical connectors on to the integrated circuit ports and the output connectors.
8. A method of packaging an integrated circiit, as claimed in claim 6, including the attachment of adhesive tape connectors to the integrated circuit ports and the output connectors.
9. A method of packaging an integrated circuit, including the securing of the integrated circuit releasably against a plane surface of one of upper and lower portions of a package sealable by closure members and an internal resilient sealing member, and securing resilient electrical connectors between the ports of the integrated circuit and electrical connectors of the package by pressing the resilient electrical connectors between the portions of the package and on to the ports of the integrated circuit.
10. A method of packaging an integrated circuit, as claimed in claim 9, including the pressing of the integrated circuit between the portions of the package and the resilient sealing member.
11. A package for an integrated circuit, including means for securing the integrated circuit resiliently within the package, means for sealing the package, and electrical connection means for effecting non-rigid electrical contact between the ports of the integrated circuit and the electrical connectors of the package.
12. A package for an integrated circuit, as claimed in claim 11, including a plane surface for supporting a surface of the integrated circuit, formations upstanding from the plane surface for contacting edges of the integrated circuit, and resilient means for pressing the integrated circuit against the plane surface and the formations.
13. A package for an integrated circuit, as claimed in claim 12, including resilient electrical connectors for establishing electrical contact, under pressure, between the integrated circuit and the electrical connectors of the package.
14. A package for an integrated circuit, as claimed in claim 11, including adhesive tape connectors for establishing electrical contact between the integrated circuit and the electrical connectors of the package.
15. A package for an integrated circuit, as claimed in any one of claims 11 to 14, including upper and lower portions and a resilient member, which, when pressed between the upper and lower portions, secures an integrated circuit resiliently and seals the package.
16. A package for an integrated circuit, including rigid and resilient support means for supporting an integrated circuit resiliently within the package, means for sealing the package, and resilient electrical connection means for effecting electrical contact between the ports of the integrated circuit and the electrical connectors of the package.
17. A package for an integrated circuit, including separable upper and lower portions, means for securing the integrated circuit releasably within the package, means for sealing the package when the portions are secured together, means for securing the portions together releasably, and releasable connection means for connecting the ports of the integrated circuit electrically to the connectors of the package.
18. A package for an integrated circuit, as claimed in claim 17, including resilient electrical connectors arranged to be pressed into contact with the ports of the integrated circuit when the upper and lower portions of the package are secured together.
19. A package for an integrated circuit as claimed in claim 17, including adhesive tape connectors for connecting the integrated circuit to the connectors of the package.
20. A package for an integrated circuit, as claimed in any one of claims 11 to 19, including a resilient gasket arranged to be pressed with the integrated circuit between the portions of the package to secure the integrated circuit releasably.
21. A package for an integrated circuit, as claimed in claim 20, wherein the resilient gasket is arranged to seal the package.
22. A package for an integrated circuit, as claimed in any one of claims 11 to 21, including a plane surface on the lower portion of the package and formations upstanding from the plane surface, with associates resilient members, assisting in the function of securing the integrated circuit releasably within the package.
23. A method of packaging an integrated circuit including the securing of the integrated circuit resiliently between releasable upper and lower portions of a package, and the connecting the ports of the integrated circuit resiliently and releasably to electrical connectors of the
package.
24. A package for an integrated circuit, including separable upper and lower portions with means for securing the portions together releasably, resilient securing means for securing the integrated circuit within the package, and resilient and releasable electrical connec
tion means for connecting the ports of the
integrated circuit to electrical connectors of
the package.
25. An integrated circuit package as claimed
in any one of claims 11 to 22, or 24, includ
ing a chamber for accommodating additional interconnected electrical components, and electrical connectors extending between the region of the package for securing an integrated circuit and the chamber.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08425708A GB2167228B (en) | 1984-10-11 | 1984-10-11 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08425708A GB2167228B (en) | 1984-10-11 | 1984-10-11 | Integrated circuit package |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8425708D0 GB8425708D0 (en) | 1984-11-14 |
| GB2167228A true GB2167228A (en) | 1986-05-21 |
| GB2167228B GB2167228B (en) | 1988-05-05 |
Family
ID=10568032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08425708A Expired GB2167228B (en) | 1984-10-11 | 1984-10-11 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2167228B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0508179A2 (en) * | 1991-04-08 | 1992-10-14 | EXPORT-CONTOR Aussenhandelsgesellschaft mbH | Circuit device |
| DE19529237C1 (en) * | 1995-08-09 | 1996-08-29 | Semikron Elektronik Gmbh | High power semiconductor circuit device |
| WO2003034467A2 (en) * | 2001-10-10 | 2003-04-24 | Europäische Gesellschaft Für Leistungshalbleiter Mbh | Semiconductor power module |
| WO2002060810A3 (en) * | 2001-01-30 | 2003-09-04 | Univ Sheffield | Micro-element substrate interconnection |
| EP2073265A1 (en) * | 2007-12-21 | 2009-06-24 | SEMIKRON Elektronik GmbH & Co. KG | Pressure contact in an assembly comprising a power semiconductor module |
| US8033838B2 (en) | 1996-02-21 | 2011-10-11 | Formfactor, Inc. | Microelectronic contact structure |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917707A (en) | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
| US5820014A (en) | 1993-11-16 | 1998-10-13 | Form Factor, Inc. | Solder preforms |
| US20020053734A1 (en) | 1993-11-16 | 2002-05-09 | Formfactor, Inc. | Probe card assembly and kit, and methods of making same |
| US5994152A (en) | 1996-02-21 | 1999-11-30 | Formfactor, Inc. | Fabricating interconnects and tips using sacrificial substrates |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB822711A (en) * | 1954-12-21 | 1959-10-28 | Gen Electric | Improvements relating to sealed rectifier units employing semi-conductors |
| GB882450A (en) * | 1958-03-21 | 1961-11-15 | Otto Eberle | Improvements in or relating to methods of making electric connections |
| GB884340A (en) * | 1958-09-10 | 1961-12-13 | Gen Electric | Improvements in semiconductor mounting |
| GB1270288A (en) * | 1968-06-25 | 1972-04-12 | Texas Instruments Inc | Header system for a semiconductor device |
| GB1325393A (en) * | 1970-11-20 | 1973-08-01 | Siemens Ag | Semiconductor arrangements |
| GB2000336A (en) * | 1977-06-20 | 1979-01-04 | Hitachi Ltd | Electronic device and method of fabricating the same |
| GB1553559A (en) * | 1977-05-02 | 1979-09-26 | Philips Nv | Hybrid circuits |
| EP0072673A2 (en) * | 1981-08-13 | 1983-02-23 | Minnesota Mining And Manufacturing Company | Area tape for the electrical interconnection between electronic components and external circuitry |
| EP0091376A1 (en) * | 1982-04-05 | 1983-10-12 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Lead format for tape automated bonding |
-
1984
- 1984-10-11 GB GB08425708A patent/GB2167228B/en not_active Expired
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB822711A (en) * | 1954-12-21 | 1959-10-28 | Gen Electric | Improvements relating to sealed rectifier units employing semi-conductors |
| GB882450A (en) * | 1958-03-21 | 1961-11-15 | Otto Eberle | Improvements in or relating to methods of making electric connections |
| GB884340A (en) * | 1958-09-10 | 1961-12-13 | Gen Electric | Improvements in semiconductor mounting |
| GB1270288A (en) * | 1968-06-25 | 1972-04-12 | Texas Instruments Inc | Header system for a semiconductor device |
| GB1325393A (en) * | 1970-11-20 | 1973-08-01 | Siemens Ag | Semiconductor arrangements |
| GB1553559A (en) * | 1977-05-02 | 1979-09-26 | Philips Nv | Hybrid circuits |
| GB2000336A (en) * | 1977-06-20 | 1979-01-04 | Hitachi Ltd | Electronic device and method of fabricating the same |
| EP0072673A2 (en) * | 1981-08-13 | 1983-02-23 | Minnesota Mining And Manufacturing Company | Area tape for the electrical interconnection between electronic components and external circuitry |
| EP0091376A1 (en) * | 1982-04-05 | 1983-10-12 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Lead format for tape automated bonding |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0508179A2 (en) * | 1991-04-08 | 1992-10-14 | EXPORT-CONTOR Aussenhandelsgesellschaft mbH | Circuit device |
| DE4111247A1 (en) * | 1991-04-08 | 1992-10-22 | Export Contor Aussenhandel | CIRCUIT ARRANGEMENT |
| EP0508179A3 (en) * | 1991-04-08 | 1992-12-30 | Export-Contor Aussenhandelsgesellschaft Mbh | Circuit device |
| DE19529237C1 (en) * | 1995-08-09 | 1996-08-29 | Semikron Elektronik Gmbh | High power semiconductor circuit device |
| US8033838B2 (en) | 1996-02-21 | 2011-10-11 | Formfactor, Inc. | Microelectronic contact structure |
| WO2002060810A3 (en) * | 2001-01-30 | 2003-09-04 | Univ Sheffield | Micro-element substrate interconnection |
| WO2003034467A2 (en) * | 2001-10-10 | 2003-04-24 | Europäische Gesellschaft Für Leistungshalbleiter Mbh | Semiconductor power module |
| WO2003034467A3 (en) * | 2001-10-10 | 2004-01-29 | Europaeische Ges Fuer Leistung | Semiconductor power module |
| US7034395B2 (en) | 2001-10-10 | 2006-04-25 | Eupec Europaische Gesellschaft Fur Leistungshalbleiter Gmbh | Power semiconductor module with cooling element and pressing apparatus |
| EP2073265A1 (en) * | 2007-12-21 | 2009-06-24 | SEMIKRON Elektronik GmbH & Co. KG | Pressure contact in an assembly comprising a power semiconductor module |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2167228B (en) | 1988-05-05 |
| GB8425708D0 (en) | 1984-11-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19921011 |