GB2163559A - Testing electrical components - Google Patents

Abstract

An apparatus for testing electrical components by contacting them with a plurality of conducting probes and ascertaining the electrical condition between each or a selected number or pairs of such probes, information relating to the spatial disposition of the probes relative to a component being tested is generated by performing a mapping procedure wherein the probes are brought into contact with onre or more calibration surfaces, the or each surface being dividing into a multiplicity of conducting areas connected to test circuitry of the apparatus. When two calibration surfaces are used they have their respective multiplicities of conducting areas arranged to overlap to produce a larger multiplicity of discrete areas, each probe being so associated with one of said discrete areas. A pair of calibration surfaces can each be constituted by a single surface of a mapping board (25) divided into parallel strips (27) separated by insulating strips (28), and disposed in two positions angular spaced about 90 DEG . Board (25) can have location means (30a, 30b) for engagement with location pins on the apparatus. <IMAGE>

Description

SPECIFICATION Testing electrical components This invention reiates to the testing of printed circuit boards. They may be boards as manufactured, ie consisting of an arrangement of conducting paths on an insulating base, in which case the testing ascertains that all desired conducting paths on each board are intact and that no undesirable bridging conducting paths exist. This involves ascertaining whether or not short circuits or open circuits exist between a number of pairs of positions on the board. In the testing of a wired board, similar testing operations will be effected, with possible additional operations such as measuring component values and/or functional characteristics between pairs of positions on the boards.All of these operations are carried out on conventional testing apparatus wherein a board to be tested and a test head mounting a plurality of conducting probes, are brought together to cause the probes to make electrical contact with desired parts of the board circuitry. The probes are each connected to one of a plurality of leads into electronic test circuitry which effects the testing and displays and/or records the results. Each test head is specific to a particular board and as many test heads need to be provided as there are boards to be tested.

If the installation is to assist in fault location, the various test probes must be spatially located for identification. This can be done by recording the wiring from the testing apparatus to each probe position, or by subsequently testing each probe position electrically, for example by applying a voltage to each probe in turn. These processes are known as "mapping" and generate information which is fed into the apparatus to enable detected faults to be spatially located.

For small numbers of probes, the time and cost of mapping is small, but with larger numbers the cost and time increases sharply. Such time and cost may be incured when a different test head is placed in the apparatus, even if such test head has been used previously.

It is an object of the present invention, therefore, to provide an improved method of and apparatus for testing electrical circuits by improving fault location.

The invention provides a method of testing an electrical circuit in an apparatus comprising; a test head mounting a plurality of probes capable of making electrical connection with a plurality of locations on the component; a plurality of leads connecting the probes to circuitry capable of ascertaining the electrical relationship between selected combinations of probes; means for locating a component to be tested, and means for bringing the component and the probes into engagement, wherein information spatially locating the probe is generated by causing the probes additionally to come into contact with at least one calibration surface the or each of which has a plurality of discrete electrically conducting areas, each individually connected to test circuitry', to cause a number of the probes to make electrical contact with each area.

Conventionally a single mapping board embodies a plurality of parallel conducting areas separated by narrow insulating areas. Greater accuracy is possible if the single mapping board is used twice in two different angular positions.

The mapping board can be rectangular and the said positions can lie at right angles to each other.

Less conveniently, two mapping boards can be used, each providing one calibration surface. The shapes of the conducting areas can be chosen as desired. Although an array of parallel strips is desired any other arrangement could be chosen, such as an array of radially arranged triangular areas. When an array of parallel strips is used the angular separation between the two calibration surfaces need not be 90" but can be any other convenient angle.

A typical mapping board is approximately 300 mm square and has centrally arranged thereon ten parallel conducting areas each 25 mm wide and about 270 mm long, separated by insulating areas some 2 mm wide. The conducting areas can be produced by electrodeposition and etching as in conventional techniques used for printed circuit boards.

Each strip has a lead connected to the test circuitry which usually incorporates a computer.

Use of such a mapping board in two positions at 90" to each other generates the necessary information spatially to identify the location of each probe within an area 25 mm square. This is sufficiently accurate to enable any subsequently detected fault to be traced to one or a small number of probes quite easily.

When the mapping board is used, it may well happen that one or more of the probes encounter the insulating areas, and thus are not mapped. To eliminate this limitation the mapping board can be moved a small distance transversely to the longer axes of the strips, typically by the width of the spacing between the conducting areas. This generates additional information identifying and mapping any probes which previously engaged the gaps between strips. This checking step can be taken in relation to each calibration surface and these two steps taken together generate a second body of probe location information. If a probe does not touch a conducting strip and thus is not identified by the first body of information generated during the first calibration steps, it can be checked against the second body of information and its location specified.

Usually, each board to be tested is located on the apparatus by having apertures which closely engage pins upstanding from the apparatus. The or each mapping board can have similar apertures for engagement with the location pins. Additional apertures can be provided to enable the sideways displacement to take place during the second step. Such apertures are displaced in a direction transversely of the longer axes of the strips by a distance equal to the aforesaid small distance. As this distance is usually small compared with the sizes of the holes, the additional apertures may also be longitudinally offset relative to the strip axes. Such displacement does not affect the mapping.

The invention also provides, for use in carrying out the method aforesaid a mapping board comprising a plurality of discrete conducting areas separated by insulating areas whose total area is small compared to the total of the conducting areas, means for locating the board on testing apparatus, and leads for connecting the areas to test circuitry.

The conducting areas can be in the form of an array of parallel strips of constant width.

The conducting areas can be separated by narrow insulating strips.

The invention also provides electrical circuit testing apparatus comprising: a test head mounting a plurality of probes capable of making electrical connection with a plurality of locations on the component; a plurality of leads connecting the probes to circuitry capable of ascertaining the electrical relationship between selected combinations of the probes; means for locating a component to be tested; and means for bringing the component and the probes into engagement, and mapping board means capable of providing at least one calibration surfaces, the or each calibration surface having a plurality of discrete electrically conducting areas, each individually connectable to said circuitry.

When two calibration surfaces are used they can be constituted by a single surface of a single mapping board used in two different positions.

The two dispositions can be angularly different, for example by 90".

The two calibration surfaces can be the opposite surfaces of a single mapping board.

Alternatively, each calibration surface can be a surface of an individual mapping board.

Each calibration surface preferably has a plurality of parallel strips of constant width separated by narrow insulating strips.

The or each mapping board can be located on the test equipment by location apertures arranged to engage location pins. Additional location apertures can be provided for use of a single board in two dispositions.

The invention will be described further, by way of example, with reference to the accompanying drawings which illustrate a preferred embodiment thereof, it being understood that the following description is illustrative and not limitative of the scope of the invention. In the drawings: Figure 1 is a fragmentary cross-sectional view through an established form of test fixture, when in use testing a printed circuit board, but before the circuit board and probes have been brought into contact; Figure 2 is a similar view after the board and probes have been brought into engagement; and Figure 3 is a perspective view of a mapping board of the invention for use in the method and apparatus of the invention.

Referring firstly to Figs. 1 and 2 of the drawings, test apparatus of the invention is, so far as is illustrated in these figures, generally conventional. The apparatus has a test head 10 comprising a platen 11 and a shield 12. The platen is drilled to receive a plurality of upstanding probe assemblies 13. Each probe assembly has a body 14 secured in the platen 11 and an upstanding head 15 on a limb 26. Limb 26 is biassed upwardly by a spring in body 14. The lower end of the body has attached thereto a lead 16. The leads 16 from all the probe assemblies 13 (of which there may be a considerable number) are bundled to form an umbilical cable 17 which terminates in a plug 18 or like connector whereby the probes can be connected to testing circuitry (not shown) of the apparatus.

Such circuitry may include or consist of a computer. The heads 15 of the probe assembly pass through apertures in shield 12 of the apparatus which is vertically slidably on pins 20. Shield 12 has upstanding location pins 21 which engage locating apertures 22 in an electrical component such as a printed circuit board 23 to be tested. Means for bringing the probe heads 15 and the board 23 into engagement is constituted by a vacuum system including flexible rubber seals 24. This system is conventional and will not be described further. When the heads 15 and boards 23 are in engagement (Fig. 2) the electrical conductors between each or selected combinations of the probe heads 15 can be ascertained by the computer. This process is also known and will not be described in further detail. It will be appreciated that each circuit board to be tested will have a particular arrangement of conductors and a test head specific to each board must be provided having probes disposed to contact desired points on the boards to be tested.

When a production run of a particular board has been tested, the test head is changed to deal with a new board. This involves the process of "mapping" that is the generation of information spatially identifying the positions of the various probes.

If one or more hundreds of probes and leads are involved this process is tedius and expensive.

By use of the present invention mapping can be considerably simplified. In the following description mapping will be described in relation to the testing of bare boards as manufactured, that is boards to which no components have yet been attached and wherein testing needs only to establish that all the design conducting paths are present and that no unwanted path interconnections, ie short circuits, exist. A test head must be manufactured having probes positioned to contact sufficient points on the board to be tested to enable the integrity of all the conductors and the lack of undesirable conducting paths to be ascertained. With a computer constituting the test circuitry it is possible to eliminate the need for expensive design stages and simply manufacture the test head to have sufficient probes appropriately positioned to contact each extremity of each conductor.The desired electrical condition between each pair of probes can then be introduced into the computer by placing on the apparatus a board which is known to be correctly manufactured and causing the computer to scan each pair of probes in turn and so build up a list whereon each pair of probes has a desired electrical condition (in the present example short circuit or open circuit) assigned to it. During testing of the recently manufactured boards each board is placed on the apparatus in turn and the computer repeats the list generation for each board and compares it with the list generated during testing of the known-to-be correct board. If there is no discrepancy the board being tested is satisfactory and can be passed on for use. If a discrepancy occurs, there is a fault in the board being tested and that board will need to be discarded or repaired.If the board is discarded mapping is unnecessary.

However, it is usually desirable to ascertain the nature of the fault more precisely, for example, for repair or to amass information for achieving better quality in the manufacturing process. Accordingly, it is necessary to know the spatial dispositions of the pairs of probes between which a discrepancy occurs.

To this end a mapping board 25 (Fig. 3) is provided which comprises a base of insulating material having had formed on one surface thereof a plurality of conducting areas 27 each in the form of a parallel sided strip about 25 mm wide and 270 mm long. The areas 27 are separated by gaps 28 about 2mm wide.

Each area 27 has attached thereto either directly (as shown) or by means of an independant probe contact an electrical lead 29 and the leads 29 are gathered together and form a cable which can be connected to the test circuitry. The board 25 has four location apertures 30a and four additional location apertures 30b. This particular arrangement assumes that there are four pins 21 at the corners of a square. If this is not the case a different arrangement of location apertures 30 will have to be provided.

The mapping board 25 is placed on the apertures in the same way as a board 23 using apertures 30a, and by applying a signal from the test circuitry to each lead 29 in turn, those probes contacting each of areas 27 can be determined and each can have allotted thereto an identifying number associated with each strip. These can be numbers 1 to 10.

The mapping board 25 is then turned through 90" and the process repeated, this time the probes contacting each strip being designated by, for example, letters A to J. This mapping process effectively divides a board some 250 mm square into one hundred areas each 25 by 25 mm and each containing one or a number of probes. Any probe or probes in a particular area will be designated by a code from Al to J10. When a board being tested shows an anomaly between two probes, comparison with the body of information generated by this mapping will enable the locations of the two probes to be ascertained and the full nature of the fault investigated.

It will be appreciated that some probes may contact the insulating areas 28 and not appear on one or other or both of the lists. Their positions are uncertain, ie one one row of 1 to 10 or in one column of A to J, or not at all. To eliminate this error, mapping is repeated using location holes 30b. The holes 30b are offset from holes 30a by the spacing of strips 28, ie by about 2 mm. The holes 30b are also usually offset longitudinally of the strips 28 as the distance of 2 mm will usually be less than the hole size. Such longitudinal offsetting does not affect the mapping. This second procedure thus generates a second body of information which certainly includes any probes which engaged the insulating strips in the first mapping procedure, although some probes mapped in the first procedure may be omitted or only partially mapped.If any probe is found to be part of a fault during testing its location can be ascertained by reference to one or other of the two bodies of information.

The invention is not limited to the precise details of the foregoing. For example two calibration surfaces have, as described, been constituted by one surface of one board in two dispositions. They can also be constituted by two sides of a single board or each by one side of one of a pair of boards. If an elongate board is to be tested either of these two possibilities might be preferable to a square mapping board. A single calibration surface having an array of discrete conducting areas can be used.

The arrangement of the conducting areas on the or each calibrating surface can be varied as desired. For example a radial array of triangular areas could be used, or an array of curved areas. Both of these possibilities may lead to some of the designated areas being larger than others and this would normally be undesirable. However, there may be circumstances where such arrangements would be preferred. If two calibration surfaces are separated by angular displacement of one or two boards, the angle need not be 90 , provided the two patterns, when superimposed, define discrete areas of practicable size and disposition.

In the testing of completed boards having components attached, the computer or testing circuitry may be adapted to test more than mere short circuit/open circuit conditions. For example, in testing a rectifier component on a board an alternating voltage might be applied to a pair of probes and a second pair of probes tested for the presence of a constant voltage. However, the mapping principles of the present invention are not affected.

Many other variations are possible within the scope of the following claims.

Claims (28)

1. A method of testing an electrical circuit in an apparatus comprising; a test head mounting a plurality of probes capable of making electrical connection with a plurality of locations on the component; a plurality of leads connecting the probes to circuitry capable of ascertaining the electrical relationship between selected combinations of probes; means for locating a component to be tested, and means for bringing the component and the probes into engagement, wherein information spatially locating the probe is generated by causing the probes additionally to come into contact with at least one calibration surface the or each of which has a plurality of discrete electrically conducting areas, each individually connected to test circuitry, to cause a number of the probes to make electrical contact with each area.

2. A method as claimed in claim 1, wherein two calibration surfaces are used sequentially, the dispositions of the discrete conducting areas on the two calibration surfaces being different so that information is generated spatially locating each probe.

3. A method as claimed in claim 2, wherein a single mapping board is provided which has a plurality of parallel conducting areas separated by narrow insulating areas, two calibration surfaces being constituted by the single mapping board used in two different angular positions.

4. A method as claimed in claim 2 or 3 wherein the mapping board is rectangular and the said positions lie at right angles to each other.

5. A method as claimed in claim 2, 3 or 4 wherein two mapping boards are used one providing each calibration surface.

6. A method as claimed in any preceding claim, wherein the or each calibration surface includes an array of radially arranged triangular areas.

7. A method as claimed in claim 2 or 3 wherein an array of parallel strips is used, the angular separation between the two calibration surfaces being any convenient angle other than a right angle.

8. A method as claimed in any of claims 2 to 7 wherein each strip has a lead connected to it directly or by means of a probe and the leads are connected to the test circuitry.

9. A method as claimed in any preceding claim wherein the test circuitry is or includes a computer.

10. A method as claimed in any preceding claim including the additional step of repeating the mapping procedure using the or both two calibration surfaces in positions offset relative to the originally used position or positions.

11. A method as claimed in claim 10, wherein the or each mapping board has apertures for engagement with board location pins of the apparatus.

12. A method of testing an electrical component substantially as hereinbefore described with reference to the accompanying drawings.

13. For use in performing the method of any preceding claim, a mapping board comprising a plurality of discrete conducting areas separated by insulating areas, means for locating the board on testing apparatus, and leads for connecting the conducting areas to testing circuitry.

14. A board as claimed in claim 13 whrein the total area of the insulating areas is small compared to the total of the conducting areas.

15. A board as claimed in claim 13 or 14 wherein the conducting areas are in the form of an array of parallel strips of constant width.

16. A board as claimed in claim 15 wherein the conducting areas are separated by parallel narrow insulating strips.

17. A board as claimed in any of claims 13 to 16 wherein the location means is a plurality of apertures for engagement with location pins of test apparatus.

18. A mapping board substantially as hereinbefore described with reference to and as illustrated in Fig. 3 of the accompanying drawings.

19. Electrical circuit testing apparatus comprising: a test head mounting a plurality of probes capable of making electrical connection with a plurality of locations on the component; a plurality of leads connecting the probes to circuitry capable of ascertaining the electrical relationship between selected combinations of the probes; means for locating a component to be tested; and means for bringing the component and the probes into engagement, and mapping baord means capable of providing at least one calibration surfaces, the or each calibration surface having a plurality of discrete electrically conducting areas, each individually connectable to said circuitry.

20. Apparatus as claimed in claim 1, wherein two calibration surfaces are provided and used sequentially, the dispositions of the discrete conducting areas on the two calibration surfaces being different.

21. Apparatus as claimed in claim 20 wherein the two surfaces are constituted by a single surface of a single mapping board used in two different dispositions.

22. Apparatus as claimed in claim 21 wherein the two dispositions are angularly different, for example by 90".

23. Apparatus as claimed in claim 20 or 21 wherein the two calibration surfaces are the opposite surfaces of a single mapping board.

24. Apparatus as claimed in claim 20 or 21 wherein each calibration surface is a surface of an individual mapping board.

25. Apparatus as claimed in any of claims 19 to 24 wherein the or each calibration surface has a plurality of parallel strips of constant width separated by narrow insulating strips.

26. Apparatus as claimed in any of claims 19 to 25 wherein the or each mapping board can be located on the test equipment by location apertures arranged to engage location pins.

27. Apparatus as claimed in claim 26 wherein additional location apertures are provided for use of a single board in two disposi tions.

28. Electrical component testing apparatus substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.