GB2157494A

GB2157494A - A hermetic package for TAB bonded silicon die

Info

Publication number: GB2157494A
Application number: GB08509224A
Authority: GB
Inventors: Stanley Bracey
Original assignee: Individual
Current assignee: Individual
Priority date: 1981-06-18
Filing date: 1985-04-10
Publication date: 1985-10-23
Also published as: GB2157494B; GB8509224D0

Abstract

A hermetic ceramic package 92 enclosing a semiconductor die 26 when attached to a TAB interconnect lead frame the lead frame 22 extending through a seal between the upper and lower parts of the package 92. The semiconductor die is mounted on a heat sink 98 having a stud 102 which may connect with other heat sink means. <IMAGE>

Description

SPECIFICATION A hermetic package for tab bonded silicon die This invention, which has many aspects, chiefly concerns the packaging of semiconductor chips or dies. It also has application in other fields, however, for example in the manufacture of circuit interconnects.

One process normally used at present for packaging a chip is as follows: Firstly, a lead pattern is formed by stamping or etching in copper foil that may or may not be mounted on a backing film of insulation material.

This lead pattern comprises an array of leads extending inwardly from an outer frame left at the periphery of the pattern. Thus, the outer ends of the leads are connected to the frame and the inner ends are free for connection to the connection pads on a chip. After the formation of the lead pattern, parts of each frame are gold plated and each frame is passed through a bonding tool where the leads are joined to the chip. Following this, the outer frame is removed and the chip and its connecting leads are packaged.

This involves seating the chip on a rectangular ceramic or plastics bed having connectors projecting from it on two sides. The connectors have inner ends arranged in the vicinity of the chip and these inner ends are joined to the outer ends of the connecting leads extending from the chip. A ceramic or plastics cover is secured to the bed thus protecting the generally rather frail connecting leads attached to the chip. Then the package is tested for faults and, providing that no faults are evident, it can be fitted into a circuit as and when desired.

Alternatively, the connecting leads extending from the chip may first be attached to separate connectors and subsequently this assembly may be encapsulated in plastics material to form the package.

Such processes have a number of disadvantages and much research has been directed towards overcoming these. To date, however, no satisfactory solutions have been found.

The main problem concerns the lead pattern. The foil is not robust and the leads in the pattern are very slender. For this reason, the inner ends of the leads are prone to distortion and damage. This, in turn, creates difficulties in accurately bonding the leads to the chip. In particular, inconsistencies tend to occur in the formation of the bump and the gold plated area normally provided at the inner end of each lead for bonding purposes, and this gives rise to considerable problems. Additionally, any faults which do occur at this stage usually cause a good and costly die to be destroyed.

A further problem is that die manufacturers frequently update their die layouts and reposition the connection pads so that the lead patterns also need redesigning.

One aim of the present invention, in its various aspects, is to overcome these problems, individually or in combination, at least in part.

Another aim is to provide means whereby the packaging of chips is facilitated and the resultant package is rendered more reliable.

According to a first aspect of the present invention, a method of providing a chip with connecting leads comprises preparing a lead pattern, in which an array of leads extends outwardly from an inner link element joining the inner ends of the leads, removing the inner link element, and connecting the inner ends of the leads to a chip.

The invention also embraces the lead pattern itself, and according to this aspect of the invention a lead pattern for providing connections for a chip comprises an array of leads extending outwardly from an inner link element joining the inner ends of the leads.

The inner link element serves to locate the inner ends of the leads in position and significantly diminishes the likelihood of distortion or damage.

By removing this element at the last minute before the leads are connected to the chip, the chances of achieving a fault-free connection are greatly improved.

A tool for achieving this constitutes another aspect of the invention. Such a tool comprises first and second parts relatively movable towards and away from one another, which parts have cooperating surface portions adapted to sever the link element from the lead pattern, and means for bonding the inner ends of the links to the chip.

For example, either or both parts may be provided with heating means for bonding purposes. In the preferred form of the tool, one of the two parts is formed with an internal opening and an optical viewing system is arranged so that the lead pattern and the die can be viewed through this internal opening. This enables the alignment of the lead pattern and die to be checked prior to bonding and facilitates adjustment to achieve the correct alignment.

The lead pattern may take various forms, although for preference it has a link element in the form of a quadrilateral link frame with leads extending generally radially from all four sides.

The leads may either be arranged exactly as required for use, or the lead pattern may be a master pattern with an array of leads only some of which are needed for any particular use. In the latter case, the master pattern is adapted for use by removal of the unwanted leads at the time when the link element is removed.

In order to give the master pattern even greater versatility the leads may be connected to each side of the link frame by way of a connecting beam arranged parallel to the relevant side and a plurality of small connecting bars joining the connecting beam to the link frame. For use, the leads whose outer ends are most suitably placed for the application in question are selected, as also are associated connecting bars whose inner ends are appropriately arranged for connection with the connection pads on a given chip. The other leads and connecting bars, and portions of the connecting beam, are removed with the link frame thus leaving the selected leads and bars and, between each lead and the associated bar, a connection formed from the connecting beam.

Alternatively, the master pattern may have a link element of susbtantial width, only portions of which are removed prior to connection of the pattern to a die, the remaining portions serving to route each lead to an appropriate die pad.

In a preferred form of the invention, a plurality of the lead patterns are formed at spaced intervals along a strip of appropriate material such that the strip provides an outer frame to which the outer ends of the leads are connected. This has the advantage that the lead patterns, once formed, are subsequently maintained in fixed relation during further steps in the process which facilitates advance of the patterns in an accurately defined manner.

The use of a strip of material bearing a plurality of lead patterns therefore has merits in its own right which are not confined to the case where the lead pattern includes an inner link element nor indeed to the case where the lead pattern is intended for providing connecting leads to a chip.

Accordingly, from a further aspect, the invention features a method for use in the manufacture of circuit interconnects comprising providing a conductive strip, removing portions of the strip at intervals along its length to form a residual framework defining a plurality of windows and to form within each window a respective lead pattern connected to the framework, processing each lead pattern for use, and removing it from the strip.

Such a strip is also considered to be inventive and the invention thus further provides a conductive strip adapted for use in the manufacture of circuit interconnects, comprising a framework defining a plurality of windows and, within each window, a respective lead pattern including an array of leads integrally connected to the framework.

The lead pattern may, for example, be designed for use as conductive paths of a circuit or it may be adapted to provide the connecting leads for a chip as mentioned previously. In the former case, components other than chips to the lead pattern. In the latter instance, the processing step in the method will include connecting a respective chip to the leads in each pattern.

In either instance, the processing step may comprise testing each lead pattern, and any components which have been connected to it, by attaching insulating means between the leads and the framework to locate the leads in spaced relation with the framework, removing portions of the pattern connecting the leads to the framework, and then conducting tests. Although this results in disconnecting the leads from the framework, the lead pattern is still attached by the insulating means and thereafter the strip can still be advanced with the lead patterns retained in a fixed and accurately aligned relationship. The advantages of testing a chip and its connecting leads in this manner before the chip is packaged are evident.

According to a further feature of the invention, the processing step mentioned above involves not only bonding a chip to the lead pattern but also enclosing the chip within a package before the lead pattern is removed from the strip. The need for handling the chip prior to packaging is thus largely avoided as a result of which improved reliability can be expected.

If desired, the packaged chip can also be tested as described above in a particularly simple manner before removal from the strip.

A special form of package has been developed for use in these circumstances, although naturally it is not essential for the package to be applied to the chip when it is still carried by the strip.

Thus, a further aspect of the invention features a packaged chip, comprising a chip, a lead frame connected to the chip and packaging means enclosing the chip such that the leads in the lead frame project from the packaging means to provide connectors for connection of the chip into a circuit.

Preferably, the packaging means comprise a pack closely conforming to the dimensions of the chip.

The, contrary to normal practice, the leads may project from the pack on three or more of its sides to provide adequate connecting space for joining the leads to other circuit components in use.

In one form, the pack comprises a ceramic capsule made up from two box portions. The chip is snugly received in and secured to one portion and the leads emerge from the capsule between the two portions where they are held in place by sealing means. The capsule may or may not include a heat sink as desired.

Alternatively, the pack may comprise a moulded plastics casing enclosing the chip and the inner ends of the leads. Again, a heat sink may or may not be provided as required.

Equally, however, the invention lends itself to the packaging of a chip in a more conventional type of ceramic pack. Either, The chip once attached to its connecting leads can be removed from the strip and thereafter packaged in an entirely conventional manner; or, the lead pattern can be adapted to provide not only the conventional connecting leads to the chip but also the connectors which normally extend from a standard package, the connecting leads and the connectors being integral with one another.

In a broad sense, such a lead pattern, which constitutes another aspect of the invention, comprises an outer frame, and an array of leads extending inwardly from the frame, each lead having an outer relatively larger and stronger portion and an inner relatively smaller portion.

Astillfurtheraspectofthe invention is the method of packaging a chip using such a lead pattern and comprising forming a lead pattern having an outer frame and an array of leads extending inwardly from the frame, each lead having a relatively larger and stronger outer portion and a relatively smaller inner portion, connecting a chip to the inner ends of the relatively smaller portions, and removing the outer frame.

The chip may be enclosed within a package, such that relatively larger and stronger lead portions project from the package, either before or after removal of the outer frame.

It is possible to form in the strip a relatively complex circuit pattern made up of a plurality of circuit sections. There are a number of ways in which this can be done.

Firstly, two circuit sections may be formed close together in the strip either simultaneously or successively. For testing purposes, the leads of the two sections are disconnected in the electrical sense but attached by insulating means in the same manner that the leads are attached to the residual framework. After testing, connectors and/or discrete circuit components are applied to the pattern to interconnect the two sectins. Identical composite circuits may thus be produced at intervals along the strip and pre-tested before removal for use.

An alternative way of creating a series of composite circuits, each with a plurality of sections, comprises providing a first strip, removing portions of the first strip at intervals along its length to form a residual framework defining a plurality of windows and to form within each window a respective first circuit pattern including a plurality of leads connected to the residual framework, providing a second strip, removing portions of the second strip at intervals along its length to form a residual framework defining a plurality of windows and to form within each window a second circuit pattern including a plurality of leads connected to the residual framework, adapting the windows of the first strip to receive the second circuit patterns, removing the second circuit patterns from the second strip, inserting them into and retaining them within the windows of the first strip, and connecting each pair of first and second patterns together.

Testing in this instance may be carried out either at a stage when the two types of pattern are still both carried by their respective strips, or at a stage when both types of pattern are supported by the first strip but have not yet been connected together.

Further aspects and features of the present invention are described below, by way of example, with reference to the accompanying drawings in which: Fig. 1 is a plan view of a first lead pattern formed in a strip of conductive material; Fig. 2 is a plan view of a second lead pattern formed in a strip of conductive material; Fig. 3 is a perspective view of a chip connected to either of these lead patterns after the relevant pattern has been adapted for such connection; Fig. 4 is a fragmentary plan view of the pattern, chip, and supporting strip adapted for testing purposes; Fig. 5 is a perspective view of a packaged chip carried by the strip; Fig. 6 is a section through the packaged chip; Fig. 7 is a section through a modified package; Fig. 8 is a section through a variation on the package of figures 5 and 6;; Fig. 9 is a perspective view of a chip attached to a modified type of lead pattern and partially packaged in a different type of package; Fig. 10 is a plan view of a tape carrying a more complex lead pattern and two dies and illustrating how this circuit arrangement is generated; Fig. 11 is a diagrammatic view of two tapes showing how the same circuit pattern may be generated in a different manner; Fig. 12 is a diagrammatic view through a tool for preparing the lead pattern to be connected to a chip and for bonding the leads in the pattern to the chip; Fig. 13 is a face view of one part of the tool; and Fig. 14 and 15 are face views of the same part modified for different lead patterns.

For the sake of simplicity, the basic process embodying the present invention will be described in detail first. The main variations of this process will be individually described afterwards.

BASIC PROCESS Referring initially to figures 1,3 and 4, the process embodying the present invention in one of its simpler forms is as follows: A strip 10 of conductive material is first formed with a row of regularly spaced apertures 12 along each edge. These apertures are used for feeding purposes for advancing the strip by a predetermined amount at discrete time intervals.

The strip is then advanced past a pattern forming station. Here, portions of the tape are removed, as by stamping or etching, leaving a residual frame 14, which defines a window 16 in the strip 10, and leaving within the window 16 a lead pattern 18. As shown in Figure 1, the lead pattern 18 comprises an inner link element 20, in this instance a quadrilateral link frame, and an array of leads 22 extending outwardly from the inner link frame 20 to the residual frame 14. The leads extend from all four sides of the link frame 20 and each lead is joined at its two ends to the link frame 20 and residual frame 14 by way of narrow bridges 24.

From the pattern forming station, the strip is advanced to a cleaning station where the lead pattern is cleaned, for example by conventional plasma etching techniques, in order to produce fresh oxide on the pattern, which is softer than that generated through exposure to the atmosphere over a period of time.

The strip then goes through a bonding station where a tool, illustrated in Figure 12 and described in greater detail below, performs three operations on the lead pattern. Firstly, it removes the inner link frame 20 and the bridges 24 by which this frame is attached to the leads 22. Next, a chip or die 26 is inserted into the tool and the tool bonds, for example welds, the inner ends of the leads 22 to the connection pads on the chip 26. Finally, and this is optional depending upon the intended application of the chip, the tool forms a kink or joggle in each lead. Of course, it will be appreciated that it is not essential to perform these steps in this particular order.

Figure 3 shows a chip after emerging from the bonding station.

Downstream of the bonding station, there is a testing station. At the testing station, insulating tape 28 is adhered to the frame 14 about the window 16 so as to retain the outer ends of the leads in position, and a punch removes the bridges 24 connecting the leads 22 to the frame 14. The outer lead ends are then spaced from the residual frame 14 and therefore the lead pattern is in no way conductively connected to the frame 14. The chip and its connecting leads are then tested by conventional techniques.

After the testing station, the strip passes either directly or indirectly, after first being shipped to a customer, to a removal station at which the insulating tape 28 is removed, thus detaching the chip and its connecting leads from the strip 10.

The chip is then prepared for use by conventional means. For example, its leads are bonded to a lead frame and it is mounted on a standard chip carrier, or it is attached directly to a printed circuit substrate.

A continuous process is thus provided in which each section of the strip 10 passes successively through the different stations and in which different sections of the strip at different stages of the process are all concurrently undergoing the respective operations. A high throughput can thus be achieved. Provision of the link frame 20 ensures that the leads 22 are not displaced from their positions prior to bonding which enhances reliability. And, pre-testing of the chip and its connecting leads before it is detached from the strip 10 and before packaging minimizes waste.

BONDING TOOL The bonding tool is illustrated in Figures 12 and 13.

This tool comprises a lower tool part 40 and an upper tool part 42 between which the strip 10 is arranged to be advanced. The two tool parts have co-operating surfaces 44,46 dimensioned such that when the lead pattern 18 is centered relative to the two parts, the co-operating surfaces will overlie the inner link frame 20 and the inner ends of the leads 22.

For centering the lead pattern 18 relative to the two parts, the upper part 42 is provided with a central opening 48, and an optical viewing system 50 is arranged to permit viewing of the lead pattern 18 through this opening. For example, the viewing system 50 may include a lens 52 disposed in the opening 48, a reflector 54 arranged above the tool part42to reflect lightfrom the lens 52, and a viewing arrangement such as binoculars or a closed circuit television camera situated to receive light from the reflector 54.

The surface 44 of the lower tool part is substantially plane, apart from a plurality of small recesses 56 corresponding in number and location to the inner ends of the leads 22. The surface 46 (shown in Figure 13) has a raised portion 58 whose profile corresponds to that of the inner link frame 20 and whose height is slightly less than the thickness of the strip 10.

The two parts 40, 42 are movable towards and away from one another and, when the lead pattern 18 is centered between them and they are brought together, the raised portion 58 punches the lead frame 20 and associated bridges 24 from the lead pattern and the inner ends of the leads 22 are compressed between the surfaces 44, 46 so that some material is forced into the recesses 56 forming small bumps on the inner ends of the leads 22.

Within the upper tool part 42, there are passages 60 serving to connect openings 62 in its surface 46 to a vacuum/air supply and control unit. The openings 62 are arranged opposite the recesses 56 for registration with the inner ends of the leads 22.

After the link frame 20 has been detached from the lead pattern 18, the control unit withdraws air from the passage 60 so that the inner ends of the leads 32 are drawn against and held to the surface 46. The upper tool part 42 is then raised away from the lower part 40 and the link frame 20, which remains resting on the lower part 40, is removed.

Concurrently, the chip 26 is placed on the lower tool part 40 and positioned with the aid of the viewing system 50. Once again, the upper part 42 is lowered, bringing the inner ends of the leads 22 into contact with the connection pads on the chip 26. The tool parts 40,42 are urged together with a force which causes the bumps on the inner lead ends to collapse and at the same time a burst of power is applied to the heating elements 64 within the two tool parts to heat the inner lead ends and the correspdonding pads on the chip and to effect a permanant connection.

A pair of joggle tool parts 66,68 encircle the parts 40,42 and, likewise, are movable towards and away from one another. Each part 66,68 has a contoured surface arranged to provide a kink or bend in each lead 22 when the two joggle parts are brought together. This is done once the leads have been connected to the chip 27.

Thereafter, the joggle parts 66 and 68 are separated. The upper and lower tool parts 40,42 are also separated and simultaneously air is forced through the opening 62 ensuring that the chip with the connecting leads attached is positively freed from the upper tool 42.

The strip is then advanced and the process is repeated.

Various modifications are possible to the tool just described. For example, the viewing system 50 may comprise a bundle of optical fibres. The joggle parts 66,68 can be arranged to form the bends in the leads 22 before these are attached to the chip rather than after. The heating element 64 in the tool parts 40, 42 may be omitted and bonding of the leads to the chip can be effected by ultrasonics. Also, the tool may be arranged only partially to sever the link frame 20 from the remainder of the pattern prior to bonding. Then, after bonding, the link frame can be forcibly detached to test the bond strength.

This tool is designed to enable accurate alignment both of the lead pattern and the chip for bonding. In particular, the severing of the link frame 20 from the lead pattern 18 at the last minute before bonding, and the application of suction to the inner lead ends through the opening 62 to lift these ends from the surface 44 whilst the chip is inserted in place, ensures that these ends are maintained in the desired location for registration with the connection pads on the chip until contact has been made and the contact pressure takes over the function of retaining the ends in place until bonding has been effected.

PROCESS EMPLOYING MASTER LEAD PATTERN The process and tool described so far are intended for use when high volume runs of identical leaded chips are required. For smaller volume runs, when the arrangement of the leads in the bonded chip is to be altered between runs, it may be preferable to modify the process and the tool somewhat so that they are more readily adaptable.

In the case of the process, this will be identical with that already described except at the pattern forming stage and the bonding stage. For the sake of simplicity, in the following description the same reference numerals are used for parts similar to those already mentioned.

At the pattern forming station, the lead pattern 70 illustrated in Figure 2 is stamped, etched or otherwise produced in the strip 10. This lead pattern has a plurality of leads 22 extending inwardly from the residual frame 14 as before except that the leads are present in considerably greater number. An inner link frame 20 is also provided but, in this instance, it is not connected to the leads 22 by way of bridges 24. Instead, the leads 22 on each side of the frame 20 are joined to a respective common connecting beam 72 arranged parallel to that side of the frame 20.

The beam 72 is in turn connected to the associated side of the inner link frame 20 by a large number of parallel connecting elements 74.

In the bonding station, additional sections of the lead pattern are partially severed or removed, as well as the link frame 20, prior to bonding in order to produce an array of leads suitable for the particular chip and application. More particularly, all unwanted leads 22 are cropped leaving only those leads which are suitably arranged for connection of the chip in its intended site for use. Some of the connecting elements 74 are also taken out such that the ones which remain are appropriately sited for connection to the connecting pads on the particular chip. The remaining leads 22 and the remaining connecting elements 74 correspond in number and are associated in pairs. Each pair is connected by a respective portion of the connecting beam 72, the remainder of the beam being removed with the unwanted leads and connecting elements.

For the purposes of removing the extraneous sections of the lead pattern 70, the upper and lower tool parts of the bonding tool have enlarged cooperating surfaces, by comparison with the tool illustrated in figure 12, to allow a raised portion 76 of the upper tool to sever the outer ends of the unwanted leads from the residual frame 14. A plan view of the surface of the upper tool part including the raised portion 76 is illustrated in figure 15, from which it will be apparent that the raised portion constitutes a considerable larger proportion of the surface of the upper tool part in this instance than in the case of the tool illustrated in figure 12.

In the modified tool, the viewing system 50, the suction/air supply passage 60 and the openings 62 are provided as previously. The joggle parts 66, 68 are either omitted entirely from the bonding station, in which case an additional station may, if desired, be provided for creating the bends in the leads, or they are made integral with the upper and lower tool parts.

By arranging for the portion of the upper tool part which removes sections of the lead pattern 70 to be removable and replaceable with a different such portion, the upper tool part can readily be adapted to suit different circumstances.

In an alternative arrangement of the master pattern, the elements 74 are replaced by a single band completely filling the space between the frame 20 and beam 72, so as to provide a solid link frame of substantial width. Then, portions of this frame are removed to produce the desired connection arrangement at the inner ends of the leads 22.

A slightly less versatile arrangement may be achieved in a similar manner by producing a simplified lead pattern such as the one illustrated in Figure 1 in the first instance and by arranging for the bonding tool to detach some of the leads with the link frame 20. For this purpose, the upper and lower tool parts will again have to be enlarged by comparison with the ones illustrated in Figure 12 to enable them to sever the outer ends of the relevant leads. The surface of the upper tool part and its raised portion 77 may, for example, take the form illustrated in Figure 14 in this instance.

MODIFIED PROCESS EMPLOYING PACKAGING CAPSULE In this modified process, the chip with its connecting leads is not detached from the strip 10 after beng tested but undergoes further processing first.

Instead of being advanced to the removal station from the testing station, the strip 10 is advanced to a packaging station where the chip is packaged in a small ceramic capsule 90.

Such a capsule is illustrated in figures 5 and 6 and comprises a ceramic box dimensioned so that the chip 26 fits snugly inside it. The capsule is constructed in two halves 92 and at the packaging station the chip is first secured by a eutectic/epoxy or solder connection 94 to the base of one of these halves with the greater portion of each lead 22 extending outwardly beyond its rim. The other half of the capsule is then applied over the first half and a glass or epoxy seal 96 is formed between the two to join them together and hold the leads in position.

This simple manner of packaging the chip does not involve any high degree of handling nor the need for subjecting the chip to severe conditions and, for this reason, the resultant package is particularly reliable.

In order to ensure that no damage has occurred, however, the packaged chip is next passed through a further testing station where it is tested for faults.

Since the leads 22 are already disconnected from the residual frame in a conductive sense and are attached simply by the insulating tape, the packaged chip is in a condition for testing upon arrival at the testing station.

After the chip has undergone a second testing step, the strip is advanced to a removal station and the packaged chip is detached from the strip 10 ready for use.

In some cases, the first testing step, prior to packaging, may be omitted.

A number of variations on the capsule itself are possible. One of these is illustrated in Figure 7. In this case, the capsule 90 additionally includes a heat sink 98 on which the chip 26 is mounted by a eutectic solder or epoxy connection 100. The heat sink itself is supported by the base of the lower capsule half and a heat sink pin 102 projects from this half.

Another variation on the capsule is illustrated in Figure 8 and comprises a plastics encapsulating mass 104, in place of the ceramic box, entirely enveloping the chip 26 and the inner ends of the leads 22. A heat sink may be provided within the encapsulating mass 104 if desired.

The resultant package in all these cases comprises a small rectangular pack closely corresponding in size to the chip itself, with the connecting leads attached to the chip projecting from the pack on two, three orfoursides. The package maytherefor be particularly compack, which opens up numerous applications for the chip where previously problems have been encountered by the limited availability of space.

MODIFIED PROCESS IN WHICH CHIP IS PACKAGED IN A STANDARD CHIP CARRIER Afurtherform of the process described initially features a modified strip and a modified packaging arrangement.

The strip illustrated in figures 1 and 2 is of constant thickness and has a width just sufficient to provide a lead pattern from which the normal connecting leads for a chip are created. It is alternatively possible, however, for the strip to be modified so that the lead pattern formed in it can be used not only to provide the standard connecting leads for the chip but also, integral with these leads, the connectors employed in a standard dual in-line package. The final package may then have the appearance of a standard packaged chip but it will differ from such a package internally, in that the connecting leads of the chip are not bonded to the package connectors as is usual.

The tape is adapted for providing the package connectors by forming it with a variable thickness.

The central portion of the tape has a thickness suitable for providing the connecting leads for the chip and flanking this portion are two portions of increased thickness suitable for providing the connectors of the chip package.

The strip is processed as described initially until the chip and the lead have been tested. Thereafter, the strip is advanced to a packaging station where the chip is embedded in a standard ceramic bed such that the thicker outer portions of the lead pattern project from the bed to form connectors; and to a removal station where the packaged chip is detached from the strip. the packaged chip is then prepared for use by bending the projecting connectors through 90 degrees to form the two sets of connecting legs normally seen in such a package.

The package resulting from this modified version of the process is illustrated in figure 9. The portion of the upper part of the chip package 120 has been broken away to show the chip 26 with its connecting leads 122, and to show the connectors 124 of the package integrally joined to the leads 122.

One of the main advantages of this package is that it avoids the occurrence of faults through misalignment or bond failure of the connecting leads attached to the chip and the connectors of the package.

PROCESS FOR CREATING COMPOSITE CIRCUIT PATTER N This is a development of the basic process in which a composite lead pattern is formed in the strip 10 at the pattern forming station. The composite lead pattern comprises two of the master patterns 70 arranged side by side with the links at their adjacent sides joined directly together.

After cleaning at the cleaning station, the composite pattern passes through the bonding station where portions of each master pattern section are first removed. In the adjacent regions of the two sections, each pair of connected leads 128 is either removed as a whole or as a whole left intact, so that in the final circuit these leads will form continuous paths between the two chips which are next attached to the two sections.

At the testing station to which the chips with their connecting leads are now carried, the bridges 24 connecting the leads in both sections to the residual frame are replaced by insulating tape. Additionally, portions of the interconnected leads 128 at the adjoining edges of the two sections are taken out and a length 130 of adhesive insulating tape is laid across the strip for holding the now separated leads 128' in place for testing. The two sections of the pattern are tested individually and the strip is then advanced to a packaging station.

Apparatus at the packaging station packages the two chips in one of the types of capsule illustrated in and described with reference to Figures 5 to 8.

At a further testing station downstream of the packaging station, both packaged chips are tested again and from there the strip is next advanced to an assembly station.

There, connecting links 140 or discrete circuit components 142 are inserted between the separated leads 22 (see Figure 10) to complete the circuit.

Afinal, removal, station is situated after the assembly station for detachment of the composite circuit from the strip.

In a minor modification of this version of the process, the two pattern sections are created successively instead of simultaneously.

The thickness of different portions of the lead pattern is selected as desired.

ALTERNATIVE PROCESS FOR CREATING COMPOSITE CIRCUIT As an alternative to the process just described for creating the same final composite product, it is possible to prepare the two sections of the circuit separately, each in relation to a different strip 10', 10", and to combine the two sections once the two chips have been packaged and tested.

Each packaged chip is prepared using the basic method modified, if desired, by the use of the master pattern and modified by encapsulating the bonded and tested chip in one of the capsules illustrated in figures 5 to 8. Each encapsulated chip is tested and then the chips are combined in a composite circuit at a combination station as follows: One strip 10' passes into the station and has its window 16 enlarged by an amount corresponding to the window 16 in the other strip 10". The connecting leads 22 extending towards the space newly formed in the strip 10' are, however, not released, and liable to damage as a result, because the insulating tape applied to the leads for testing purposes remains and holds them in position.

Next, the second strip 10" is brought into overlying relation with the first and the packaged chip carried by the second strip is transferred to the space created for it next to the first packaged chip.

The second strip has now served its purpose but the first continues to an assembly station and on to a removal station as described with reference to the previous process for creating a composite circuit pattern.

The present process can, of course, be extended to add any number of circuit sections from different tapes. These sections may be arranged side by side as just described.

Alternatively or as well, two sections may be combined by placing one on top of the other, in which case there is no need to enlarge the window in the strip which is to receive the additional section.

Connecting links for discrete circuit components will, however, be applied at the assembly station as previously. Since, in all cases, the packaged chips have been pretested before combination, a reliable composite circuit can be built up in a simple manner.

It will be appreciated that the present invention has many aspects and is capable of various modifications. Those described can be employed singly or in combination either with or without additional modifications of a more minor nature. For example, in some applications testing is not necessary and the testing steps may therefore be omitted.

The invention is considered most suitable for use with aluminium alloy strip, in which case regions may, in some applications, have to be plated for the purposes of connection and protection.

Alternatively, however, copper foil may be used if desired.

Also, it should be noted, the invention may be used for securing connecting leads to components other than chips.

Claims

1. A ceramic package for hermetically packaging semiconductor die which are attached to a TAB interconnect leadframe and in which the leadframe passes through the wall of the package at the seal between an upper and lower part.

2. A ceramic package as claimed in claim 1 which also includes a thermal pillar in the form of metal pillars between the inner cavity of the package and an outer surface.

3. A ceramic package as claimed in claim 2 but where the pillar extends beyond the outer surface to provide a stud for example to connect additional heat sinking facility.

4. A ceramic package is hereinbefore substantially described and with reference to the accompanying drawings and text.