GB2157085A - Multilayer flexible circuit with ultrasonically welded interlayer connections - Google Patents
Multilayer flexible circuit with ultrasonically welded interlayer connections Download PDFInfo
- Publication number
- GB2157085A GB2157085A GB08508567A GB8508567A GB2157085A GB 2157085 A GB2157085 A GB 2157085A GB 08508567 A GB08508567 A GB 08508567A GB 8508567 A GB8508567 A GB 8508567A GB 2157085 A GB2157085 A GB 2157085A
- Authority
- GB
- United Kingdom
- Prior art keywords
- traces
- circuit
- multilayer circuit
- circuit configuration
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011229 interlayer Substances 0.000 title description 2
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 230000005923 long-lasting effect Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229920002799 BoPET Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000005041 Mylar™ Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920005570 flexible polymer Polymers 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
- H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/0939—Curved pads, e.g. semi-circular or elliptical pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0285—Using ultrasound, e.g. for cleaning, soldering or wet treatment
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Combinations Of Printed Boards (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
A multilayer flexible circuit (10) in which polymer thick film (PTF) circuits (18, 20, 28) are separated by an insulating polymer layer (16). The circuits are interconnected by ultrasonic welds, the circuit traces having enlarged connection pads (22, 24, 30, 32) in the areas of the welds. <IMAGE>
Description
SPECIFICATION
Multilayer flexible circuit with ultrasonically welded interlayer connections
This invention relates to the field of. electrical circuit connection. More particularly, this invention relates to interconnections between multilayer flexible circuits in which the circuits consist of circuit traces or circuit patterns on insulating polymer
substrates.
Multilayer flexible circuits are known in which the circuits are made with polymer thick film (PTF) technology. These circuits include sheets of flexible
polymer substrate material with circuit patterns thereon. The insulating substrate materials may be, for example, a polyester plastic such as Mylar
(RTM) or other known plastic insulating materials;
and the conductive traces may be conductive ink
or paste or copper or other standard conductive trace materials for flexible circuitry and membrane
keyboards. It is often desirable to interconnect two
layers of flexible circuitry which face each other.
Currently there are three main methods for provid
ing such interconnection. One method is to form a
conformal coating of insulating material over the
appropriate traces and then use a conductive ink to
close the connection between the two layers by
crossing oVer the insulating material. A second
method is to separate the conductive traces by a
nonconductive insulating layer and make the con
nections by plating through holes through the in
sulating layer at the appropriate locations. A third
method is to separate the conductive traces by a
nonconductive insulating layer except in areas
where connections are to be made, and connec
tions are made by metallic crimps which pass
through the two layers of conductive circuitry and
hold in contact the conductive traces to be con
nected.These methods are plagued with reliability
problems due to either migration through the conformal coating of insulating material, and/or to
voids in the conductive material in the through
holes, and/or poor crimp connections. Also, these
methods require expensive materials and/or proc
essing steps.
There is a recognized need for a long lasting, re
liable and relatively inexpensive interconnection
method and structure which has not heretofore
been available in the art.
The above discussed and other problems of the
prior art are eliminated or reduced by the present
invention. In accordance with the present invention there is provided a multilayer circuit configuration
including a first circuit layer having at least one
first conductive trace thereon, a second circuit
layer having at least one second conductive trace
thereon, said first and second traces being in fac
ing relationship, said first and second conductive
traces each having an enlarged. connection pad of
predetermined configuration at opposed locations,
and ultrasonic weld means interconnecting said first and second traces at said enlarged connection
pads.
The termination pads are of special shape to effect reliable and permanent contact. The resulting interconnected multilayer flexible circuitry is reliable and relatively inexpensive.
It has also been determined that specific interconnect patterns contribute to improved reliability and dependability.
Referring now to the drawings, wherein like elements are numbered alike in the several Figures:
Figure 1 shows an exploded schematic view of one multilayer circuit in accordance with the present invention.
Figure 2 shows an exploded view of another multilayer circuit in accordance with the present invention.
Figure 3 shows a side elevation of the multilayer circuit of Figure 2.
Figures 4A, 4B, 4C, 4D and 4E show specific interconnect configurations in accordance with the present invention.
Figures 5-5C show a foldover circuit with the top and bottom layers interconnected with a special interconnect pattern in accordance with the present invention. Figure 5 shows a top plan view of the foldover circuit; Figure 5A shows a partial side elevation; Figure 5B shows a front edge view (looking at the right had end of Figure 5); and Figure 5C shows an enlargement of the interconnect area.
Referring to Figure 1, an exploded view is shown of a multilayer circuit 10. Multilayer circuit 10 has a lower circuit sheet 12, an upper circuit sheet 14, and an intermediate insulating spacer sheet 16.
Lower circuit sheet 12 has conductive traces 18 and 20 on the upper surface thereof which terminate in interconnection pads 22 and 24. Merely for purposes of illustration, another conductive trace 26 is shown on circuit sheet 12 between conductive traces 18 and 20. The presence of conductive trace 26 does, however, make it impossible to connect traces 18 and 20 on circuit sheet 12; so, it it is desired to interconnect traces 18 and 20, the interconnection must be made through upper circuit sheet 14.
The lower surface of circuit sheet 14 (i.e., the surface facing sheet 12) has a conductive trace 28 with termination pads 30 and 32 which are aligned, respectively, with termination pads 22 and 24 on the upper surface of circuit sheet 12. Conductive trace 28 is shown in dashed or broken line merely to indicate that it is on the bottom surface of sheet 14. Also, insulating spacer layer 16 has a pair of apertures 34 and 36 which are aligned with termination pads 22 and 30 and terminations pads 24 and 32, respectively.
To assemble the multilayer circuit of the present invention, the circuit layers 12 and 14 and the separating insulating layer 16 are brought together in the alignment shown in Figure 1, with the circuit traces facing each other and separated by insulating layer 16. With this alignment, termination pad 22 is in alignment with termination pad 30 through aperture 34, and termination pad 24 is in alignment with termination pad 32 through aperture 36. The sheets are brought together in an assembly with spacer sheet 16 sandwiched between circuit sheets 12 and 14. The assembly of the three sheets may be adhesively bonded together at selected points if desired.
Electrical interconnection between termination pads 22 and 30 and between termination 24 and 32 is effected by ultrasonically welding the aligned termination pads to each other through the respective apertures in sheet 16. The resulting structure is a multilayer interconnected circuit with a long lasting reliable and relatively inexpensive interconnect system.
The interconnebout involvement and complications which might otherwise be present from the prior art interconnect systems such as plated through holes and conformal coatings. Furthermore, the interconnect system of the present invention lends itself particularly well to the design of interconnections which are particularly reliable.
To this end, several particularly preferred termination pad and interconnection layouts are shown in
Figures 4A-4E.
Figures 2 and 3 show the present invention employed to interconnect circuit layers of a type which, in the prior art, were typically connected by crimp connectors. in this embodiment, a multilayer circuit 50 has a lower circuit sheet 52, an upper circuit sheet 54 and an insulating spacer 56. Lower circuit sheet 52 has conductive traces 58 and upper circuit sheet 54 has conductive traces 60. The circuit segments to be interconnected may, for example, be tail areas of flexible circuits.
As best seen in Figure 3, insulating layer 56 stops short of the end of circuit layer 52, so that conductive traces 58 and 60 are exposed to each other at facing locations. In a typical prior art construction, costly crimp connectors would be used to connect together circuit sheets 52 and 54 in the area where traces 58 and 60 are exposed to each other, thus effecting electrical contact between the conductive traces on the two circuit sheets. In accordance with the present invention, the facing and exposed conductive traces are connected together by ultrasonic welds to deliver power or signals from one circuit sheet to the other, thus eliminating the costly crimp connectors and achieving positive and reliable interconnection.
It is to be understood that the present invention involves more than the elemental structure of ultrasonic weld interconnection. The present invention is also directed to specific interconnect configurations in the areaof the weld. When effecting the ultrasonic weld, care must be taken to ensure that the weld does not interfere with circuit functions, such as, for example, by changing circuit resistance. To this end, in accordance with the present invention the circuit traces to be interconnected are modified in shape in the area t traces to be connected (e.g., the lower and upper traces 18, 20 of Figure 1 or the lower and upper traces 58, 60 of Figure 3) will be specially and similarly shaped in the connection pad areas.
While the connection pad enlargement may take several shapes (as shown in Figures 4A-4E or other shapes), the basic parameter of the enlarged connection pad is that it does not adversely affect rsistivity or other electrical parameters of the traces being connected.
Figures 5-5C show a typical foldover circuit 80 (such as is common in a flexible circuit keyboard) with lower layer 82 and upper layer 84 interconnected by an ultrasonic weld in accordance with the present invention. Lower cirouit sheet 82 has conductive traces 86 on its upper surface, and upper circuit sheet 84 has conductive traces 88 on its lower surface. For simplicity of illustration, these conductive traces are shown only in the end or tail area where connection is to be made, but it will understood that they continue in desired patterns on the remainder of the sheets. The upper and lower circuit sheets are separated by an insulating spacer 90 except in the area where ultrasonic weld connections are to be made (or holes can be located in the spacer at the weld position).
As best seen in Figure 5" the circuit traces (both 86 and 88) are enlarged at 92, and are connected together at the site of the enlargement by an ultrasonic weld 94. Thus, power or a signal in traces 86 is delivered to the respective connected traces 88.
Claims (1)
1. A multilayer circuit configuration including a first circuit layer having at least one first conductive trace thereon,
a second circuit layer having at least one second conductive trace thereon,
said first and second traces being in facing relationship,
said first and second conductive traces each having an enlarged connection pad of predetermined configuration at opposed locations, and
ultrasonic weld means interconnecting said first and second traces at said enlarged connection pads.
2. A multilayer circuit configuration as claimed in Claim 1, wherein said connection pads are configured to meet the parameter of effecting electrical connection without impairing electrical characteristics of said traces.
3. A multilayer circuit configuration as claimed in Claim 1, wherein said connection pads are configured to effect electrical connection without impairing red in Claim 4, wherein said enlarged area is rectangular.
6. A multilayer circuit configuration as claimed in Claim 4, wherein said enlarged area is arcuate.
7. A multilayer circuit configuration as claimed in Claim 4, wherein said enlarged area is circular.
8. A multilayer circuit configuration as claimed in any one of Claims 1 to 7, including insulating spacer means between said first and second circuit layers to insulate said layers other than in said contact pad areas.
9. A multilayer circuit configuration substantially as hereinbefore described and as illustrated in the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8405220A FR2562335B1 (en) | 1984-04-03 | 1984-04-03 | FLEXIBLE MULTILAYER CIRCUIT WITH CONNECTIONS BETWEEN ULTRASONIC WELDED LAYERS |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8508567D0 GB8508567D0 (en) | 1985-05-09 |
| GB2157085A true GB2157085A (en) | 1985-10-16 |
| GB2157085B GB2157085B (en) | 1987-06-24 |
Family
ID=9302775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08508567A Expired GB2157085B (en) | 1984-04-03 | 1985-04-02 | Multilayer flexible circuit with ultrasonically welded interlayer connections |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS60227497A (en) |
| DE (1) | DE3512237A1 (en) |
| ES (1) | ES295813Y (en) |
| FR (1) | FR2562335B1 (en) |
| GB (1) | GB2157085B (en) |
| IT (1) | IT1183552B (en) |
| SE (1) | SE459832B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0278485A2 (en) * | 1987-02-13 | 1988-08-17 | Aristo Graphic Systeme GmbH & Co KG | Process for making a digitalization board |
| EP0278484A2 (en) * | 1987-02-13 | 1988-08-17 | Aristo Graphic Systeme GmbH & Co KG | Process for making a digitalization board |
| GB2227887A (en) * | 1988-12-24 | 1990-08-08 | Technology Applic Company Limi | Making printed circuits |
| GB2233157A (en) * | 1989-06-13 | 1991-01-02 | British Aerospace | Conductive track arrangement on a printed circuit board |
| GB2240221A (en) * | 1989-12-26 | 1991-07-24 | Nippon Cmk Kk | Method of forming an insulating layer on a printed circuit board |
| US5347710A (en) * | 1993-07-27 | 1994-09-20 | International Business Machines Corporation | Parallel processor and method of fabrication |
| EP1094693A2 (en) * | 1999-10-18 | 2001-04-25 | Sony Chemicals Corporation | Multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards |
| US6428908B1 (en) * | 1997-07-16 | 2002-08-06 | Fraunhofer Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Contact and method for producing a contact |
| US9011799B2 (en) | 2011-08-11 | 2015-04-21 | Eppendorf Ag | Laboratory sample instrument with printed circuit board cable device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3535008C2 (en) * | 1985-10-01 | 1994-09-29 | Telefunken Microelectron | Foil circuit with two overlapping cable carriers |
| DE10035175C1 (en) * | 2000-07-19 | 2002-01-03 | Fraunhofer Ges Forschung | Making electrical/mechanical connection between flexible thin film substrates involves positioning substrates so openings coincide, positioning bonding elements, pressing together |
| DE102005033218A1 (en) * | 2005-07-15 | 2007-01-18 | Printed Systems Gmbh | Three-dimensional circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1456994A (en) * | 1973-06-28 | 1976-12-01 | Marconi Co Ltd | Methods for forming electrical internconnection between metal layers for printed circuit assembly |
| FR2380686A1 (en) * | 1977-02-15 | 1978-09-08 | Lomerson Robert | PROCESS FOR ESTABLISHING AN ELECTRICAL CONNECTION THROUGH A PLATE OF INSULATING MATERIAL |
-
1984
- 1984-04-03 FR FR8405220A patent/FR2562335B1/en not_active Expired
-
1985
- 1985-04-01 ES ES1985295813U patent/ES295813Y/en not_active Expired
- 1985-04-02 IT IT20190/85A patent/IT1183552B/en active
- 1985-04-02 GB GB08508567A patent/GB2157085B/en not_active Expired
- 1985-04-02 SE SE8501635A patent/SE459832B/en not_active IP Right Cessation
- 1985-04-03 DE DE19853512237 patent/DE3512237A1/en not_active Ceased
- 1985-04-03 JP JP60070730A patent/JPS60227497A/en active Granted
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0278484A2 (en) * | 1987-02-13 | 1988-08-17 | Aristo Graphic Systeme GmbH & Co KG | Process for making a digitalization board |
| EP0278485A3 (en) * | 1987-02-13 | 1989-09-20 | Aristo Graphic Systeme Gmbh & Co Kg | Process for making a digitalization board |
| EP0278484A3 (en) * | 1987-02-13 | 1989-09-20 | Aristo Graphic Systeme Gmbh & Co Kg | Process for making a digitalization board |
| EP0278485A2 (en) * | 1987-02-13 | 1988-08-17 | Aristo Graphic Systeme GmbH & Co KG | Process for making a digitalization board |
| GB2227887A (en) * | 1988-12-24 | 1990-08-08 | Technology Applic Company Limi | Making printed circuits |
| GB2233157B (en) * | 1989-06-13 | 1992-10-21 | British Aerospace | Printed circuit board |
| GB2233157A (en) * | 1989-06-13 | 1991-01-02 | British Aerospace | Conductive track arrangement on a printed circuit board |
| GB2240221A (en) * | 1989-12-26 | 1991-07-24 | Nippon Cmk Kk | Method of forming an insulating layer on a printed circuit board |
| GB2240221B (en) * | 1989-12-26 | 1994-03-30 | Nippon Cmk Kk | Improvements relating to multi-layer printed circuit boards |
| US5347710A (en) * | 1993-07-27 | 1994-09-20 | International Business Machines Corporation | Parallel processor and method of fabrication |
| US6428908B1 (en) * | 1997-07-16 | 2002-08-06 | Fraunhofer Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Contact and method for producing a contact |
| EP1094693A2 (en) * | 1999-10-18 | 2001-04-25 | Sony Chemicals Corporation | Multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards |
| EP1094693A3 (en) * | 1999-10-18 | 2003-08-27 | Sony Chemicals Corporation | Multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards |
| US6812060B1 (en) | 1999-10-18 | 2004-11-02 | Sony Chemicals Corporation | Multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards |
| US9011799B2 (en) | 2011-08-11 | 2015-04-21 | Eppendorf Ag | Laboratory sample instrument with printed circuit board cable device |
Also Published As
| Publication number | Publication date |
|---|---|
| SE8501635L (en) | 1985-10-04 |
| FR2562335B1 (en) | 1988-11-25 |
| ES295813U (en) | 1987-06-16 |
| GB2157085B (en) | 1987-06-24 |
| GB8508567D0 (en) | 1985-05-09 |
| DE3512237A1 (en) | 1985-12-12 |
| FR2562335A1 (en) | 1985-10-04 |
| IT1183552B (en) | 1987-10-22 |
| SE8501635D0 (en) | 1985-04-02 |
| JPH0564880B2 (en) | 1993-09-16 |
| ES295813Y (en) | 1987-12-16 |
| JPS60227497A (en) | 1985-11-12 |
| IT8520190A0 (en) | 1985-04-02 |
| SE459832B (en) | 1989-08-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19940402 |