GB2156556A

GB2156556A - Electrical circuit unit and circuit arrangement including a plurality of such units

Info

Publication number: GB2156556A
Application number: GB08407620A
Authority: GB
Inventors: Stewart Frederick Bryant
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1984-03-23
Filing date: 1984-03-23
Publication date: 1985-10-09
Also published as: JPS60238953A; EP0179497B1; GB8407620D0; EP0179497A2; GB2156556B; US4642473A; DE3587103T2; DE3587103D1; EP0179497A3

Description

1 GB 2 156 556A 1

SPECIFICATION

Electrical circuit unit and circuit arrangement including a plurality of such units The invention relates to an electrical circuit unit including means for recognising an address signal applied thereto and to a circuit arrangement including a plurality of such cir- cuit units.

One problem in designing and constructing electronic systems which includes a plurality of circuit units is the assignment to each unit of a unique identity or address. Such units may be RAMs, ROMs, Codecs, etc. which may be, for example, in the form of integrated circuits, hybrid circuits or printed circuit boards carrying a plurality of discrete and/or integrated circuits. One possibility is to assign an address to each circuit unit at the manufacturing stage but this leads both to more expensive circuit units and to a greater possibility of inserting the circuit units into the wrong position within the system. Another possibility is to provide each circuit unit with a 90 number of programming pins which are connected to internal decoding circuitry and to external potentials either directly or through switches. These two possibilities may be com- bined so that part of the address is fixed at the manufacturing stage and part is programmable. The fixed portion of the address normally indicates the type of circuit, i.e. RAM, Codec, etc., while the programmable part identifies the particular circuit of that type. This reduces the number of external pins required which is particularly important when the circuit unit is formed as an integrated circuit since the cost of an integrated circuit increases significantly with each additional pin provided. However the number of circuit units which can be addressed is limited if the number of programming pins is not to become excessive. A further possibility is to provide an external address decoding circuit feeding an enable pin on the integrated circuit. This reduces the number of addressing pins required to one but has the disadvantage that additional circuit elements have to be provided to enable addressing to be effected thus increasing the cost and complexity of the system.

When the circuit units are formed as printed circuit boards (PCBs) which are plugged into either a mother board or a wiring frame it is usual to provide programming switches on the PCB which are appropriately set to give the PCB address. This arrangement has a number of disadvantages amongst which are the diffi- culties involved with mounting and soldering the switches to the PCB, the possibility of incorrectly setting the switches, and the area of the PCB occupied by the switches which reduces the available board area for the func- tional parts of the circuit unit.

It is an object of the invention to enable the provision of a simple means of assigning addresses to each of a plurality of circuit units in a circuit arrangement.

The invention provides an electrical circuit unit as set forth in the opening paragraph characterised in that the circuit unit further includes an address generator, means for modifying the state of the address generator in response to clock pulses applied to the unit or generated within the unit as a result of signals applied to the unit, and means for inhibiting the modication of the state of the address generator in response to a further signal applied to the unit.

The inclusion of an address generator within the circuit unit enables each circuit unit of a given type to be manufactured in identical form without requiring additional pins for setting the address apart from that needed to apply the signal to inhibit address modification and possibly one for the clock signal if the circuit unit does not require a system clock for other purposes.

This is particularly advantageous when the circuit units comprise integrated or hybrid circuits because of the significantly increased manufacturing cost of each additional pin but is also advantageous when the circuit unit comprises one or more printed circuit boards since the number of edge connector terminals is frequently a limiting factor in the complexity of circuits which can be accommodated on a single printed circuit board. Further in a given system all the printed circuit board terminals may be allocated to system functions by a standard bus specification, for example the VIVIE Bus. Details of the VIVIE Bus have been published by Mostek Corporation in the VME

Bus Technical Specification, the contents of which are hereby incorporated by reference.

Each circuit unit may comprise an address generation input an address generation output, a clock signal input, and means for generating an inhibit signal on the address generation output on the next clock pulse after the application of an inhibit signal to the address generation input. The means for generating an inhibit signal on the address generation output may comprise a clocked bistable circuit having an input connected to the address generation input, an output connected to the address generation output, and a clock input connected to the clock signal input.

The circuit unit may include means for enabling the address generation input and/or output to be used for other circuit functions after the address has been generated. This further reduces the number of external termi- nals required by the circuit unit. Examples of other system functions where daisy chained lines are already used are the interrupt priority lines 1ACKIN and IACKOUT in the VME Bus and IEI and IEO in the Z80 microcomputer system.

2 GB2156556A 2 The circuit unit may includes means for changing the address generated by the address generator in response to appropriate signals applied to the circuit unit. Thus having set up an initial addressing scheme this may subsequently be altered. This may be advantageous in systems such as 12 C Bus where the priority given to a given circuit unit depends on its address. By arranging for the address to be alterable the priority given to a particular circuit unit can be changed at will and does not depend on its physical position within the system.

The invention further provides a circuit ar- rangement comprising a plurality of circuit units each of which includes means for recognising an address signal applied thereto characterised in that each circuit unit includes an address generator, means for modifying the state of the address generator in response to clock pulses applied to the unit or generated within the unit and applied to the address generator as a result of a signal or signals applied to the unit, and means for inhibiting the modification of the state of the address generator in response to a signal generated by the circuit arrangement and applied to each unit in turn.

Each circuit unit may comprise an address generation input, an address generation output, a clock signal input, and means for generating an inhibit signal on the address generation output on the next clock signal after the application of an inhibit signal to the address generation input.

The means for generating an inhibit signal on the address generation output may cornprise a clocked bistable circuit having an input connected to the address generation input, an output connected to the address generation output, and a clock input connected to the clock signal input.

The units may be arranged in sequence with the address generation output of one unit connected to the address generation input of 110 the next unit, the address generation input of the first unit being connected to a reference potential source.

In this arrangement the circuit units may be connected in a chain with the signal on the 115 address generation input of the first unit in the chain being applied to each succeeding link in the chain at clock pulse intervals thus enabling each unit to count one more clock pulse than the preceding unit in the chain and 120 automatically allocating consecutive addresses to each unit along the chain. It should be noted that since the links between the units will normally be conductive tracks on a printed circuit board or wire links between 125 printed circuit boards successive units along the chain need not be physically adjacent to each other. The links between the units can be arranged to give any of the units an arbitary place along the chain. This may be important when the circuit arrangement is formed from integrated circuits connected to an 12 C bus where the priority of a particular circuit depends on its address. The 12 C bus is described in, for example Electronic Components and Applications, Volume 5, No. 1, November 1982, pages 19 and 20 and European Patent Application No. 0051332A.

Means for monitoring the state of the ad- dress generation output of the last circuit unit in the sequence may be provided. This enables detection of when all the circuit units have generated their own addresses or of a fault in one of the units or in the connection between two or more of the units which prevents the inhibiting signal from being propagated along the chain. Further, if the circuit units include means for enabling the address generation input and/or output to be used for other circuit functions after the addresses have been generated the monitoring means may cause a signal to be presented to the circuit units to cause them to change the function of the address generation input and/or output.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:- Figure 1 shows in block schematic form a first embodiment of a circuit arrangement according to the invention, Figure 2 shows in block schematic form a second embodiment of a circuit arrangement according to the invention, Figure 3 shows in block schematic form a third embodiment of a circuit arrangement according to the invention, Figure 4 shows a first embodiment of an electrical circuit unit according to the inven- tion which is suitable for use in the circuit arrangement shown in Figs. 1, 2 or 3, and Figure 5 shows a second embodiment of an electrical circuit unit according to the invention which is suitable for use in the circuit arrangement s6wn in Figs. 1, 2 or 3.

Fig. 1 shows a system comprising a plurality of circuit units 1 - 1 to 1 n each having an input Al and an output AO, the units being arranged in sequence such that the AO output of each is connected to the A[ input of the succeeding unit. The circuit unit may take many forms, for example individual integrated circuits, complete printed circuit boards, or computer terminals. The A[ input of the first unit 1 - 1 is connected to an input terminal 10 while the AO output of the last unit 1-n is connected to an output terminal 11. A termirfal 12 to which, in operation, a clock signal is connected is connected to a clock input of each of the units 1 1 to 1 -n. Each unit 1 - 1 to 1-n includes an address generator, the state of which is modified in response to the clock signal until the signal at its Al input is at a logical '1' and each unit is arranged to gener- ate a logical '1' at its output AO on the clock GB 2 156 556A 3 pulse after a logical 1' appears at its AI input. A simple way to modify the state of the address generator in response to the clock signal is to form the address generator as a counting circuit and cause it to count applied clock pulses. Thus in this case the address will be incremented by each applied clock pulse. However the state of the address generator may be modified in any arbitary manner on the occurence of each clock pulse. For example, the address generator could be formed as a read only memory with the clock pulses counting through memory addresses so that the contents of any memory location can be used as the circuit unit address. Thus, in the case where the address generators cornprise counting circuits to generate addresses for each of the units 1 - 1 to 1 -n a logical '1 ' is applied to terminal 10. On the next clock pulse this logical '1' appears at the output AO 85 of unit 1 - 1. The address generators of units 1 -2 to 1 -n are incremented but that of unit 1 - 1 is not since it has a logical 1 ' on its AI input. On the following clock pulse a logical 1' appears at the output AO of unit 1 -2 and the address generators of units 1 -3 to 1 -n are again incremented but those of units 1 -2 are not since both units have a logical '1' on their A1 inputs. This process is repeated until all the units 1 - 1 to 1 -n have a 95 logical 1' on their AI inputs and consequently the units 1 - 1 to 1 -n are set to have incremen tally increasing addresses along the length of the chain the actual address depending only on the position of the unit along the chain.

In order to detect that all the addresses have been set up the state of the terminal 11, which is connected to the AO output of unit 1 -n, may be monitored to determine when it changes to a logical 1' by means of a moni105 toring unit 13. The unit 13 may include an audible or visible warning device, such as a lamp, which may indicate when the state of terminal 11 is at a logical '0' or which may be operated when the state of terminal 11 goes to a logical 1' to indicate that the address setting up procedure has been com pleted. The unit 13 may also or alternatively produce an output signal which may be fed to a system controller to indicate that the ad dress generation phase has been completed and which may be applied directly or via a system controller to the circuit units. This signal may be effective to cause the AI and AO terminals of the circuit units to be discon- 120 nected from the address generator and be connected to other functional circuits within the circuit units, for example interrupt request ers/ controllers. Alternatively the number of clock pulses applied may be counted to en sure that sufficient time has elapsed to enable all the addresses to be generated. If the alternative method is used however faulty units would not be detected and if the chain is broken some units will not generate their own addresses.

Fig. 2 shows a circuit arrangement in which circuit units 20-1 to 20-3, 30-1 to 30-4, 40-1 and 40-2 are arranged in three bran- ches. The circuit arrangement has an input 110 to which in order to generate addresses for the circuit units a signal is applied and an input 112 via which a clock signal is applied to each of the circuit units. In a similar manner to that described with respect to Fig. 1 when a logical 1' is applied to the AI input of circuit unit 30-1 the clock signal is inhibited from incrementing the address generator in circuit unit 30-1 but the address genera- tors in all the other circuit units are incremented and at the same time the logical '1' on the AI input of unit 30-1 is transferred to its AO output. On the next clock pulse the address generators, of circuit units 20-1, 30-2 and 40-1 are also inhibited and a logical '1' is transferred to their AO outputs while the address generators of the other circuit units are once again incremented. This process is continued until all the units have set up their addresses i.e. a logical '1' appears on output terminals 113, 114 and 115.

A construction similar to that shown in Fig. 2 may be useful when each unit has an address comprising a fixed part which is related to the unit type and a variable part which defines the unit number within the unit type. Thus, for example the units 20-1 to 20-3 may be RAMs, the units 301 to 30-4 ROMs and the units 40-1 and 40-2 display drivers.

Fig. 3 shows an alternative embodiment in which the circuit units 501 to 50-n are not connected in a daisy chain but have their AI inputs connected to the outputs of a control circuit 51. The control circuit may be, for example, a shift register or a read only memory (ROM) or may be a microprocessor controlled circuit. A clock signal is applied to terminal 52 and the address generators within the circuit units 50-1 to 50-n are incremented so long as their AI inputs remain at a logical '0'. The clock pulses also cycle the control circuit 51 so that the state of the AI inputs of the individual circuit units can be appropriately set in synchronism with the clock pulses. Since in this embodiment the address generator control signal is not passed from unit to unit the AO output is not required.

In some circumstances it may be desired to modify the addresses of the circuit units and the arrangement of Fig. 3 may be used for this purpose if the address generators are modified so that they can be reset other than by switching off the power. This could be achieved by providing a further input on the circuit units to which a signal may be applied to reset the counting circuit 107 and bistable 103. Alternatively the power may be switched off when address re-allocation is to be made.

4 GB 2 156 556A 4 Fig. 4 shows a circuit diagram of a circuit unit 1 -n according to the invention which is suitable for inclusion in the arrangements of Figs. 1, 2 or 3. The circuit unit has a first terminal 100 which corresponds to the A] input of the units of Fig. 1, a second terminal 10 1 which corresponds to the clock input of the units of Fig. 1, and a third terminal 102 which corresponds to the AO output of the units of Fig. 1. The terminal 10 1 is connected to the D input of a D- type bistable circuit 103 and via an inverter 104 to a first input of an AND gate 105. The terminal 10 1 is connected to the clock input of the D- type bistable circuit 103 and to a second input of the AND gate 105. A switch-on reset circuit 106, which generates a reset signal of a desired duration when power is first applied, is connected to reset inputs of the D-type bistable 103 and counting circuit 107. The output of AND gate 105 is connected to a clock input of the counting circuit 107 and the G output of the D-type bistable 103 is connected to terminal 102.

When power is applied to the arrangement the circuit 106 generates a pulse which resets the D-type bistable 103 so that its (1 output is at a logical '0' and resets the counting circuit to an initial state which may be, but is not necessarily, all zeros. If the signal at terminal 100 is at a logical '0' and clock pulses are applied to terminal 10 1 the counting circuit 107 will be incremented by each clock pulse and the D-type bistable 103 will remain reset and therefore a logical '0' will remain on terminal 102. When the signal on terminal 100 goes to a logical '1' the AND gate 105 will be blocked and no clock pulses will be applied to the counting circuit 107 and thus it will no longer be incremented. Further the D- 105 type bistable 103 will change state on the occurrence of the first clock pulse after the logical '1' appears on input 100 thus causing a logical '1' to appear on output 102. Conse- quently by connecting the address generators in a chain they can be made to produce incrementally increasing addresses along the length of the chain. The counting circuit 107 which may take the form of a binary counter, or could, for example be a shift register determines the address of its circuit unit by the state of its outputs and the circuit unit contains means for comparing incoming addresses with the counting circuit outputs. The incoming address may be in serial or parallel form depending on the system design and the circuit until will contain appropriate address decoding circuitry.

As shown in Fig. 4 the circuit unit 1 -n is arranged to receive and decode addresses present in parallel form on inputs 120-1 to 1 20-n. These inputs are connected via an n bit highway 123 to a comparator 122. The outputs of the counting circuit 107 are ap- plied via a further n bit highway 121 to the comparator 122. When the applied address and the address contained in the counting circuit 107 correspond an output is generated on line 124 and fed to the functional section 125 of the circuit unit.

Various other arrangements for receiving and decoding addresses are possible and would be readily apparent to one skilled in the art, for example the addresses may be re- ceived serially over a single line and applied to a serial/parallel converter such as a series in-parallel out shift register. Such an arrangement reduces the number of addressing pins required but increases the time necessary to receive and recognise an address.

The clock input 101 may serve a dual purpose in that a system clock may be necessary for the operation of the functional part 125 of the circuit unit and in that case will not require an increase in the number of input terminals needed by the circuit unit. Further the circuit unit may include its own internal clock generator and an output of this clock generator may be used to increment the ad- dress generator provided that the clock generators of all the circuit units are synchronised.

The counting circuit 107 may be any circuit which is capable of stepping through a number of states in response to a clock signal and could for example, be a read only memory whose memory locations are addressed in turn by means of the clock pulses. Thus non sequential addresses could be generated in a simple manner.

The A 1 input 100 and AO output 102 could be dual purpose inputs/outputs. Thus, if the circuit units form part of a computer system (micro, mini, or main frame) interrupt lines and/or bus priority lines could be daisy chained in order to initially generate the cir cuit unit addresses and then returned to their other function by incorporating appropriate logic circuitry within the circuit units and central processor. It is, of course, necessary in that case to ensure that the address, once set up, is retained by the circuit unit until any possible instruction to alter the address is generated within the arrangement.

The circuit unit 200 shown in Fig. 5 in- cludes means for enabling dual use of the Al and AO pins and for changing the address of the circuit unit after the initial address has been set. A terminal 201 forms the Al input and a terminal 202 forms the AO output. The terminal 201 is connected to the pole of a changeover switch 203 while the terminal 202 is connected to the pole of a changeover switch 204. A terminal 205 is connected to a control input of both changeover switches 203 and 204. A first contact of the changeover switch 203 is connected to the D-input of a D-type bistable circuit 206 and to the input of an inverter 207 while a second contact of the changeover switch 203 is con- nected to an input of an interrupt control GB 2 156 556A 5 circuit 208. The output of the interrupt con trol circuit 208 is connected to a second contact of the changeover switch 204 while the G output of the D-type bistable circuit 206 is connected to a first contact of the changeover switch 204 and is connected to a first contact of the changeover switch 204 and to a first input of an AND gate 209 via an inverter 210. A terminal 210 is connected to a second input of the AND gate 209 while 75 the output of the AND gate 209 is connected to a first input of an AND gate 211 and the clock input of the D-type bistable circuit 206.

The output of the inverter 207 is connected to a second input of the AND gate 211 while the 80 output of AND gate 211 is connected to a clock input of a counting circuit 212. A terminal 213 is connected to reset inputs of the D-type bistable circuit 206 and the count ing circuit 212. The counting circuit 212 also 85 has inputs to which a data highway 214 is connected, the data highway 214 also being connected to the functional portion 215 of the circuit unit 200. A control line 216 is also connected between the counting circuit 212 90 and the functional portion 215. The outputs of the counting circuit 212 are connected to a first set of inputs of a comparator 217 while terminals 220-1 to 220-n are connected to a second set of inputs of the comparator 217 while the comparator output is fed via a line 218 to the functional portion 215. Further input terminals 221 -1 22 1 -n and output terminals 222-1 to 222-n are connected to the functional portion 215.

In operation an initialisation signal is applied to terminal 213 to set bistable circuit 206 to the state where its Q output is at a logical '0' and to set the counting circuit to a desired initial state. This signal may also be applied to the switching circuits 203 and 204 to cause them to adopt the state shown in the drawing instead of or as well as the terminal 205. Alternatively the initialisation signal may be generated within the circuit unit when power is first supplied. A system clock signal is fed via terminal 210 to one input of the AND gate 209 and its passed through the gate until the bistable 206 changes state. As with the circuit unit shown in Fig. 4 the 115 counting circuit 212 will be incremented by the clock pulses until a logical '1' appears on terminal 20 1. When this occurs the gate 211 no longer passes clock pulses to the counting circuit 212 and the next clock pulse causes the bistable 206 to change state after which no further clock pulses pass through the AND gate 209 and a logical '1' is transferred to the AO output 202. Thus far the operation of the address generation circuitry is identical to that shown in Fig. 2 apart from the feedback from the Q output of bistable 206 to the clock input the purpose of which will be described hereinafter.

When the address of all the circuit units 130 have been set up a signal on terminal 205, which may, for example, be generated by the monitoring unit 13 of, Fig. 1, causes the switches 203 and 204 to change state so that terminals 201 and 202 may be used for other purposes, for example an interrupt daisy chain. When this occurs the logical '1' may be removed from the D input of the bistable circuit 206 but the bistable circuit 206 is prevented from changing state since the logical '1' on the Q output which is fed via the inverter 210 to the AND gate 209 prevents clock pulses from being fed to its clock input.

The state of outputs of the counting circuit 212 is compared with that of addressing signals on terminals 220-1 to 220-n and if correspondence is detected an output is applied on line 218 to the functional portion 215. This then enables the functional portion to receive information from or transmit information to the rest of the system via the terminals 221-n to 221-n and 222-1 to 222n. These terminals may be devoted exclusively to input or output functions or may be bidirectional. The construction of the functional portion is not relevant to the invention apart from the possibility of subsequent address modification.

Address modification may be achieved as follows. If the counting circuit is formed by presettable binary or decade counters, such as the 74196 or 74197 TTL integrated circuits, the initial address may be allocated as described and subsequently modified by apply- ing signals to the presetting inputs. Thus the functional portion 215 may receive an instruction from a system controller and in response thereto put data onto the highway 214 which is fed to the presetting inputs of the counters under the control of a signal on line 216 which is applied to the parallel load pin of the counters.

Various modifications to the circuit unit shown in Fig. 5 would be readily apparent to one skilled in the art. For example, the changeover switches 203 and 204 may be set to the state shown by the initialisation signal and changed over after a given number of clock pulses determined by a counter. The addresses may be applied to the circuit unit serially over a single line in which case the comparator may compare the incoming address with that stored on a bit by bit basis as the address arrives or it may be fed into a series to parallel converter. Any or all of the possibilities discussed with reference to Fig. 4 are equally applicable to the embodiment of Fig. 5 and vice versa and both embodiments may be used in the arrangements of Figs. 1 and 2 and with appropriate modifications in that of Fig. 3.

Claims

1. An electrical circuit unit which includes means for recognising an address signal ap- 6 GB2156556A 6 plied thereto characterised in that the circuit unit further includes an address generator, means for modifying the state of the address generator in response to clock pulses applied to the unit or generated within the unit and applied to the address generator as a result of a signal or signals applied to the unit, and means for inhibiting the modification of the state of the address generator in response to a further signal applied to the unit.

2. A circuit unit as claimed in Claim 1, characterised in that the circuit unit comprises an address generation input, an address gen eration output, a clock signal input, and means for generating an inhibit signal on the 80 address generation output on the next clock signal after the application of an inhibit signal to the address generation input.

3. A circuit unit as claimed in Claim 2, characterised in that the means for generating an inhibit signal on the address generation output comprises a clocked bistable circuit having an input connected to the address generation input, an output connected to the address generation output, and a clock input connected to the clock signal input.

4. A circuit unit as claimed in any preced ing claim, in which the address generator comprises a counting circuit driven by said clock signal.

5. A circuit unit as claimed in any preced ing claim in which the address generator is incremented by one in response to each clock pulse.

6. A circuit unit as claimed in Claim 2, comprising means for enabling the address generation input and/or address generation output to be used for other circuit functions once the address has been generated.

7. A circuit unit as claimed in any preced ing claim, comprising means for changing the address generated by the address generator in response to appropriate signals applied to the circuit unit.

8. An electrical circuit unit including an 110 address generator substantially as described with reference to Fig. 4 or to Fig. 5 of the accompanying drawings.

9. An electrical circuit unit as claimed in any preceding claim in which the circuit unit comprises an integrated circuit.

10. An electrical circuit arrangement comprising a plurality of circuit units each of which includes means for recognising an ad- dress signal applied thereto characterised in that each circuit unit includes an address generator, means for incrementing the address generator in response to clock pulses applied to the unit or generated within the unit and applied to the address generator as a result of a signal or signals applied to the unit, and means for inhibiting the incrementing of the address generator in response to a signal generated by the circuit arrangement and applied to each unit in turn.

10. A circuit arrangement as claimed in Claim 9, characterised in that each circuit unit comprises an address generation input, an address generation output, a clock signal in- put, and means for generating an inhibit signal on the address generation output on the next clock signal after the application of an inhibit signal to the address generation input.

11. A circuit arrangement as claimed in Claim 10, characterised in that the means for generating an inhibit signal on the address generation output comprises a clocked bistable circuit having an input connected to the address generation input, an output connected to the address generation output, and a clock input connected to the clock signal input.

12. A circuit arrangement as claimed in Claim 10 or Claim 11, characterised in that the units are arranged in sequence with the address generation output of one unit connected to the address generation input of the next unit, the address generation input of the first unit being connected to a reference po- go tential source.

13. A circuit arrangement as claimed in Claim 12, characterised by means for monitor ing the state of the address generation output of the last unit in the sequence.

14. A circuit arrangement as claimed in any of Claims 10 to 13 in which the address generation output of one unit is connected to the address generation input of a plurality of further units.

15. A circuit arrangement as claimed in Claim 13, comprising circuit units as claimed in Claim 6, in which said means for enabling the address generation input and/or output terminals to be used for other purposes is operable in response to a signal produced by said monitoring means.

16. A circuit arrangement comprising a plurality of circuit units substantially as described herein with reference to Figs. 1, 2 or 3 or to Figs. 1, 2 or 3 and 4 and/or 5 of the accompanying drawings.

Printed in the United Kingdom for Her Majesty's Stationery Office. Dd 8818935, 1985, 4235. Published at The Patent Office. 25 Southampton Buildings, London. WC2A l AY. from which copies may be obtained.