GB2156175A - Signal processing circuits - Google Patents

Abstract

A processing circuit (e.g. for audio processing) comprising four transistors (Q1-Q4) forming a log amplifier (A1, Q1, Q3) and an antilog amplifier (A2, Q2, Q4) has its bias current set by an FET (Q5). The base voltage of the FET is set by the output of an amplifier/rectifier (A3) monitoring the input signal (on A3). The base voltages of the output stage transistors (Q2, Q4) can be derived from the output of the antilog amplifier (via VR4, VR3, R14, R15). The base voltages of the input stage transistors can be derived from the output of the antilog amplifier (via C2, R17, VR2, R12, R13). <IMAGE>

Description

SPECIFICATION Improvements to signal processing circuits This invention relates to an improved method of setting up the bias point and linearising the transfer characteristic of log-antilog types of four quadrant multipliers usually although not exclusively used as voltage controlled amplifiers.

The invention has been developed to facilitate the implementation and production of such circuits in the field ofthe control of audio signals although the techniques described have applications in all fields of electronic analogue multiplication of one function by another, particularly where high accuracy of signal processing and low introduced noise are required.

Important embodiments of the invention relate to signal processing circuits in which an array offour transistors are arranged in the feedback loops oftwo operational amplifiers so that a first stage in the circuit constitutes a logarithmic amplifier and a second stage in the circuit constitutes an antilogarithmic amplifier as is described in US-A-3,714,462.

The invention pertains to a number of improve mentswhich are applicable to circuits ofthe general kind disclosed in US-A-3,714,462, these improvements relating, in particular, to the setting and adjusting of the static and dynamic characteristics of the processing circuit.

Referring to the accompanying drawing which illustrates the features ofthe invention, the circuitry around an operational amplifierAi,which includes the transistors Q1 & 03, constitutes a logarithmic amplifier which adjusts the feedback applied to the inverting input of the ampliferA1,via a variable resistorVR1, Q1 and Q3, that the current into this input-provided by a signal input V3 acting through a resistor R5-produces currents at points N1 and N2 which are opposing half wavers and have a logarithmic relationship to the input voltage in the manner known in the art.

The points NI and N2 can be thought of as forming the in puts to a second operational amplifierA2via a further pair of transistors Q2 and Q4 and the arrangement of Q2 and 04 and a resistor R4 constitutes an antilogarithmic amplifier which takes the opposing half waves present at N 1 and N2 and combines them as an input to the ampl if ier A2 imposing on them an antilogarith mic transfer characteristic.

As is known in the art, control currents from input voltagesV1 and via resistors R1 and R9, respectively, can be applied tithe bases ofthefour transistors 01-Q4 in such manner asto add or subtract linear coefficients to the logarithm and antilogarithm ofthe input signal V3, such that an output voltage V6 is proportional to the signal V3 multiplied by a factor proportional to V1 and V2.

Where the voltage V3 is an audio signal, the gain or loss of the output voltage V6 with respect to the input voltage, can be controlled by the sig nals V1 and V2 injected into R1 and R9.

In order to prevent the input stage from taking the logarithm of zero or a negativequantitywhere one or other of the transistors would be cut off entirely, a static bias current from a curren source 11 is passed via the point N1 to the point N2 and into a current sink 12. The value of this current is chosen to be great enough to prevent any devicefrom switching off when subjected to the largest expected input signal when this is also multiplied by the largest expected control signal.

The sources Ii and 12 can be made fixed tf proportional to the junction temperatures of the closely linked transistor elements 01-04 if large variations in ambient temperature may occur. Howev er, it is found that the noise on V6 at the output terminal when the output pair (Q4 & 02) are not cut off by the control signal, is also proportional to the bias current. This yields a fixed ratio between the ultimate lytolerable audio signal for a known distortion figure and the remnant output noise which cannot be better than about 90 dB for distortion figures appropriate for studio equipment.

One solution to this problem is shown in the drawing, and involves including a circuit branch which includes resistors R6 and R8, an FET OS and an amplifier/rectifier unit A3. The components in this circuit branch are selected to provide a current from il or 12 which is great enough forthe maximum throughput signal expected but steals some ofthis, via R6and Q5 under manual control byvaryingthe bias voltage on the gate ofthe FET Q5.

The manual control ofthe bias can be linked to a prior stage (not shown) whose expected maximum signal is set by some switching or variable control which also acts on a voltage V4 in sympathy.

Alternatively, the voltage V4 can be setforthe required signal to noise ratio for maximum signal and adjusted by the unit A3 which sensesthe audio input and/or output levels and adjusts the resistance ofthe transistor Q5 in sympathy, by varying the gate channel voltage by means ofthe outputvoltage V5 of the unitA3.

A3 constitutes an amplifier-rectifier which produces a a DC output proportional to the signal level at its inputs. Its attack and recovery times are made appropriate to the type ofsignal carried by the main circuit (V3 and/orV6) and are typically 101lS and 1S respectively, for normal audio duty.

Thethreshold where the voltage V5 starts to swing negative is adjusted to be about 6dB lowerthan the point at which the inputvoltageV3and/orthe output voltage V6 reach the maximum signal appropriate to the amount of bias current leftoverfrom that passing through the FET Q5. The gain of the amplifier part of the unit A3 can be adjusted so thatthe increase in the effective current passing through the transistors Q1-04 exactly matches that required by the increased values of input signal V3 or outputsignal V6.

Owing to the factthatthe increased output signal V6 usually masks the noise atthe output, it is notfound necessary to make the matching of the required bias to signal level particularly accurate. The only important parameter being that the rate of change of bias is equaj4ciorslightly greaterthan the change in signal th roughput so that the four transistors Q1-04 are never starved of bias at high signal levels.

Using sJJch a-technique in one implementation, the imprnvementin noise overthe 90dB cited above is 10 dB. In Thermass consideration with variable bias: When:tbe4hermal equilibrium of the two sides of the device (i.e. Q1/03 and 02/Q4) is upset, current whichcannot flow from Q1's collector into 03's collector for example, must then form an offset current which will cause the output ofthe amplifier Al t-fall.so thatthe transistor 03 is turned further on to compensate.

Thearn:e problem will occur if there is an imbalance between'thetsansistors 02 and 04which wili cause the outputofthe amplifierA2 to rise orfall to take up the oftset current in its feedback resistor R4. All such offsets will modulated by the control current and prnvidea;:spurious outputfrom the amplifierA2 which will be an image ofthe control waveform.Ifthe control signalis moved quickly aswhen abruptly muting the audio path through the VCA, a very audible click or thump wiltbeproduced;at the output a The Lowertheactual turrentfiowing between the --p6jnts-NI-and-N2,the lowertheactual offsetcurrent will be indirect relationship and hence the lower the -spur'ouscontml inducedMoutputfeedthrough will be.

A large-valueofV3 anci/or V6 which has caused the unit A3 to setthe bias at ahigh level will still result in -substantia,contrnl waveform feedth rough but again the effect will be maskedby the sidebands produced by the sudden interruptuion ofthe signal.

For critical applications on intermittent percussive sounds, where the recovery time constant ofthe unit - A3 would not allow the movement to be masked, this time.constantwould be tied to the control input waveform so that any sudden control movement, which wolltd allow the decaying high bias to be modulated, would first reduce the bias current a few hundred microseconds before the control waveform itself began tract.

Setup Considerations: In prior.art circuits, the balance between the NPN and PNP paths has been done by making R2 and/or R10 variable aswell as utilising the balancing effect of VR1. The known technique has been to balance the two sideswhen no control current is present using variable R2 and/or R1 Gand then to balance again with substantial control currents from V1 and V2 using the variable-resistor VR 1. Unfortunately, the two settings interactconsiderably and the procedure is tedious.

The circuit shown in thedrawing represents a substantial improvement because in this case, the balance adjustmentwith no control signal is accom plishedbyfeeding back some ofthe output signal to the output pair bases and balancing this feed with a variable resistorVR3. Sincethis balancing signal is reduced in sympathy with the outputfrom whence it is taken, the setting ofthe variable resistorVR1, when strongly attenuating control is present, is largely independentoFthesetting ofthevariable resistorVR3.

Using this balancing method has another benefit in that itallowsforthe simpie implementation of high frequency balancing via the time constant dominated by C2 and R17 using a further variable resistorVR2. In one embodiment of the circuit the time constant (C2, R17) is chosen to be between 1 and 2 uS depending on the hfe and fT of transistor Q1 -Q4.

High frequency balance has been found to be important because the most serious distortion pro ductsgeneratedinVCA'swhenoperating belowthe signal level which would cause one or other side to saturate or cut off, are at high frequencies where the imbalance in hfe between the sides gives a strongly rising frequency/distortion curve. The effect of the circuit arrangement described improves the high signal level distortion at 20Khz, in one impiemention, by 12dB.

It has also been found that where the VCA does not have to produce gain, the extreme HF balance should be mostly confined to the antilog pair and thus the presence of a capacitorC1 between the control input resistors Ri and R9 is important. The optimum input stagetime constant dominated byC1 and R2/R10has been found in one implementation ofthe principle to be some 10 times smallerthan C2/R17.

The capacitor C1 has a further beneficial effect in that it removes some high frequency noise present in the control current. Owing to inevitable small differences in stray capacitance and inductance between the two sides of the array, high frequency noise on the control lines has a strong tendancyto feedthroughto the outputV6.

Cross coupling ofthe input bases has been found to be very much more effective at reducing such noise feadthrough than simple decoupling of each base to ground. This technique is particularly important when the control voltage V1 and V2 are derived from high speed switching components (such as computer drivenA:D converters) which have a small amount of superimposed clock waveform(s) riding on a mean DC level.

US-A-3, 714,462 discloses a VCA utilising four transistors in logarithmic and antilogarithmic amplifier arrays which although having a low signal to noise ratio has a transfer characteristic which is somewhat lacking in linearity.

Onefeature ofthis invention relates to an improved VCAwhich although still operating with a very good signal to noise ratio at low signal inputs, has a more lineartransfer characteristic than prior artVCA's having log-antilog types offour quadrant multipliers.

The signal to noise ratio at high signal input levels is typically lower as atrade-inforthe improved linearity, butthis is an acceptable price to pay in the face of a strong input signal. This feature ofthe invention can broadly be identified with the components A3, R8, OS and R6 in the drawing.

Afurtherfeature ofthe invention resides in concentrating the HF balance to the antilog pair of the quadrant array and this feature can be broadly identifed with the inclusion ofthe capacitor Ci.

Third and fourth features ofthe invention resides in the improved ways of effecting balance adjustments possible with the circuit illustrated. At high frequencies this improvementis identified with the components VR2, R17 and C2. When strongly attenuating control is present it is the components VR3, VR4and R16 which are responsible for the improvement.

Although all four of the above-noted features are shown usedtogether in the illustrated circuit, it is not ruled outthatthe advantage afforded by each could justify its separate use so the invention should be seen to include one, two orthree of these features omitted.

Claims (1)

1. A method of setting up the bias point and linearising the transfer characteristic of a signal processing circuit in which an array offourtransistors are arranged inthefeedback loops of two operational amplifiers, a first stage of the circuitconstituting a logarithmic amplifier and a second stage in the circuit constituting an antilog amplifier whose input is connected to the output of the first stage, and with a bias point setting means connected across the output" input ofthefirst/second stage to feed a bias current between said output/input which is great enough to prevent any of the fourtransistors being switched off during use ofthe circuit, wherein the bias point setting means includes means to change the bias current during operation of the circuit.

2. A method as claimed in claim 1, in which the bias point setting means includes bias current generating means, the output of the generating means being proportional to the junction temperatures of the array of transistors.

3. A method as claimed in claim 1 or claim 2, in which the bias point setting means includes an amplifier/rectifier unit monitoring the input signal fed tothefirststageofthecircuit.

4. A method as claimed in claim 3, in which the recovery and attacktimesoftheamplifier/rectifierunit are 1 and 10-5 seconds, respectively.

5. A method as claimed in any preceding claim, in which some part of the output signal from the second stage is fed back to the bases of the transistors in the second stage.

6. A method as claimed in any preceding claim, in which some part of the output signal from the circuit is fed back, via a capacitor, to the bases ofthe transistors of the first stage.

7. A log/antilog signal processing circuit comprising a first stage constituting a logarithmic amplifier having two transistors in the feedback loop of a first operation amplifier, the output of the first stage being connected to the input of a second stage constituting an antilogarthmic amplifier having twofurthertransis- tors in the feedback loop of a second operational amplifier, and a bias point setting means connected across said conjoined output/input, wherein the bias point setting means includes bias current supply means, and a bias current control means in the form of afield effecttransistor(FET) whose voltage is controlled buy a due signal derived from the input signal to the processing circuit.

8. A circuit as claimed in claim 7, in which the FET is in parallel with a potentiometer, the slider of which receives the outputfrom the first operational amplifier.

9. A circuit as claimed in claim 8, in which the base of the FET receives voltage from an amplifier/rectifier whose input terminals bridge between the input and output of the circuit.

10. A circuit as claimed in any of claims 7 to 9, in which the base potential ofthe two transistors inthe second stage is derived from the output of the second stage via a variable resistor.

11. Acircuitas claimed in anyofclaims7to 10, in which the base potential of the two transistors in the first stage is derived from the output ofthesecond state via avariablecapacitor.

12. A circuit as claimed in any of claims 7 to 11, in which a capacitor is connected between two control current inputs ofthecircuit, which control current inputs lead, respectively, to the base of a respective one of the two transistors in each stage.

13. Asignal processing circuit substantially as hereinbefore described with reference to, and as illustrated in, the accompanying drawing.

Amendments to the claims have been filed, and have the following effect: (a) Claim 1 above has been textually amended.

1. A method of setting up the bias point and linearising the transfer characteristic of a signal processing circuit in which an array offourtransistors are arranged in the feedback loops of two operational amplifiers, a first stage of the circuit constituting a logarithmic amplifier and a second stage in the circuit constituting an antilog amplifier whose input is connected to the output of the first stage, and with a bias point setting means connected across the output" input ofthe first/second stage to feed a bias current between said output/input which is great enough to prevent any of the four transistors being switched off during use ofthe circuit, wherein the bias point setting means includes means to change the bias current during operation of the circuit. in response to changes in the signal fed as input to the first stage.