GB2154400A - Distributed arbitration circuitry - Google Patents

Abstract

A silicon semiconductor wafer containing a plurality of silicon integrated circuits formed therein or attached thereto contains at least one data bus to which some of the circuits are connected. Each of the circuits coupled to the data bus contains an arbitration request circuit which selectively passes a signal that requests that its circuit be given access to the data bus so it can transmit information to another circuit on the wafer. In addition, each of the circuits coupled to the data bus has an arbitration circuit which detects which of any of the circuits coupled to the data bus is requesting access to the data bus and facilitates its circuit gaining access to the data bus if its circuit has a higher preselected priority than any other circuit which is simultaneously seeking access to the data bus. The distribution of the arbitration request circuits and of the arbitration circuits simplifies layout and tends to improve the speed of operation. <IMAGE>

Description

SPECIFICATION Distributed arbitration circuitry Technical Field This invention is directed to components mounted orformedinacommoncarrierandin particular to silicon integrated circuit chips formed in or attached to a silicon wafer.

Background of the Invention The need for very high speed large memory capacity computers is leading to the use of wafer scale integration which uses a single silicon wafer as the carrierfortens, or hundreds, or thousands of integrated circuits which are formed in the wafer and are separated from each other by p-n junction or dielectric isolation. Conductors formed on oroverthetop planar surface of the wafer serve to interconnect the circuits.

Anothersimilarapproach is to attach wholly formed integratedcircuitsto a semiconductorwaferandthen to interconnect the circuits with conductors. One such implementation is described in the article entitled "Wafer-Chip Assembly for Large-Scale Integration," IEEE Transactions on Electron Devices, Vol. ED-15, No.

9, September, 1968, pp. 660-663.

In most of these structures multiple integrated circuits are coupled to a common data bus with each also being coupled to common arbitration circuitry which determines which circuit gains access to the data bus iftwo or more circuits seek access at essentially the same time or within a preselected time period. One problem with the common arbitration circuitry is that it adds to the wiring complexity and therefore limits the number of circuits which can be used on or in a given semiconductorwafer and requires two interchip transactions which adversely affects speed performance.

Itwould be desirable to achieve the needed arbitration functions for multiple circuits having a common data bus without incurring the wiring and speed penalties of prior art structures.

Summary of the Invention These penalties can be avoided by using apparatus comprising: a plurality of component circuits coupled to a signal conduit path and selectively needing, in use, totransmit information onto the signal conduit path; a plurality of arbitration conduit paths; each of the component circuits being adapted to have a priority with respect to transmission of information onto the signal conduit path; each of the component circuits, except for possibly the component circuit having the lowest priority, comprising a separate one of a plurality of arbitration request circuits; each arbitration request circuit being coupled to a separate one ofthe arbitration conduit paths and being adapted to selectively allow a signal from its component circuit to reach the arbitration signal conduit path coupled thereto; each of the component ci rcuits, except for possibly the component circuit having a highest priority, comprising a separate one of a plurality of arbitration circuits; and each arbitration circuit being coupled to at least one of the arbitration conduit paths and being adapted to detect which of any of the other componentcircuitshavinga higherpriorityis requesting access to the signal conduit path and to enable its component circuitto gain access to the signal conduit path if its component circuit is requesting access to the signal conduit path and if its component circuit has a higher priority than any other component circuit which is requesting such access.

In a preferred embodiment of the invention a semiconductor wafer has a plurality of component circuits formed therein or attached thereto. The component circuits are typically silicon integrated circuits which may be denoted as chips. Some of these chips are coupled to a common data bus and at least two or more selectively need access to the data bus such that signal information can be sent from one chip to another. Each ofthe chips is adapted to have a priority with respect to transmission of information onto the data bus.The carrier and at least some of the chips are of the same material. Each of the chips which needs access to the data bus comprises an arbitration request circuit and an arbitration circuit.The arbitration request circuit selectively passes a signal from its chip that effectively requests that its chip be given access to the data bus such that its chip can transmit information overthe data bus to another chip. The arbitration circuit is adapted to detect which of any of the other chips coupled to the data bus are requesting access within a selected time period to the data bus and to facilitate its chip gaining access to the data bus if its chip has a higher priority than any other chip seeking access to the data bus during the selected time period. A plurality of arbitration conduits (condoctors) exist. Each of the arbitration request circuits, except for possibly the arbitration circuit having a lowest preselected priority, has an output terminal thereof coupled to a separate one ofthe arbitration conductors.Typically, each of the arbitration circuits, exceptfor possibly the arbitration circuit of the chip having the highest preselected priority, is coupled to some ofthe arbitration conductors.

The use of a separate self-contained arbitration request circuit and a separate self-contained arbitration circuit as part of each ofthe chips which requires selective access to a common data bus tends to reduce the interconnection wiring complexity ofthe system since there is no need for sepa rate connections of each chip to a central arbitration circuit. Thus the chips can be interconnected in a variety of different configura tions without concern asto howto couple same to a common arbitration circuit and without suffering the speed loss associated with the need to do two circuit transactions.

The component circuits (chips) which can be used can be Central Processing Units) (CPUs), Memory Management Units (MMUs), Math Acceleration Units (MAUs), Direct Memory Access controllers (DMACs), Dynamic Random Access Memories (DRAMs), Static Random Access Memories (SRAMs), Read Only Memories (ROMs), Gateways (GTWYs), or a variety of other circuits, including but not limited to analog circuits and to circuits which transmit and receive light signals.

Brief Description of the Drawings The preferred embodiment of the invention, given byway of example, will now be described with reference to the accompanying drawings, in which: FIG. 1 illustrates a silicon wafer with silicon inte grated circuits formed therein or attached thereto; and FIG. 2 illustrates circuitry of some ofthe circuits of FIG. 1.

Detailed Description Referring nowto FIG. 1, there is illustrated a system 10 comprising a wafer 12 with integrated circuits (chips) illustrated as Chip 0,Chip 1, . . . Chip 7,and Chip N and Chip N+ 1. These chips are only illustrative of some of the chips that can ormayordo exist as part of wafer 12 or are attached to wafer 12. The wafer may be denoted as a carrier and the chips may be denoted as integrated circuits, component circuits, or ICs.

Chips 0,1,... 7 are illustrated coupled to Data/ Address Bus 1 and to Data/Address Bus 2. The interaction of Chips 0, 1,... 7 7 with Data/Address Bus 2 will be discussed hereinbelow. It is not necessary for use of the present invention that Data/Address Bus 1 be in existence. Each ofthe Data/Address Buses may be referred to as a signal conduit path. Chips N and N+1 are illustrated coupled to Data/Address Bus 2 and to a Data/Address Bus M. Each of chips 0,1,... 7 contains a separate arbitration request circuit (denoted as ARC0, ARC1, . . . ARC7) and a separate arbitration circuit (denoted as AC0,AC1,... AC7).

ARCO need not exist if Chip 0 has the lowest priority of the eight chips. Each of Chips 0,1,... 7 selectively needstogain access to Data/Address Bus2suchthat signal information can besentfrom one chip to another orto some circuitry (not illustrated) coupled to Data/Address Bus 2. The ARC's and the AC's generallyworktogetherto allow only one ofthe eight chips to send (transmit) information onto data/ address bus 2 at a given time or during a given period oftime. Essentially no other arbitration request circuit or arbitration circuit is needed to perform this function. This allows for greatflexibility in arranging different chips in essentiallyanyneededconfigura- tion.

Seven Arbitration lines (conductors),A1,A2... A7, which may be referred to as Arbitration Conduit Paths, exist with ARC1,ARC2,... ARC7 being coupled to A1, A2, . . . A7, respectively. ARCO is not coupled to any of the Arbitration Conduit Paths. The AC circuits of Chips 1 through 7 have been connected to the A1 ,A2, . . . A7 lines orto a reference potential, with Chip 7 having highest priority and each preceding chip having lower priority with Chip 0 having the lowest priority. TheAC circuit of chip 0 is not connected to an arbitration line.

This means that during an access request portion of a cycle of operation of chips 0 through 7, that if chip 7 requests access to data/address bus 2, that it will be granted access during the next appropriatetransmit portion of the cycle of operation even if all otherseven chips are also seeking access. Chip 0 only gains access if none ofthe other seven chips are requesting access atthe same time or at anytime during an access request portion (selected time period) of a cycle of operation.

Each ofAC0,AC1,... AC7 has eight input terminals 0,1,2,3,4,5,6, and 7. The 1 terminal ofAC1,the 1 and 2 input terminals of AC2, the 1,2, and 3 inputterminals of AC3 (not exl;ressly illustrated), the 1,2,3 and 4 input terminals of AC4, (not expressly illustrated), the 1,2,3, 4and 5 inputterminalsofAC5,the 1,2,3,4, 5, and 6 input terminals of AC6 (not illustrated) and the 1,2,3, 4,5,6 and 7 input terminals ofAC7 are coupled to a reference voltage Vref. The 1,2,3,4,5,6, and 7 input terminals of ACO are coupled to Al through A7, respectively. The 2 through 7 input terminals ofAC1 are coupled to A2 through A7, respectively.The 3 through 7 input terminals of are coupled to AC3 through AC7, respectively. The 4th rough 7 input terminals of AC3 are coupled to A4th rough A7, respectively. The 5 through 7 inputterminals of AC4 are coupled to A5 through A7, respectively. The 6 and 7 inputterminals of AC5 are coupled to A6 and A7, respectively. The 7 input terminal of AC6 is coupled to A7.

A clock line Cl, which may be denoted as a clock conduit path, is coupled to each of ARCO through ARC2 and to inputterminals of invertercircuits IQ1, 111,... 171. The outputterminal of each of 101, Ill,... 171 is coupled to ACO, AC1,... AC7, respectively. A reset line R is illustrated coupled to each of ACO, AC1, . . . AC7. An outputterminal of each of ARCO through ARC7 is coupled to an inputterminal of inverters102,112,... 172, respectively. An output terminal of each of 102,112,... 172 is coupled to the 0 inputterminal ofAC0,AC1,... AC7, respectively.

Referring nowto FIG. 2, there is illustrated a portion of system 10 of FIG. 1 which illustrates component parts of ARC1 and AC1. Each of ARCO and ARC2 through ARC7 has essentiallythe same structure as ARC1. Each of AC0 and AC2 through AC7 has essentiallythe same structure as ARC1 comprises a gating device 01, illustrated as a field effect transistor, and a non-inverting driver circuit Dl. The gate of Q1 is coupled to Cl. Afirst output terminal of Q1 and an inputterminal of D1 are coupled to a node 14.A second output terminal of Q1 is coupled to portions of chip 1 which determine if chip 1 desires accesstodata/addressbus2.An outputterminai of D1 is coupled to Al and to an inputterminal of inverter 112. AC1 comprises an eight inputAND gate 22 having input terminals 0,1,2,3,4,5,6 and 7, a gating device 02, illustrated as a field effect transistor, and a latch circuit. The gate of 02 is coupled to an outputterminal ofinvertercircuit 1 and to a node 16. An input terminal of 111 is coupled to ClAn outputterminal of the AND gate is coupled to one output terminal of Q2 and to a node 18. A second output terminal of Q2 is coupled to an inputterminal of the latch circuit24and to a node 20.An output terminal of the latch circuit is coupled to a portion of chip 2 which enables chip 2 to send information onto data/address bus 2.

The operation of Chips 0, 1,2,3,4,5,6, and 7 is essentially as follows. At the beginning of a cycle of operation the clock signal and resetsignal both go high, a "1 ".This sets the output terminals of all the latch circuits of through AC7 all to low's, "0". At the startthe beginning of a subsequent cycle ofthe clock (i.e., the clock goes from a "O" to a "1"), reset switches from a "1 " to a "0" and each of Chips O through 7 will generate a "1 " or a "0" from its associated ARC circuit A "1" indicates that the chip generating the "1" does not need to gain access to data/address bus 2 at this time. A "0" indicates that the chip generating the "0" seeks access to data/address bus 2 at this time. Chips 0 through 7 have been, for illustrative purposes only, configured and connected suchthatthechip7hasthehighestpriority(i.e.,ifit needs access to data/address bus 2 it gains access independent of whether or not any ofthe other seven chips needs access) and chip 0 has the lowest priority (i.e., only if none of the other seven chips needs access does chip 0 gain same). The preselected priority decreases with the numerical assignmentofthe chip.

The magnitude and polarity of reference voltage Vref is selected such that it is at a logic "1" level. If chip 7 7 sends a "0" from ARC7 onto A7, then the seventh inputterminal of each of the AN D gates of ACO through AC6 receives one "0" input signal and thus the output signals of each of same are all "O's". During the second half ofthis clock cycle (i.e., the clock signal is a "0") each ofthe gating means (i.e., 02) of each of ACO through AC6 becomes enabled and the "0" atthe output terminals ofthe seven AND gates becomes inputsignalsto each oftheseven latch circuits. This causes the output of each ofthese seven latch circuits to be at a "0" level.This causes each of chips 0 through 6 to disable any information it desires to send onto data/address bus 2 from reaching data/address bus 2.

AC7 receives "1 " input signals on input terminals 1 through 7 of AC7 because same are coupled to Vref, and receives a "1" on inputterminal 0 since ARC7 is generating a "0" which is inverted by 172. The eight "1 " i n put signals to th e AN D gate of AC7 cause the outputterminal thereofto assume a "1" level. During the second part ofthe clock cycle 02 of AC7 is enabled and the "1" signal becomes an input to the latch circuit of AC7. This causes the output terminal of thins latch circuit to be set to a "1" which allows chip7 to transmit information onto data/address bus 2.

Now assume that chip 1 desires during a subse quentcycle ofthe clocktotransmitinformation onto data/address bus 2 and all chips having a higher priority do not need to so transmit information at th is time. This results in A2 through A7 being "1's" and Al being a "O". Al being a "O" will inhibit (prevent) chip 0 from gaining access to data/address bus 2 since one of the inputsto itsAND gate of ACO isa "0" and thus the AND gate ofACO has a "0" output and the corresponding latch circuit likewise will have a "0" output when the clock goes low (a "O").The 1 through 7 input terminals ofthe AND gate of AC1 are all "1's" as if the O inputterminal sinceARCi is a "l".Thiscausesthe latch circuit of AC1 to be a "1 " which in turn causes the output terminal ofthe latch circuit to be a "1". This allows chip 1 to transmit information onto data/ address bus 2. If chip 1 needs to transmit, but one or more of the chips with a higher priority also needs to so transmit, then chip 1 will not transmit because one or more ofthe 1 through 7 input terminals of its AND gate of ACl will be "O's".

Nowassumethatchip0desiresduringasubse- quent cycle of the clock to transmit information into data/address bus 2 and all other chips do not so desire.

All ofthe 1 through 7 inputterminals oftheAND gate of ACO are "1 's" and the 0 inputterminal thereof is also a "1". With all ofthe eight input terminals oftheAND gate of AC0 being "1 's",the output oftheAND gate becomes a "1" and during the next partofthe clock cycle the latch circuit associated therewtih assumes a "1" output level. This results in chip 0 transmitting information onto data/address bus 2.102 can be eliminated in some since it is not really always needed because the output terminal of the AND gate of ACO can assure a "1"whetheror notinputterminal 0 is in "1". This results in chip 0 transmitting "random data" at all times when no chip needstotransmit.Typically transmitted information contains at least one bit which indicates that same is valid. If chip 0 is transmittingwithoutthatbitthenthe information will effectively be ignored by all other chips. The leaving out of 102 allows chip 0 not to have to request access to data/address bus 2 and to yet gain same, assuming no other chip is requesting same at the same time. This saves one cycle of operation of the clock and thus enhances speed performance.

If chip O and another chip simultaneously need to transmit onto data/address bus 2 then the other chip disables ACO and it gains access to data/address bus 2.

After a chip gain access to bus 2 it will then during the first half of the next cycle of the clock transmit the information which will be received by all ofthe other chips coupled to bus 2. The transmitted information is decoded during thesecond half ofthis cycle and only one chip or several chips which are intended to be recipients ofthe information will receive and decode same. The chip(s) which receivesthetransmitted information will send back during the first half of the next clock cycle an acknowledgment signal on the ACK line(ACK) ora busy signal on the busy line (BY). If the information sending chip receives an acknowledg ment signal it will not resend the same information again. It will subsequently transmit the same information if it receives a busy signal or no return signal.

The embodiments described herein are intended to be illustrative of the general principles of the present invention. Various modifications are possible consistent with the spirit ofthe invention. For example, each ofthe 1 through 7 inputs to the AND gate of ACO through AC7 can be connected to circuitry which can be programmed and reprogrammed to couple the in put terminals to a multiple of different combinations of A1 through A7 such that the priority of any chip can be modified at anytime priortothe need to gain access to a data/address bus. ARCO through ARC7 also are coupled through programmable and reprogrammable circuitry such that same can be coupled as desired.Still further, multiple other chips on the same wafer and coupled to another data/address bus can also have distributed arbitration request circuits and arbitration circuits contained on all of the chips which selectively need access to that data/address bus. Still further, separate data/address buses can be coupled together via gating circuits. Still further, the data/ address buses can be aluminum, doped polysilicon or other conductors, or optical connections such as optical fiber, or air. Still further, the wafer and chips can be a Ill-V semiconductor compound such as, e.g., gallium arsenide and gallium arsenide indium phosphide. Still further, some of the chips may provide biasing for a bus and may not send information onto the bus. Still further, the number of chips can be essentially any numberovertwo. Still further, multicycle arbitration can be done. Still further, other types of gates could be substituted forthe AND gates if the input signals thereto are changed. Still further, the wafer, which may be referred to as a carrier, can have circuits (chips) or other components attached thereto which are not of the same material as each other or as the carrier. Still further, the component circuits can be formed in and be a partofwafer 12. Still further, each ARC could be a separate integrated circuit chip and each AC could be a separate integrated circuit chip.

Still further, an ARC and an AC could be on one common integrated circuit chip with the circuitry which would function with same being on a second chip.

Claims (21)

1. Apparatus comprising: a plurality of component circuits coupled to a signal conduit path and selectively needing, in use, to transmit information onto the signal conduit path; a plurality of arbitration conduit paths; each of the component circuits being adapted to have a priority with respect to transmission of information onto the signal conduit path; each of the component circuits, except for possibly the component circuit having the lowest priority, comprising a separate one of a plurality of arbitration request circuits; each arbitration request circuit being coupled to a separate one of the arbitration conduit paths and being adapted to selectively allow a signal from its component circuit to reach the arbitration signal conduit path coupled thereto;; each of the component circuits, except for possibly the component circuit having a highest priority, comprising a separate one of a plurality of arbitration circuits; and each arbitration circuit being coupled to at least one of th arbitration conduit paths and being adapted to detect which of any of the other component circuits having a higher priority is requesting access to the signal conduit path and to enable its component circuit to gain access to the signal conduit path if its component circuit is requesting access to the signal conduit path and if its component circuit has a higher priority than any other component circuit which is requesting such access.

2. The apparatus of claim 1 further comprising a clock conduit path coupled to each of the component circuits coupled to the signal conduit path.

3. The apparatus of claim 2 wherein: the numberofarbitration conduit paths at least equals one less than the number of component circuits which are coupled to the signal conduit path; and each arbitration circuitcomprisesa logiogateorthe equivalentthereofwhich has a number of input terminals equal to at least the number of component circuits which have higher priority.

4. The apparatus of claim 3 wherein each of the input terminals of the logic gate of each arbitration circuit is coupled to one of the arbitration conduit paths or a node which is connectable to a potential level.

5. The apparatus of claim 4wherein: each arbitration circuitfurther comprises a latch circuit and a first gating device having a control terminal and first and second outputterminals; the first outputterminal of the gating device is coupled to an outputterminal ofthe logic gate and the second outputterminal ofthe gating device is coupled to an inputterminal ofthe latch circuit; and each arbitration request circuit comprises a second gating device having a control terminal and first and second output terminals.

6. The apparatus of claim Swherein: the gate terminal of each of the second gating devices is coupled to the clock signal conduit path and the gate terminal of each ofthefirst gating devices is coupled through an inverter circuit to the clock conduit path; and thefirstoutputterminal of each of the second gating devices, except for possibly the lowest priority component circuit, is coupled to one of the arbitration conduit paths and the first output terminal of each of the second gating devices is coupled to a portion of the component circuit which determines if the component circuit desires access to the signal conduit path.

7. The apparatus of claims 1 and 6wherein a body portion of each of some of the component circuits is a semiconductor material.

8. The apparatus of claim 7whereinthesemicon- ductor material is silicon.

9. The apparatus of claim 8 wherein the silicon is single-crystal silicon.

10. The apparatus of claim 7 wherein the semicon ductormaterial is a Ill-V semiconductor compound such as, e.g., gallium arsenide and gallium arsenide indium phosphide.

11. The apparatus of claims 1 and 6 further comprising: a carrier with the plurality of component circuits being coupled thereto or being a partthereof; and a body portion of the carrier and a body portion of at least some of the component circuits being essentially of the same type of material.

12. The apparatus of claim 11 wherein the body portion of the carrier and the body portion of each of some of the component circuits are semiconductor materials.

13. The apparatus of claim 12 wherein the body portion of the carrier is silicon.

14. The apparatus of claim 13 wherein the signal conduit path is a data bus which is a conductor and the body portion of some ofthe component circuits is silicon.

15. The apparatus of claim 14wherein a body portion of the carrier and a body portion of each of some ofthe component circuits are essentially of a single-crystal silicon.

16. Theapparatusofclaim lSwhereinthecarrier and component circuits are both part of a silicon member.

17. The apparatus of claim 16 wherein the silicon member is a silicon wafer.

18. The apparatus of claim 11 wherein the carrier and the component circuits are all essentially of a Ill-V semiconductor compound such as, e.g., gallium arsenide and gallium arsenide indium phosphide.

19. The apparatus of claim 11 wherein the signal conduit path is air or an optical fiber or other optically responsive material.

20. The apparatus of claim 11 wherein the signal conduit path is a conductor such as aluminum or doped polysilicon.

21. The apparatus ofclaim 11 wherein the priority of each of the component circuits is changeable.