GB2152712A

GB2152712A - Apparatus for handling data

Info

Publication number: GB2152712A
Application number: GB08427434A
Authority: GB
Inventors: Raymond Anthony Sheehan; Conner Valentine O'reilly; Gerhardt Bakker; Robert Gerhard Richardson; Patrick Gerhard Carroll
Original assignee: NAT MICROELECT APPLIC CENT Ltd
Current assignee: NAT MICROELECT APPLIC CENT Ltd
Priority date: 1983-11-02
Filing date: 1984-10-30
Publication date: 1985-08-07
Also published as: BE900978A; GB8427434D0; IE832561L

Abstract

The apparatus comprises a plurality of data entry stations (1) with keyboards (2) through which the data is entered. The data entry stations (1) are connected in a daisy chain loop (3) into a master station (4) which directs the data into a personal computer (5). The data is processed in the computer (5) and directed to the relevant data entry stations (1) through the master station (4) and displayed on an appropriate liquid crystal display (6) connected to each data entry station (1). The data entry stations (1) and master station (4) are interfaced using a high-level data link controller, and the master station (4) is interfaced with the personal computer (5) using a serial interface link provided by an asynchronous communication interface adaptor. <IMAGE>

Description

SPECIFICATION Apparatus for handling data The present invention relates to apparatus for handling data from a plurality of sources and for feeding the data to a computer means and in particular it relates to apparatus comprising a plurality of stations for receiving the information for subsequent direction to a computer. Preferably, though not necessarily, the apparatus is for handling production data and or quality control data.

According to the invention there is provided apparatus for handling data from plurality of sources for feeding to a computer means, the apparatus comprising a plurality of data entry stations to receive the data from each source and a master station to direct the data from the data entry stations to the computer means, each data entry station comprising: interface means for interfacing with the keyboard to receive the data.

interface means to interface the data entry station with the master station to direct the data to the master station and receive data from the master station, interface means to interface with a liquid crystal display for displaying data being directed to or received from the computer means, control means to control the data entry station, and memory means to store data in the data entry station, the master station comprising; interface means for interfacing with each data entry station for receiving data from the data entry station and directing data to the data entry station, interface means for interfacing with the computer means to direct data to the computer means and to receive data from the computer means.

control means to control the master station, and memory means to store data in the master station.

Wherein the interface means at each data entry station and master station for interfacing respectively with the other station comprises a high-level data link controller (HDLC) provided in each data entry station and the master station, the stations being connected in a loop, and the interface means in the master entry station for interfacing with the computer is provided by a serial interface link.

In one embodiment of the invention the high-level data link controller is provided by an integrated circuit, namely, an advance data link controller and a line driver and receiver are provided.

Preferably, the high-level data link controller interface comprises by-pass logic to allow serial data in the loop to by-pass a particular station when it is off-line. Preferably, the serial data is by-passed through double pole double throw relays in the high-level data link controller if the main power fails.

In another embodiment of the invention the line driver and line receiver of the high-level data link controller are integrated circuits of the type meeting standard EIA RS422.

Preferably, the interface means to interface each data entry station with the liquid crystal display comprises CMOS logic.

Advantageously, a pair of CMOS data latches drive the liquid crystal display interface signals.

In another embodiment of the invention the relay coils of the relays of the high-level data link controller are controlled by one of the CMOS data latch drivers of the liquid crystal display.

In a further embodiment of the invention the interface means for interfacing with a keyboard is provided by an integrated circuit CMOS data latch. Preferably, the data latches are octal D-type flip-flop latches.

Advantageously, a three to eight line decoder/demultiplexer integrated circuit is provided to enable the interfacing means for the liquid crystal display, the keyboard and other interfacing means.

In another embodiment of the invention the serial interface link of the master station comprises an asynchronous communication interface adaptor (ACIA).

In a further embodiment of the invention a clock drive is provided in the interface means with the computer to generate the master HDLC clock signal and the ACIA clock signal.

Preferably. the serial interface link also comprises a line receiver and driver.

Preferably, the control means in each data entry station and each master station is provided by a central processing unit. provided by a microprocessor. Advantageously, the memory means is provided by RAM AND PROM.

The invention will be more clearly understood from the following description of a preferred embodiment thereof given by way of example only with reference to the accompanying drawings in which: Figure 1 is a schematic representation of the apparatus according to the invention, Figure 2 is a circuit diagram of a data entry station according to the invention, Figure 3a to e are enlarged views of the circuit of Fig. 2. and Figure 4 is a circuit diagram of portion of the circuitry of a master station of the apparatus according to the invention.

Referring to the drawings. and initially to Fig. 1, there is provided apparatus according to the invention for handling production data from a plurality of sources and directing it to a personal computer and subsequently displaying the data. In this case the apparatus comprises five data entry stations indicated by the reference numeral 1. each of which receives the data from a keyboard 2. The data entry stations 1 are connected in a daisy chain loop 3 to a master station 4 and data is directed around the loop 3 in the same direction. The master station delivers the data to a computing means, in this case a personal computer 5, and the received data from the personal computer 5 is directed by the master station 4 to the relevant data entry station 1. An LCD display 6 hooked up to each data entry station 1 displays the data delivered to and from the personal computer 5.Data is also displayed on a visual display unit 7 of the computer 5 and a printer 8 if desired may be hooked up to the personal computer 5.

Essentially, the circuitry for the master station 4 is substantially similar to the circuitry for each data entry station 1. and the only difference is that the master station has an additional expansion circuit which is illustrated in Fig. 4. The circuitry for the data entry stations 1 is illustrated in Fig. 2. For clarity it is intended to deal initially with the circuiry for each data entry station 1, and then to deal with the additional circuitry for the master station.

Referring to Fig. 2 each data entry station comprises a control means, in this case a central processing unit provided a Hitachi 6303 microprocessor indicated by the reference U12. The microprocessor operates at a clock rate of 1.2288 MHz which allows the baud rate of the on chip serial interface to be set at either 300, 1,200 or 9.600. A crystal XTAL 1 or a ceramic resonator CSC 300 sets the clock frequency of the microprocessor.

The microprocessor U12 directs all operations in the circuit by setting up timing control signals. The microprocessor U12 relies on the instructions it receives from a program to carry out is functions.

A memory means, in this case, is provided by up to 40K bytes of memory. In this case five memory integrated circuits, namely, U3, U4 and U19, and U7 and U8. The upper 1 6K bytes of memory is dedicated to PROM, namely, U7 and U8 to store the program to direct the microprocessor U 1 2. The lower 24K bytes of memory is dedicated to RAM, namely U3, U4 and U19 to temporarily store the data in each station 1 or 4 prior to transfer. The RAM also stores the functions of the keys of the keyboard which are offloaded from the computer 5. The 3 RAM IC's U3, U4 and U19 are CMOS with very low standby current consumption. The RAM integrated circuits U3, U4 and U19 can be either 2K byte memory integrated circuits or 8K byte memory integrated circuits as required.A jumper K1 is provided to allow for the differences between the 2K and 81 < integrated circuits. The main difference being that the read/write line is pin number 27 in the 8K byte integrated circuits and it is pin number 23 in the 2K byte integrated circuits.

The PROM integrated circuits U7 and U8 are NMOS and each are 8 byte IC's. The RAMS U3. U4 and U19 and the PROMS U7 and U8 are addressable by a memory address decoder. in this case a 3 to 8 line decoder/ demultiplexer U1 1 of the type 74HC138 CMOS logic is used to implement address decoding. The microprocessor in addressing the memory uses address lines Al 3 to Al 5 to decode the memory integrated circuits enable lines where the lines connected to pins 15.

14, 13 and pin 9 and 7 enable the memory integrated circuits U3, U4, Us 9. U7 and U8 respectively.

The RAM integrated circuits are disabled during mains power failure by three transistor circuits indicated by the reference numeral 9 To protect against accidental over-writing during power down and start up sequences a NAND gate U10 output Is connected to the R/N line of the memory integrated circuits and keeps the memory integrated circuits In the read mode during power down and start up sequences.

Data is inputted to each data entry station through a 64 key keyboard 2 illustrated in Fig. 1, but not In Figs. 2 to 4. The keyboard 2 is connected to port J1A and is interfaced to the microprocessor U 1 2 by an interface means, in this case provided by an octal Dtype latch integrated circuit U 1 2 of the type 74HC273. In this case the keyboard is an 8 x 8 key matrix, and encoding is performed by the central processing unit U1. The least significant 8 address bits are used to set up the scan pattern, the result of which is read in by Port 1 of the microprocessor Us 2. Port J3 is provided for connecting other peripheral devices which would be interfaced by an onchip serial interface provided on the microprocessor U12 at Point P22.

The liquid crystal display 6 is connected to each data entry station 1 through port J1 B, in this case the liquid crystal display is a 40 character Daini Seikosha liquid crystal display module type M401 1. The liquid crystal display 6 is interfaced to the microprocessor U2 by interface means which in this case are provided by a pair of integrated circuits U17 and U18, each being CMOS octal D-type latches.

Interface means for connecting each data entry station 1 to other data entry stations and to the master station 4, in this case is provided by a high-level data link controller (HDLC), in this case, an advanced data link controller (ADLC) U6 sold under the Trade Name Motorola Part No. MC 6854. The purpose of the ADLC U6 in the master terminal is to set up the data to be transmitted in a frame by frame format i.e. the data is transmitted on a frame basis, where each frame contains flags which give information on the frame boundary and the position of each field of the frame, an address field which gives the address to which the data is being sent, a control field which gives information on the link control, an information field which contains the data and a frame check sequence field which ensure that each frame reaches its destination in the correct order.In the station terminals the purpose of the ADLC U6 is to recognise data which is meant for that particular terminal and to interface the data to the microprocessor U12. When data is being sent from a station terminal to a master terminal the roles of the ADLC U6 in each terminal is reversed. Line drivers provided by integrated circuits U14 and line receivers provided by integrated circuits U15 are provided. In this case, the integrated circuis U 1 4 are drivers to meet standard EIA RS422, and the integrated circuits U 1 5 are receivers conforming to the same standard. Integrated logic circuit U2 provides a by-pass facility in the event of the ADLC controller U6 being off-line.

Two double pole double throw relays RL1 and RL2 are provided in the HDLC link so that the loops signals completely by-pass the data entry station if the mains power fails. The coils of the relays RL1 and RL2 are driven by the integrated circuit U 1 7 via VMOS fets 03 and Q4. A four pole single throw relay RL3 isolates the loop signals from the data entry station circuitry to avoid adversely effecting the loop signals in the event of power failure in any of the data entry stations. The coil of the relay RL3 is driven by a VMOS fet 05.

A hardware decoder in this case a 3 to 8 line decoder/demultiplexer U 1 6 enables the interfacing means for the liquid crystal display module, the keybaord, the high level data link controller and an expansion port as will be described below. The decoder U16 is enabled using signal from ditto CS7 U11 and addressed using lines A10 to A12 of the microprocessor U 12.

Power fail (PFAl) indication from the power supply unit is connected to the microprocessor U 1 2. The microprocessor U 1 2 releases the by-pass relays RLI to RL3 and sets up a memory protect when an interrupt occurs.

An audible warning means, in this case a buzzer 9 is provided to warn in the event of incorrect data being inputted. A light emitting diode 10 also gives a visual warning in the event of incorrect data being inputted. These are driven by the integrated circuits U17 via bifets Q1 and Q2.

Referring to Fig. 4, an expansion circuit for connecting to a data entry station just described is illustrated. The circuit converts a data entry station into a master station and it forms an interface means for the master station 4 with the personal computer 5. This circuit is connected by its ports JA, JB into the port J5 of the data entry station circuit.

Port P1 in the expansion circuit is provided for connecting the circuit to the personal computer 5. The interface circuit is a serial interface link and comprises an asynchronous communications interface (ACIA) which is provided by an integrated circuit sold under the Trade Name Hitachi Part No. HD6350. This implements hand-shaking. A clock divider U21 divides the microprocessor clock EU12 to generate the baud rate clock signal AC1ACLK for the interface. The clock divider U21 also provides the master HDLC clock signal for the loop. A line driver U23 and a line receiver U24 are provided by integrated circuits of the type 1488 and 1489 respectively.

Both the data entry stations 1 and the master station 4 are powered by a mains driven power supply (not shown). This output + 5 volts and - 5 volts for the data entry stations, and + 5 volts and - 5 volts and + 12 volts and - 1 2 volts for the master station. The 12 volts is required to power the line driver U23 of the expansion circuit illustrated in Fig. 4. The power supply units supply a TTL lever power fail signal at least 5 milliseconds prior to loss of power. A standby power supply in this case provided by an NEC 1.0 Farad "Supercap indicated generally by the reference numeral 8 provides temporary back-up for the RAMS U3. U4 and U19 in the event of mains interruption. The standby power supply maintains the supply to the RAMS for a minimum of 12 hours at 25 C.

A reset facility is provided by reset switch SW1, which is passed to the microprocessor reset line RST via a Schmitt trigger U9.

In this case, the personal computer is the personal computer sold by IBM (RTM). The data is processed in the personal computer having been entered via the master station.

The program to process the data is stored in the personal computer. This program also monitors the operation of the network of the data entry stations and the master station.

Further, the configuration of each keyboard is set up by the program in the personal computer prior to start-up of the system. This, as already discussed, is offloaded into the RAMS of the data entry stations.

In use. an operator inputs the production data into a data entry station 1 by the keyboard 2. All the inputted data is stored in the RAMS U3. U4 and U19 in the data entry station and relayed to the master station where it is further stored in the RAMS U3, U4 and U 1 9 of the master station and then subsequently it is transmitted by the master station to the personal computer 5. The data from the personal computer is directed to the master station 5 where it is in turn sent down the loop 3 to the relevant data entry station 1 and then can be displayed on the liquid crystal display 6 of the data entry station, or alternatively stored in the RAMS of the relevant data entry station 1.

Audible and visual warnings are provided to an operator from the buzzer 9 and light emitting diode 10 should an attempt be made to input inconsistent or incorrect data.

While the apparatus just described has been described as having a microprocessor sold under the Trade Mark HITACHI Part No.

6303 any suitable micrprocessor could be used. Furthermore, it will be appreciated that all received data is formatted before being displayed. although, needless to say. this is not essential to the invention.

It will also be appreciated that while the apparatus has been described as having other specific integrated circuits, any other suitable integrated circuits could be used. It will of course be appreciated that in certain cases the apparatus could be provided without a standby power supply without departing from the scope of the invention. Similarly, any suitable power supply unit could be provided.

It will be appreciated that while the main circuit of the master station has been described as being similar to the circuit of the data entry station, this is not necessary. It will of course be appreciated that certain portions of the circuitry may be omitted for the master station. For example, in certain cases it is envisaged that the keyboard interface could be dispensed with, as also could the liquid crystal display interface be dispensed with.

Needless to say, it will be appreciated to those skilled in the art that other portions could similarly be dispensed with without departing from the scope of the invention.

Claims

1. Apparatus for handling data from plurality of sources for feeding to a computer means, the apparatus comprising a plurality of data entry stations to receive the data from each source and a master station to direct the data from the data entry stations to the computer means, each data entry station comprising; interface means for interfacing with the keyboard to receive the data, interface means to interface the data entry station with the master station to direct the data to the master station and receive data from the master station, interface means to interface with a liquid crystal display for displaying data being directed to or received from the computer means, control means to control the data entry station, and memory means to store data in the data entry station, the master station comprising;; interface means for interfacing with each data entry station for receiving data from the data entry station and directing data to the data entry station, interface means for interfacing with the computer means to direct data to the computer means and to receive data from the computer means.

control means to control the master station.

and memory means to store data in the master station.

2. Apparatus as claimed in claim 1 in which the high-level data link controller is provided by an integrated circuit, namely. an advance data link controller and a line driver and receiver are provided.

3. Apparatus as claimed in claim 2 in which the high-level data link controller interface comprises by-pass logic to allow serial data in the loop to by-pass a particular station when it is off-line.

4. Apparatus as claimed in claim 3 in which the serial data is by-passed through double pole double throw relays in the highlevel data link controller if the main power fails.

5. Apparatus as claimed in any of claims 2 to 4 in which the line driver and line receiver of the high-level data link controller are integrated circuits of the type meeting standard EIA RS422.

6. Apparatus as claimed in any preceding claim in which the interface means to interface each data entry station with the liquid crystal display comprises CMOS logic.

7. Apparatus as claimed in claim 6 in which a pair of CMOS data latches drive the liquid crystal display interface signals.

8. Apparatus as claimed in claim 7 in which the relay coils of the relays of the highlevel data link controller are controlled by one of the CMOS data latch drivers of the liquid crystal display.

9. Apparatus as claimed in any preceding claim in which the interface means for interfacing with a keyboard is provided by an integrated circuit CMOS data latch.

10. Apparatus as claimed in any of claims 7 to 9 in which the data latches are octal Dtype flip4lop latches.

11. Apparatus as claimed in claim 10 in which a three to eight line decoder/demultiplexer integrated circuit is provided to enable the interfacing means for the liquid crystal display, the keyboard and other interfacing means.

12. Apparatus as claimed in claim 11 in which the serial interface link of the master station comprises an asynchronous communication interface adaptor (ACIA).

13. Apparatus as claimed in claim 12 in which a clock drive is provided in the interface means with the computer to generate the master HDLC clock signal and the ACIA clock signal.

14. Apparatus as claimed in claim 13 in which the serial interface link also comprises a line receiver and driver.

15. Apparatus as claimed in any preceding claim in which the control means in each data entry station and each master station is provided by a central processing unit, provided by a microprocessor.

16. Apparatus as claimed in any preceding claim in which the memory means is provided by a random access memory (RAM) for temporarily storing the data to be transferred.

17. Apparatus as claimed in claim 16 in which the function of the keys of the keyboard are offloaded from the computing means and stored in the RAM.

18. Apparatus as claimed in claim 16 or 17 in which the memory means comprises a programmable read only memory (PROM) to store the program to direct the control means.

19. Apparatus as claimed in any of claims 17 to 19 in which 3 X 8K bytes of CMOS static RAM is provided with low standby consumption.

20. Apparatus as claimed in claim 19 in which a jumper selectable option is provided to allow 2K X 8 or 8K X 8 bits integrated circuits to be equipped.

21. Apparatus as claimed in claim 18 in which the PROM comprises 2 X 8K X 8 bit integrated circuits, giving up to 16K bytes of program memory.

22. Apparatus as claimed in claim 21 in which the PROM integrated circuits are NMOS.

23. Apparatus as claimed in any of claims 16 to 22 in which the memory means are addressable by a CMOS logic address decoder.

24. Apparatus as claimed in any preceding claim in which a standby power supply is provided.

25. Apparatus as claimed in claim 24 in which the standby power supply is an NEC 1.0 Farad "Supercap".

26. Apparatus as claimed in any preceding claim in which a power supply is provided to power each data entry station and the master station and power fail indicting means from the power supply unit is connected to the interrupt line of the central processing unit of each station so that the central processing unit releases the by-pass relays of the highlevel data link controller and sets up a memory protect when an interrupt occurs.

27. Apparatus as claimed in any preceding claim in which an alerting means is provided to alert in the event of an attempt to enter incorrect data.

28. Apparatus as claimed in claim 27 in which the alerting means is provided by an audible buzzer.

29. Apparatus as claimed in either claims 27 and 28 in which the alerting means is provided by a light emitting diode.

30. Apparatus as claimed in any of claims 27 to 29 in which the alerting means is driven by one of the latches of the liquid crystal display interface.

31. Apparatus as claimed in any preceding claim in which the apparatus is connected to a computing means provided by a personal computer.

32. Apparatus as claimed in any preceding claim in which the apparatus is for handling production data.

33. Apparatus as claimed in any preceding claim in which the apparatus is for handling quality control data.

34. Apparatus as claimed in claim 33 in which the liquid crystal display displays quality control data including deviations from a standard.

35. Apparatus as substantially described herein with reference to and as illustrated in the accompanying drawings.

36. A data entry station for use in the apparatus of any of claims 1 to 35.

37. A master station for use in the apparatus of any of claims 1 to 36.

38. A data entry station substantially described herein with reference to and as illustrated in the accompanying drawings.

39. A master station substantially described herein with reference to and as illustrated in the accompanying drawings.