GB2151421A

GB2151421A - Phase synchronizer of digital kind for signals at the same frequency, particularly for signal demodulator

Info

Publication number: GB2151421A
Application number: GB08430638A
Authority: GB
Inventors: Guido Torelli; Vincenzo Daniele; Giovanni Salomone
Original assignee: ATES Componenti Elettronici SpA
Current assignee: STMicroelectronics SRL
Priority date: 1983-12-12
Filing date: 1984-12-05
Publication date: 1985-07-17
Also published as: GB8430638D0; DE3444401A1; IT1212796B; JPS60142638A; FR2556527B1; GB2151421B; KR850005054A; FR2556527A1; IT8324109A0; DE3444401C2

Abstract

One of the signals (B) at the same frequency which are to be submitted to phase synchronization is generated at multiple frequency (A) by a frequency generator 11, and then submitted to frequency division in a frequency divider 6. A phase detector 13 detects the phase error between the above mentioned signals and a digital phase error detector 9 transforms said phase error into a digital control signal for a lead/lag circuit 5 for advancing or delaying the commutation instants of digital signals, which circuit 5 is interposed between said frequency generator 11 and said frequency divider 6. The signal B forms a reconstructed carrier for demodulating received signal M by beating 7 and filtering 12, e.g. in a television. <IMAGE>

Description

SPECIFICATION Phase synchronizer of digital kind for signals at the same frequency, particularly for signal demodulator The present invention relates to a phase synchronizer of digital kind for signals at the same frequency, particularly for signal demodulator.

A typical example of circuit in which it is necessary to operate the phase synchronization of two signals at the same frequency is represented by those demodulators, known per se, in which a reduced-frequency reference signal is firstly multiplied in frequency and then caused to beat in phase synchronism with the modulated signal, in order to obtain a demodulated signal suitable for the foreseen objects. This happens, for example, in some television-sets, in which the available reference frequency is 15.6 kHz and that of the modulated carrier ("master tone") is about 54.7 kHz equal to 3.5 times the reference frequency.

In such demodulator the frequency multiplication of the reference signal is conventionally obtained by a PLL system ("Phase locked loop"), in which a VCO oscillator ("voltage controlled oscillator") is caused to oscillate at the frequency of the carrier of the modulated signal to be demodulated, thereby causing a so called "restored carrier", which is then submitted to beat with the above mentioned modulated signal. In such PLL system, the VCO oscillator is controlled by a voltage controlled by the error signal resulting from the phase comparison between the reference sig nal and the output signal of the VCO oscillator, submitted to frequency division by a factor equal to the frequency ratio between the above mentioned signals.In the televisionsets such ratio, and consequently the frequency division factor, is for example equal to 3.5.

In some cases, as the frequency division by 3.5 shows some difficulties, one obtains the same result by causing VCO to oscillate at a frequence multiple of that of the modulated signal and then obtaining from said multiple frequency, through frequency division, the desired "restored carrier", at a frequency equal to that of the modulated signal. The output signal of the VCO oscillator is also submitted to further frequency division, by a factor equal to the frequency ratio between said output signal and the reference signal, in order to obtain a signal useful for the phase comparison with the reference signal and the consequent generation of the control voltage for the VCO oscillator.Particularly, for the televisionsets there is usually used a VCO oscillator, which oscillates at a frequency equal to 112 times the reference one and said frequency is divided by 32 in order to obtain the "restored carrier" and by 11 2 in order to obtain the signal useful for the phase comparison with the reference signal.

In the last mentioned cases the phase synchronization between the two signals at the same frequency subjected to "beat" (that is the restored carrier and the modulated signal) is obtained with analogue sytem, by obtaining from the "beat" a phase difference indicating signal, which through suitable circuits is made operating on the VCO oscillator in order to change, if necessary, its oscillation frequency.

It is on the other hand known that for different reasons sometimes it can be preferable to use digital systems instead of analogue systems.

The object of the present invention is thus to realize a phase synchronizer, particularly but not exclusively for a signal demodulator, in which there is provided the use of digital circuits.

According to the invention such object is reached by means of a phase synchronizer for signals at the same frequency, in which one of said signals at the same frequency is made available by a frequency divider through frequency division of a digital signal at multiple frequency, which is produced by a frequency generator, characterized in that it comprises a lead/lag circuit for advancing and delaying the commutation instants of digital signals, which circuit is inserted between said frequency generator and said frequency divider, a phase detector able to detect the phase error between said signals at the same frequency and a digital error detector able to transform said phase error into a digital control signal for said lead/lag circuit for the commutation instants.

An embodiment of the phase synchronizer according to the invention is represented for better clarity in the enclosed drawings, in which: Figure 1 shows the block diagram of a signal demodulator including a phase synchronizer according to the invention; Figure 2 shows illustrative graphics of the waveforms of the signals on which the above mentioned phase synchronizer operates.

With reference to Fig. 1, there is illustrated a signal demodulator, for example for television uses, in which a modulated signal M, particularly a modulated carrier, is submitted to demodulation by beat with a signal at the same frequency or "restored carrier" B obtained through suitable multiplication and division of the (lower) frequency of the reference signal R. For example, in the above mentioned supposition of television use, the modulated carrier M could have a frequency equal to 54.7 kHz, while the reference signal R could have a frequency equal to 15.6 kHz, which is then the line frequency.

For the frequency multiplication it is used a VCO oscillator 1, which is caused to oscillate at a frequency multiple of that of the reference signal, for example with a multiplication factor equal to 1 12, as well as of that of the modulated carrier M, for example with a factor equal to 32.

The oscillator 1 is controlled by a voltage V obtained after filtering, in a low-pass filter 2, of the error signal E resulting from a phase comparison, executed in a comparator 3, of the reference signal R and of a signal of equal frequency S obtained by division of the oscillation frequency of the oscillator 1, in a divider 4, by a factor equal to the multiplication one due to the loop including the oscillator 1.

In the considered example the divider 4 thus makes a division by 112.

The oscillator 1, the comparator 3, the filter 2 and the divider 4 substantially form a frequency generator 11, at the output of which a multiple frequency digital signal A (Fig. 2) is made available. As shown in Fig. 1, the signal A is then made pass through a transfer logic gate 5 and submitted to frequency division (by 32 in the considered example) in a divider 6 until to obtain a digital signal B (Fig. 2) having the same frequency of the modulated carrier M, that is the so called "restored carrier".

A beat circuit 7 finally carries out the "beat" of the modulated carrier M with the restored carrier B, creating, through a lowpass filter 12, the desired demodulated signal DM.

For a correct demodulation it is however necessary that the two signals at the same frequency M and B submitted to beat are also in phase with each other.

For such object there is provided a phase synchronizer according to the invention, which is indicated with 10 in Fig. 1 and comprises, in addition to the already mentioned transfer gate 5, a phase detector 13, a low-pass filter 8 and a digital error detector 9.

The phase detector 13, for example constituted by a further beat circuit or by a phase comparator, receives the two signals at the same frequency M and B, one of which (the signal B in the illustrated example) subjected to a phase shifting of 90 in a phse shifter 14, detecting the phase error as a deviation of the cosine from the unit value.

Through the low-pass filter 8 such phase error is communicated to the error detector 9, which transforms it into a digital error signal DE (one or more pulses of fixed or variable length), which controls the opening time of the transfer gate 5, in a continuous or discontinuous way, up to cause the annulment of the phase.

In order to better understand the mode of operation of the synchronizer 10, one considers the graphics of Fig. 2, where it is supposed that from the signal A at multiple frequency can be obtained a restored carrier B having the same frequency of the modulated carrier M, but with phase advancement with respect to it.

Therefore there exists a phase error, from which derives, through the detector 9, a digital error signal DE, which, through the control of the opening time of the gate 5, delays the leading front of the restored carrier B up to cause it to coincide with that of the modulated carrier M.

In similar way the same synchronizer would act in case of phase delay of the signal B with respect to the signal M.

Naturally, the example illustrated in the drawings is only an embodiment of the phase digital synchronizer according to the invention and several changes can be brought to the above mentioned example without going out of the limits of the invention.

Particularly, for example, the transfer logic gate 5 can be replaced with a different logic circuit (for example of NAND or NOR kind), as well as by a circuit which provides the pulse generation to anticipate, rather than to delay, the signal B with respect to the signal M.

Generally, however, the circuit 5 must be a circuit able to advance or to delay the commutation instants of the multiple frequency signal A.

Besides, the phase synchronizer could not be included in a signal demodulator, but generally used for the phase synchronization of two signals at the same frequency B and M for the most various uses. In such case, the frequency generator 11 could be of any known kind and could use either a reducedfrequency reference signal as the above mentioned signal R or the same signal B to create by multiplication the multiple frequency signal A to be controlled through a lead/lag circuit such as the transfer logic gate 5 or other suitable circuit.

Claims

1. Phase synchronizer of digital kind for signals at the same frequency, particularly for signal demodulator, in which one of said signals at the same frequency is made available by a frequency divider through frequency division of a digital signal at multiple frequency which is produced by a frequency generator. characterized in that it comprises a lead/lag circuit for advancing and delaying the commutation instants of digital signals, which circuit is inserted between said frequency generator and said frequency divider, a phase detector able to detect the phase error between said signals at the same frequency and a digital error detector able to transform said phase error into a digital control signal for said lead/lag circuit for the commutation instants.

2. Phase synchronizer according to claim 1, characterized in that said lead/lag circuit for the commutation instants is constituted by a transfer logic gate with opening times con trolled by said digital control signal.

3. Phase synchronizer according to claim 1, characterized in that said lead/lag circuit is constituted by a logic circuit of NAND/NOR kind.

4. Phase synchronizer according to claim 1, characterized in that said lead/lag circuit comprises a pulse generator.

5. Phase synchronizer according to claim 1, characterized in that said phase detector is constituted by a beat circuit for said signals at the same frequency.

6. Phase synchronizer according to claim 1, characterized in that said detector phase is constituted by a phase comparator.

7. Phase synchronizer according to claim 1, characterized in that said frequency generator is constituted by a frequency multiplier fed with a digital reference signal at reduced frequency.

8. Phase synchronizer according to claim 7, characterized in that said reference signal has a frequency lower than that of said signals at the same frequency.

9. Phase synchronizer according to claim 7, characterized in that said reference signal has the same frequency of said signals at the same frequency.

10. Phase synchronizer according to claim 7, characterized in that said frequency generator comprises a VCO oscillator caused to oscillate at a frequency multiple of that of said signals at the same frequency.