GB2151358A - Multiplexed control of ultrasonic transducers - Google Patents

Abstract

A plurality of ultrasonic transducers 0 to 11 are connected to a pulsing or firing unit 29 and to a multiplexer 30. A selected transducer can be fired and an echo signal received on that or another of the transducers and is transmitted on a common echo line 26 from the multiplexer. The sequential operation of the pulser unit and the multiplexer are controlled by unit 28; and address code signals for the pulser and multiplexer and control code signals for unit 28 and the echo line 26 are passed on a common cable 23. The transducers may be in an inspection head, e.g. disposed around a circumferential weld in a primary vessel of a fast breeder reactor, and operatively connected to a remote location. <IMAGE>

Description

SPECIFICATION Multiplexed control of ultrasonic transducers.

This invention relates to methods and apparatus for sensing, and in particular to the multiplexed control of ultrasonic transducers.

According to one aspect of the invention sensing apparatus comprises a-plurality of ultra-sonic transducers, means for energising any one of said transducers, and means for transmitting an echo signal from any predetermined one of the transducers to a common output.

The energised transducer may be the predetermined transducer.

The apparatus may comprise a multiplexing unit connected to the transducers for receiving the echo signal from the predetermined one transducer and transmitting an output signal on a common line.

The apparatus may comprise a pulser unit for receiving a coded signal and selecting said one of said transducers to be energised in accordance with the code.

The multiplexing unit may receive a coded signal to select the predetermined transducer.

The apparatus may comprise a control unit for controlling the multiplexing unit and the pulser unit in accordance with a coded control input signal.

According to another aspect of the invention a method of sensing comprises energising any one of a plurality of ultrasonic transducers, and transmitting an echo signal from any predetermined one of the transducers on a common output line.

The.method may comprise energising the one transducer in response to a coded transducer selection signal. The method may comprise selecting said predetermined one-of the transducers in response to a coded echo transducer selection signal.

The invention also includes a method of testing for flaws using a method as defined above.

The invention further includes apparatus for testing for flaws comprising an apparatus as defined above.

The invention may be performed in various ways and one specific embodiment with possible modifications will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a schematic arrangement of a sensing apparatus; Figures 2 to 4 show the apparatus in more detail; Figure 5 shows a pulser circuit; and Figure 6 shows a sequence of operations.

In general, the apparatus is housed in a metal enclosure 20,. Fig. 1, with suitable'connectors 21, 22 mounted on the outside respectively for ultrasonic crystal transducers 0 to 11 and an umbilical control cable.23. There are twelve individual sockets for the.twelve transducers'and a multi-waysocket 22 for the umbilical cable 23 which has sixteen-lines'of which four are not used., There are four distinct signals passing along the umbilical cable 23. These signals are: (a) address code; (b) control code; (c) echo signal; and (d) power supplies.

The address code signal is transmitted on-four lines 24 J 1 /1 3, J 1 /1 4, JI /1 5,'Jljl 6); it is a four bit binary code and it is used in conjunction with the control code signal to identify one of the twelve channels. The control code signal is transmitted on four lines 25 (J1/9,-J1/10, J 1 /11, J 1 /1 2); three. of the lines 25 carry a three bit binary code which is used to instruct the circuits within the apparatus which operation is to be performed. The fourth line J1/9 carries a timing signal which 'clocks' the control code signal into the circuits. The echo-signal is the return signal from the previously addressed ultrasonic crystal transducer which is-transmitted down a common echo return line 26.The power supplies are transmitted down three lines 27 (J1/6, J1/7, J1/8) and consist of + 15 volts with an earth return. As shown in-Fig..1, the internal circuit can be considered to comprise a three sub-system parts ie (a) Control.unit 28; (b) crystal pulsing unit 29; (c) echo signal multiplexing unit or multiplexer 30.

The control unit 28 produces, in response to the control code signals, a number of operational signals for the other two sub-system components 29, 30. The operational signals 1 to 5 with the corresponding control code are listed below: Control code Operational Signal 001 Latch address of mux (multiplexer) channel on which signal is to be received.

010 Latch address of pulser (pulsing circuit) to be fired.

100 Latch mux enable.

101 Fire pulser.

111 Latch mux disable.

Each control code signal is clocked into the control unit 28, ie at the end of the clock period the operational signal corresponding to the clocked control code signal becomes available from the control unit, on the appropriate output line.

The crystal pulsing unit 29 consists of twelve individual high-voltage pulsing circuits with a binary-to-decimal convertor which identifies the addressed operational pulsing circuit.

Each pulsing circuit (termed pulser) basically consists of an energy storage capacitor (which is for example capable of being charged to a maximum of 700 volts) and a chain of semiconductor devices. When the addressed pulser is signalled to 'fire', the semiconductor devices turn on to discharge the capacitor into the ultrasonic crystal of the associated transducer.

The multiplexing unit 30 connects just one of the crystals at a time to the common echo return line 26. The unit 30 is based on a miniature semiconductor circuit contained in a plastics package. However, it can be considered conceptually to consist of a group of switches connected to a common output line plus an internal mechanism for identifying and turning on each switch individually.

All the circuits operate fro a + 1 5 volt power supply with the exception of the high voltage supply 700v which may be provided via an external plug and socket. It is possible to generate the high voltage locally to the apparatus from the + 1 5 volt power supply as shown dotted at 80a Fig. 1 which could be adopted if further reductions in size of the umbilical cable are required.

The apparatus will now be described in greater detail.

The control unit. 28 consists of two integrated circuits 40, 41 see Fig. 2. Both circuits 40, 41 are fabricated in COOS; circuit 40 is a binary-to-decimal decoder, so that a 4 bit binary number on the input to circuit 40 will select and activate one of ten decimal output lines. Circuit 41 is a dual RS bistable. Five operational signals are required within the apparatus which are derived from the lower order outputs on circuit 40. The term lower order outputs refers to the numerical status. There are ten outputs which correspond to the numbers 1 to 10, each individually addressed via a parallel 4 bit binary input signal. The lower order outputs 1 to 5 appear on the pins 14, 2, 15, 1, 6, as shown. By feeding the control code signals from the umbilical cable 23 directly to the circuit 40, the internal operational signals are accordingly generated.The clock line J1/9 from the umbilical cable is also fed to circuit 40 to form the highest significant binary bit of the 4 bit binary number input; thus whilst the clock signal is high (ie binary 1) only outputs in excess of five are available. When the clock signal is low (ie binary 0) the operational signal corresponding to the control code signal becomes available on one of the decimal output lines 40a to 40e. Only one of the output lines 40a to 40e is active at any particular moment.

The dual RS bistable circuit 41 acts as an interlock between some of the operational signals.

This is to ensure that the Multiplexing Unit 30 is disabled and isolated before the high voltage can be applied to the particular transducer to be energized.

Two signals come from circuit 41 via the signals on lines 70 and 71. Circuit 41 will only allow a signal on line 71 to be activated if the signal on line 70 is holding the multiplexer disabled. This is achieved by feeding back to the input via line 74 the signal on line 70 which prevents the crystal being fired (by holding the associated bistable in a reset condition) whilst the multiplexer 53 is enabled. Signals on lines 40c and 40d control the two bistables. If the first bistable is in a first (set) condition then a signal cannot pass on line 71 because the second bistable is held in a second (reset) condition; if the first bistable is in a second (reset) condition a signal can pass on line 71 by placing the second bistable in a first (set) condition. A signal on line 40d changes the second bistable from the reset to the set condition and fires the pulser. A signal on line 40c places the first bistable in the set condition and enabies the multiplexer. A signal on line 40e places the first bistable in the reset condition, disables the multiplexer and allows the second bistable to be set by the signal on line 40d.

In the circuit shown in Fig. 5 the ultrasonic crystal transducer would be connected across the points marked A and ground L. This effectively puts the transducer in series with capacitor C11.

During operations, capacitor Cli charges up to a high voltage determined by the rail voltage (shown as 700 volts for example) via resistors R20, R21 and diode D3. Once charged, capacitor Cii has stored sufficient energy to physically vibrate the crystal which will in turn produce the required ultra-sound. The energy is transferred to the crystal by turning on the stack of thyristors SCR1 to SCR8, with associated components resistors R5 to R19 and capacitors C3 to C10, which connects capacitor C11 in parallel with the transducer. The thyristor.stack operates in an avalanche mode, thus turning on SCR1 causes all.the other thyristors to turn on simultaneously.

This arrangement is self-commutating, ie the thyristors turn off when capacitor Cm 1 is discharged. Thyristor,SCR1 is turned on via an input circuit based on transistor Q1, and including components R1, R2, C1, C2, R3, R4, C37, C38,. which circuit in' addition to..

converting a bistable input signal 1 /P into a monostable signal provides the necessary power to turn the thyristor on. < * Diode network D1,.D2, D4, D5, R22, R23 ensures that the energy stored in the capacitor Cli is dissipated in the ultrasonic transducer and not in parallel paths that would exist during reverse voltage firing conditions. ., ",' -, After the particular crystal has been fired, it is required to return it to a quiescent state quickly so it will be ready to receive the return echo signals. For this purpose electrical damping is included in the circuit, which damping consists of an inductor L1 and resistor R24..The degree of damping required is dependent on the transducer used; however, ifa fixed finite recovery time can be tolerated then inductor L1 and resistor R24 may be fixed for all applications. The return echo signal 0/P is transmitted to the multiplexing circuit via an active buffer circuit based on transistor Q2, and including components R44, R45, R46, R47, R48, R49, C34, C36, D6, D7. The back-to-back diodes D6 and D7 prevent the high voltages within the pulser from reaching the multiplexer 30. Signals lower than the diode clamping level (ie return echo signals) are simplified by transistor Q2.

There are twelve of the above described circuits, one for each of the transducers. The one to be fired is selected via the address lines J 1 /1 3, J 1 /14, J 1 /1 5, J 1 /1 6, using a binary-todecimal convertor integrated circuit 50 which has the additional feature of latching or memorising the address signal. The signal on line 71 is an enable/disable signal to the binary to decimal convertor 50; when enabled the convertor activates the addressed decimal output line which in turn fires the associated pulser unit.

A signal on line 40b latches the convertor 50. The addressed output (and therefore transducer) is activated by an 'enable' input signal on line 71, which is derived from the control code signal to fire the selected pulser. The integrated circuits 72, 73, act as buffers to convert the low capacity signals from circuit 50 to a form compatable with the. pulsing circuits, The echo signal multiplexer sub-system consists of four integrated circuits 52, 53, 54, 55 (Fig. 4).

The principal component is circuit 53 which is a CMOS analog multiplexer. Using a 4 bit binary input address circuit 53 will switch one of sixteen inputs onto a common output using; solid state switches. The analog inputs in this example are connected to the ultra-sonic crystal transducers and will therefore see. both the high voltage pulse plus the subsequent echo signals.

When the multiplexer 53 is disabled, the inputs are effectively isolated from the internal circuits of the integrated circuits; this feature is used to protect the multiplexer from the potentially..

damaging high voltage.pulse. Latch 52 holds the address for circuit 53,.the-multiplexer.

Only twelve of sixteen available inputs on circuit 53 are used; the unused inputs are connected to the ground; the twelve inputs 0/PA to 0/PL (being output signals from the pulser unit) are addressed from the address lines via circuit 52, a latching circuit, which provides the necessary address to switch through the correct input transducer when the multiplexer is - enabled. The signal on line 70 is the enable/disable signal to the multiplexer. : 4 Circuits 54, 55 (with respective associated components C35, R31,.C15, R26, C12, R25, C15a, C14, RV1, C13; and RV2, C17, R30, R28, R29, C16, C18) are series-connected analog amplifiers which buffer/amplify the return echo signal and transmit it down the return line 26.

(Ji/1 is screen; J 1 /2 is core).

Although it is possible to produce and apply the control code signals in a random manner, it is highly desirable operationally to impose a pre-determined sequence. For example, there would be nothing..gained from enabling the return echo multiplexer 53 if none of the transducers had been previously pulsed. The control code signals and the address line signals can be obtained.

from a computer programmed to give a desired operating sequence for the pulses.

For most purposes the sequence of operations would typically be: Step Functions Code 1 Latch address of pulser to be fired 010 2 Latch multiplexer address 001 3 Latch multiplexer disable 111 4 Fire pulser 101 5 Latch multiplexer enable 100 Step 1 is achieved by a signal on line 40b, step 2 by a signal on line 40a, step 3 by a signal on line 40e and line 70, step 4 by a signal on lines 40d, 71, step 5 by a signal on line 40c and line 70. The signals in steps 3 and 5 on line 70 are bistable signals, ie two different states.

By changing the address during the latching period both the pulse echo (ie send and receive on the same channel) and tandem operational modes can be simulated. The period for each code is determined by the clock rate. Each code is clocked into the control unit 28 during the clock period; thus a code cannot be changed outside the clock period. The clock period can be varied; however, it is necessary to ensure that the high voltage crystal pulse has decreased to a safe level before allowing the multiplexing unit to be enabled. The crystal pulse period will typically be 500 nS which allows a maximum clock frequency of 1 MHZ. A typical timing chart for the above sequence is shown in Fig. 5, based on a 1 MHZ clock rate. The pulse address latch signal is at 80, the receiver address latch signal at 81, the mux enable signal at 82, the fire pulser signal at 83 and the pulse at 84.

The electronic apparatus is intended to enable a plurality of transducers, for example in an inspection head, to be operatively connected to a remote location. In one example the transducers are ultrasonic crystal transducers disposed at spaced locations around a circumferential weld in a primary vessel of a fast breeder reactor for insepection purposes. The apparatus is located in the restricted annulus between the primary vessel and the outer guard vessel. The apparatus can individually pulse the transducers and transmit an echo signal to a central unit outside the guard vessel. The number of bulky, high voltage screened cables required between the inspection head and control room is significantly reduced compared with a system having a separate supply and control for each transducer.

An operator can address a particular pulser unit and receive the echo at a particular transducer which may be the transducer which has been fired, or one of the other transducers.

A particular pulser can be repeatedly fired and echoes respectively received by the other transducers in sequence: or a number of transducers fired in sequence and echoes received by selected transducers in accordance with a predetermined pattern, each firing producing one echo signal. The firing could be computer controlled and could be automatic. For example twelve firing signals could be made on 0/PA in succession with respective echoes on lines 0/PA to 0/PL; then twelve firing signals on 0/PB with respective echoes in 0/PA to 0/PL; and so on to twelve firing signals on 0/PL. This sequence could be repeatedly performed at predetermined intervals.

If the transducer which is to receive the echo is a different one from the transducer which is to be fired, an appropriate second address signal is supplied to the multiplexer between the latching of the pulser address and the latching of the multiplexer address.

The echo signals may for example pass to a visual display device where inspection of the display and/or comparison with predetermined displays may give information as the existence, nature, depth or other characteristic of a flaw. The echo signals may pass to a computer which may effect calculations to obtain other information relating to any flaw.

Claims (12)

1. A method of sensing comprising energising any one of a plurality of ultrasonic transducers, and transmitting an echo signal from any predetermined one of the transducers on a common output line.

2. A method as claimed in claim 1, comprising energising the one transducer in response to a coded transducer selection signal.

3. A method as claimed in claim 1 or claim 2, comprising selecting said predetermined one of the transducers in response to a coded echo transducer selection signal.

4. A method of sensing substantially as hereinbefore described.

5. A method of testing for flaws using a method as claimed, in any preceding claim.

6. Sensing apparatus comprising a plurality of ultrasonic transducers, means for energising any one of said transducers, and means for transmitting an echo signal from any predetermined one of the transducers to a common output.

7. Apparatus as claimed in claim 6, comprising a multiplexing unit connected to the transducers for receiving the echo signal from the predetermined one transducer and transmitting an output signal on a common line.

8. Apparatus as claimed in claim 7, in which the multiplexing unit receives a coded signal to select the predetermined transducer.

9. Apparatus as claimed in any of claims 6 to 8, comprising a pulser unit for receiving a coded signal to select said one of the transducers to be energised in accordance with the code.

10. Apparatus as claimed in claim 8 and claim 9, including a control unit for controlling the sequential operation of the pulser unit and the multiplying unit in response to a coded signal.

11. Apparatus as claimed in claim 10, in which the coded signals for the pulser unit, the multiplying unit and the control unit pass on a common cable.

1 2. Sensing apparatus substantially as hereinbefore described with reference to the accompanying drawings.

1 3. Apparatus for testing for flaws comprising an apparatus as claimed in any one of claims 6 to

12.