GB2149625A - A bridge circuit for interconnecting networks - Google Patents

Description

1 GB 2 149 625 A 1

SPECIFICATION

A bridge circuit for interconnecting networks This invention relates to a bridge circuit for intercon- 70 necting networks.

It is well understood in the art of data processing that it is desirable to interconnect local networks. In the prior art such local networks have been coupled together through devices generally referred to as routers. Such router devices are normally peculiar to the manufacturer thereof, such that in order for one station, on a local network, to send messages to a second station, on another local network, the first station must transmit at least a two level address or involve a two level protocol arrangement. In other words the address arrangement in the prior art is analogous to a common telephone system wherein the first three digits, i.e. exchange number such as Gramacy 3 (GR3), is one level of address and the last four digits is a second level of address. The fore going arrangement has been reasonably acceptable.

However as users have commenced purchasing equipment from different manufacturers, problems have arisen with respectto communicating, from one network to another, through a router which is manufactured by a different manufacturer than the manufacturer of the stations communicating. The difficulties have arisen in part because the higher levels of protocol required in prior art systems and also because a station of a different manufacturer has great difficulty in providing information to a router of a first manufacturer even if the router has memory means. The present invention has only one level of address information, has a learning capabil ity to increase its knowledge as to what stations are where, on any network, connected thereto, and includes a means for jettisoning relatively unused address information.

According to the present invention there is pro vided a bridge circuit for interfacing at least first and second local networks, each of which networks has a plurality of stations and each of which stations is formed to send messages that include at least a destination address and a source address, compris ing in combination: first logic circuitry means, including tridirectional data transmission path means, connected to said first and second local networks to receive data messages theref rom and formed to have a first data storage means to temporarily store said messages, said first logic circuitry further formed to examine a message sent thereto to determine if said message should be further considered for further transmission, at least to the one of said local networks not sending said message, and still further formed to generate inter rupt signals, respectively indicative of which of said first or second local networks is transmitting said message; data processor means connected to said first logic circuitry and having at leasttwo interrupt signal ports and including means to enable said data processor to be programmable; first memory means which has stored therein destination addresses, and network data indicative of which network is associ ated with each destination address, for at least part of the stations connected to said local networks; second logic circuitry connected to said first memory means, and to said first logic circuitry, and to said data processor whereby in the event it is determined that said message should be further considered, said data processor will cause at least said destination address portion of said message to be brought from said first data storage means to said second logic circuitry whereat it will be compared with said destination addresses stored in said first memory means to determine whether said message should be sent to a station connected to a network which did not initiate said message.

The present invention, in a preferred embodiment, is taught to be dealing with two local networks. It should be understood that it could be dealing with more than two networks and with multiple bridge circuits connected with multiple local networks. In the preferred embodiment taught, there is con- nected to a first local network a first LANCE device and to a second local network a second LANCE device. When, for instance, a message is sent from the first local network to its associated LANCE device, the message is examined and if it is accept- able for further transmission, the LANCE device sends an interrupt signal to a microprocessor. Meantime the message has been stored in a buffer RAM. In response to the interrupt signal, the microprocessor is aware of which network has sent the message and fetches the destination address portion of the message, from the buffer RAM, to a look up controller circuit. The look up controller circuit is designed to take the destination address information and compare it against a group of destination addresses which are held in a look up RAM. The destination address information, in the look up RAM, includes a tag which indicates whetherthe destination address belongs to a station in the first orthe second local network. If there is a match between the destination address portion of the message and a destination address in the look up memory, the microprocessor will send the message to the proper station through the bridge, or ignore the message if the sending station is on the same local network as the receiving station. If there is no match (because there is no destination address loaded in the look up memory which will match the destination address of the message), then the message will be sent to the other network. After operating on the destination address portion of the message, the system operates on the source address portion of the message. The source address portion is compared against the destination addresses stored in the look up memory and if there is no match, then the system has "learned" that another station is present and where it is located. This "learned" address information is temporarily stored in a "new source" RAM and at some latertime is added, through reorganization by the microprocessor, to the look up memory destina- tion addresses. The system insures that there will be available space in the look up memory by removing therefrom destination addresses which are not repeatedly used. This feature may be called into play when portable stations are "plugged in" at new locations which, of course, may mean anew net- 2 GB 2 149 625 A 2 work. For instance, and by way of example only, if a station is not addressed at its old network address for 15 minutes, then its old network address will be removed from the look up memory.

The objects and features of the present invention will be better understood in view of the following description taken in conjunction with the drawings wherein:

Figure 1 is a block schematic diagram of the presentsystem; Figure 2 is a block schematic diagram of the memory controller; and Figure 3 is a block schematic diagram of the look up controller circuitry.

Consider Figure 1. In Figure 1 there is shown a first network made up of three stations 1 A, 2A and 3A connected to a common bus 11. In addition in Figure 1 there is shown a second network made up of three stations 1 B, 213 and 313 connected to a common bus 13. It should be understood that there could be more than three stations in each network and there could be more than two networks.

Connected to the -A- local network is a LANCE 15, while connected to the---Wlocal network is a LANCE 17. Each of the LANCEs 15 and 17, in a preferred embodiment, is a MK 68590 device, manufactured by Mostek Company, a division of United Technolo gies Corporation. The LANCE device is designed to do a number of operations. First, a message trans mitted from a station on a network is examined by its associated LANCE device to determine whetherthe message is complete and errorfree. For instance if the message were too long, ortoo short, or carries an indication that an error is present, or some other infirmity is present then the LANCE would not indicate to the system that the message should be transmitted through the bridge circuit. However if the LANCE device determines that the message received is suitable to be considered for further transmission, then the LANCE device 15, for inst ance, is connected to send an interrupt signal on line 19 to the microprocessor 21. Meantime the message is transmitted, while the LANCE 15 examines the message, to the Buffer RAM 29. In a preferred embodiment the microprocessor is a type 68000 manufactured by Motorola Corporation. Other types of microprocessors could be used.

It will be noted in Figure 1 that the program RAM and the new source RAM are shown as separate components. The two foregoing RAMs, whose roles will be explained below, can be part of one data processor, or one RAM device, although in the present embodiment they are considered as sepa rate components. Also shown in Figure 1 is a look up controller, depicted as a separate component and it should be understood thatthe look up controller circuitry could be included in a data processor. The foregoing mentioned separate components are em ployed and discussed as separate components in the preferred embodiment in order that system can be discussed with a relatively uncomplicated microp rocessor.

Further as can be seen in Figure 1, the LANCE device 15 is connected through channel 23 to the memory controller circuit 25 while the LANCE device130 17 is connected thereto through channel 27. The memory controller 25 is depicted in detail in Figure 2. As mentioned earlier, connected to the memory controller 25 is a buffer RAM 29. The memory controller 25 is a three port device with bidirectional data paths to and from the LANCE 15, the LANCE 17 and microprocessor 2 1.

Connected to the bus 31 in a ROM 33, a new source RAM 35, a look up control circuit 37 which is connected to a look up RAM 39, and a program RAM 41. The ROM 33, in a preferred embodiment is a 2764 manufactured by Intel Corporation. The new source RAM 35, in a preferred embodiment is a 2167 manufactured by Intel Corporation. The program RAM 41 in a preferred embodiment is a 2167 manufactured by Intel Corporation.

Considerthe circuitry of Figure 1 to understand the overall operation of the system. Assume a first situation where station 1A wants to send a message to station 2B. In this first station, station 1A would send a message which would have 64 bits of preamble information, 48 bits of destination address information, 48 bits of source address information, variable amounts of user data thereafter and finally a group of signals which indicates the presence or absence of an error. The present system is principally involved with the destination address signals and the source address signals. The message from station 1A would have a destination address of station 2B and a source address of station 1A.

The message would be transmitted to the LANCE device 15 whereat the preamble portion is decoded, the number of bits in the message are counted and the error status checked. The capacity to accomplish these functions is inherent in the LANCE device. If the LANCE device 15 finds no improprieties in the message format, the LANCE device 15 will generate an interrupt signal on line 19 to the microprocessor 21. As mentioned earlier in conjunction with the examination of the message by LANCE 15, the message is transmitted to the Buffer RAM 29. In response to the interrupt signal on line 19, the microprocessor 21 sends a set of address signals to the buffer RAM 29, to fetch therefrom the destination address portion of the message being held by the buffer RAM 29. The destination address information is transmitted along channel 31 to the look up control circuitry 37. It should be understood that the channel 31 is composed of at least 40 parallel lines, 24 of which are dedicated to address signals, and 16 of which are dedicated to data signals. As will be better understood when Figure 3 is discussed, the address information from the buffer RAM 29 is received by the look up control circuit 37. The look up control circuit 37 is designed to compare the destination address signals from the buffer RAM 29 against a plurality, or library, of destination addresses held by the look up RAM 39. The loading of the destination addresses into the look up RAM 39 will be discussed below but for the moment it should be accepted that the look up RAM 39 is storing a plurality of destination addresses. The destination addresses in the look up memory have additional information associated therewith. The additional information provides an indication of whether the GB 2 149 625 A 3 station, whose address is stored in the look up memory, is on the "A" network or the "B" network.

After the comparison has been made by the look up control circuitry 37, the microprocessor 21 is advised that the destination address is present in the look up memory and the addressee is not on the "A" side. Thereafter the microprocessor 21 sends a request to the buffer RAM 29 to fetch the source address signals from the message it is holding and forward said source address signals to the look up control 37. Meantime the microprocessor sends a command signal to the LANCE which instructs the memory controller to fetch the message from the buffer RAM 29 and transmit it over channel 27 to the LANCE 17, therefrom to the common bus 13 and subsequently station 2B will respond to accept the message.

When the source address is received by the look up control circuit 37, it is compared against the destination addresses, as was the destination address of the message previously described. This procedure is part of the "learning" capability of the present system. If the source address is found to match a destination address, the look up RAM 39, then the microprocessor is so advised and nothing more is done with this part of the operation. On the other hand if the source address is not found amongst the destination addresses held by the look up RAM 39, then the microprocessor directs the look up control circuitry 37 to send the source address to the new source RAM 35 and the microprocessor adds the above mentioned additional information thereto, i.e. in our example, the additional informa tion indicates in which network station 1A (the source) is located. The system operates to self learn 100 and load the look up RAM 39 by adding destination addresses (from source addresses) to the look up RAM 39 when a station on a network sends a message, When a station on a network sends a message, the message includes the source address as explained earlier and the interrupt signal indicates to the microprocessor from which network the message is being sent, hence in which network the source is located. Accordingly, even after just start ing the system up, as the various stations send messages, their addresses are added to the look up RAM and the bridge circuit system commences to "learn" where the various stations are located.

Returning to our example we find that when the microprocessor 21 has some spare time, it under takes a programmed routine to fetch address signals from the new source RAM 35 and transfers them to the look up control circuitry to be inserted into the proper location in the look up RAM 39. As will become better understood from the discussion of Figure 3, the microprocessor 21 can effect a reorga nization of the look up RAM 39. Thus far we have considered an example of sending a message from station 1A to station 2B and have seen how the circuitry works.

If in a second situation, the station 1A sends a message to station 3A a somewhat different scenar io is painted. The "A" network does not need the bridge circuit to enable station 1A to send a message to station 3A. However the bridge circuit makes use of this operation in its self learning procedure. In our second example when the message is sent from station 1Ato station 3A it is still received by the LANCE 15 simultaneously with it being received by the station 3A. The LANCE 15 does not "know" that the message need not go through the bridge and it handles the message as before. However in the second situation when the destination address (that of station 3A) is compared with the look up RAM addresses, itwill be determined that station 3A is on the same network as the sending station 1A, or the source, and hence the message in buffer RAM 29 will not be forwarded through the bridge. At the same time, the source address will be compared, as described before and if not found in the look up RAM 39 it will be added thereto as explained above.

If we alter the facts in our second example and assume that the destination address (station 3M is not in the look up RAM, then a variation on the operation occurs. The message is received by the LANCE 15, stored in the buffer RAM 29, and the destination address compared, all as explained before. However in this last situation the microprocessor is advised that the network location of the station is unknown, in fact its existence is unknown. In this situation the microprocessor directs the LANCE to cause the memory controller to fetch the message from the buffer RAM and send it to the "B" network. In accordance with the philosophy of the bridge system, if the destination address is not identified with a network, it will be transmitted through the bridge. Sooner or later the station 3A will send a message and then its address (sent as a source) will be added to the look up RAM and its whereabouts will no longer be unknown as was the case in the variation of the second situation just discussed.

The capacity to transmit messages when the destination address is not identified with a network enables the present bridge system to handle situations where if the look up RAM should become filled, and the destination address for a station could simply not get loaded into the look up RAM, messages sent to that station would be transmitted and received. The capability to transmit, when a station's address is not identified with a network, permits the system to operate before the learning algorithm takes effect, i.e. the system accomodates stations which are on a connecting network but which have not as yet been identified from a source address. An example of such a situation could be a data processing system in an office building, or a university building, where each floor is a network and a portable terminal is moved from the first floor to the second floor and wherein from its new location it has not yet been identified.

Some other features which can be gleaned from Figure 1 have not been discussed. The ROM 33 is a non volatile memory in which there is stored all of the programs necessary to operate the microprocessor 21 in the present bridge system. Program RAM 41 is a volatile memory to which the current program signals are transferred from ROM 33 and which acts as the scratch pad memory and current program memory for the microprocessor 21.

4 GB 2 149 625 A 4 The present bridge system also includes, philo sophically, the notion that if a station is not active, then its address should be deleted to make room for more active station addresses. This notion is im plemented by having the timer 43 provided an interrupt signal at some given time period, for instance byway of example every 100 milliseconds.

Othertime periods could be used. When the timer 43 sends said last mentioned interrupt signal, the microprocessor goes into a programmed routine whereby every destination address in the look up RAM is brought therefrom and the clock bits associ ated therewith are decremented. The clock bits are also additional information bits added to the destina tion addresses when they are loaded in the look up memory. The clock bits will have some value, for instance, the value of fifteen minutes in some binary code. Other value could be used. When the clock bits have been decremented to zero, the associated destination address is eligible for being removed in a reorganization operation or during an entry of addresses from the new source RAM 35. It should be understood that when a destination address in the look up RAM has been involved in a match, the data processor automatically resets its clock bits to the maximum value.

The interrupt signals from LANCE 17 are sent on line 20. It should be understood that although interrupt signals are sent to the microprocessor 21, the system could be operated where the LANCEs merely generate a "need attention" signal and the microprocessor could regularly pole the LANCEs to obtain the equivalent of an interrupt signal by virtue of the "need attention" signal. The system is arranged by the programmer so that LANCE 15 loads the messages it handles in predetermined addresses in the buffer RAM 29 and in a similar fashion LANCE 17 loads the messages it handles in different prede termined addresses. The microprocessor 21 pro vides instructions to the LANCEs 15 and 17 to accomplish the foregoing. The microprocessor is programmed to keep an account of what addresses the respective LANCEs will use and in fact in what addresses in the buffer RAM, particular messages have been stored. This programming arrangement enables the microprocessor to fetch from the buffer RAM the destination address information and the source address information of a particular message, make a decision as to whether or not that message should be transmitted on, add network location 115 information to the addresses, etc. as described above.

Consider Figure 2 which is a detailed block diagram of the memory controller 37. In Figure 2 the LANCEs 15 and 17 are shown as well as the DAL Bus 120 31 from the microprocessor 21 of Figure 1. In addition the buffer RAM 29 as shown in Figure 1 is depicted. It will be recalled that in our first example a message was sent from station 1A to station 2B. The system operates that when the LANCE 15 receives the message it generates a buffer RAM request signal on line 51, which is transmitted to the buffer RAM arbitor circuit 53. The buffer RAM Arbitor is comprised of a programmable array of logic inte grated circuits which are commercially available and 130 in a preferred embodiment, are manufactured by Advanced Micro Devices Corporation. The BR Arbitor 53 generates a steering signal to the MUX (multiplexer) 55 so that the message from LANCE 15 can be transmitted along channel 57, through the MUX 55, along channel 59, to the buffer RAM data bus 61. The message is transmitted from the BR data bus 61, along channel 63, to the buffer RAM 29 and is located therein at an address specified by the signals on channel 65. It will be recalled that the LANCE 15 is provided with address information from the microprocessor 21 and in accordance with transmitting this message to the buffer RAM 29, as just described, the LANCE 15 transmits a set of address signals on Channel 67, through the latch 69, along channel 71 to the MUX 73. The MUX's 55 and 71 are each a 74S1 58 manufactured by Signetics Corporation. The MUX 73 has received a steering signal on line 75 to direct the address signals on channel 71 to channel 65. The BR Artitor 53 sends a start signal to the timing circuit which provides clock and read.iwrite signals to the buffer RAM 29. The buff er RAM 29, which in the preferred embodiment is a 8264 manufactured by Fujitsu Corporation, operates in response to clock and read/write signals.The microprocessor 21 has been programmed to fetch the destination address portion of the message by addressing the location in the buffer RAM whereal the destination address information is located. Therefore, assuming thatthe LANCE 15 has sent an interrupt signal as described earlier, the microprocessor will send address signals on the DAL bus 31, along Channel 79, to the MUX 73. In response to a BR request MP signal on line 81, the BR arbitor 53 will send a steering signal on line 75 to cause the MUX 73 to pass the address signals on channel 79. Accordingly the destination address portion of the message will be transferred from the buffer RAM 29, along line 63, along the BR data bus 61, along channel 83, through latch 85, to the microprocessor DAL 31. Hence the destination address portion of the message is transmitted from the buffer to the look up controller 37 described in connection with Figure 1. When the microprocessor requires the source address portion of the message, it fetches it the same way except, of course, that the address for the source address portion of the message is different.

When the microprocessor 21 has made a decision that the message, in our example, should be sent from the buffer RAM 29 (the message originally from station 1 A) to station 2B, then the microprocessor sends instruction signals on DAL 31, along channel 87, through latch 89, along channel 91 to the BR data bus 61, therefrom along channel 63 to the buff er RAM 29. Periodically the LANCE 15 will check the address locations in the buffer RAM 29 whereat such instruction signals are stored and when such instruction information is present, the appropriate signals are transmitted along BR data bus 61, along channel 93, through latch 95, through LANCE A DAL 97 to the LANCE 15. In response thereto the LANCE 15 sends address information to fetch the entire message from the buffer RAM 29, along channels as previously described. The message signals are transmitted along Channel 63, along bus 61, along Channel 99, GB 2 149 625 A 5 through latch 101, along DAL 103, to the LANCE 17 and therefrom to station 2B. The flow of address information and data information from LANCE 17 should be readily apparent from Figure 2 and it will not be discussed further.

It should be apparentthat if the microprocessor 21 decides not to forward the message from the buffer RAM 29, there will be no instruction to the LANCE via the buffer RAM as described above.

Consider Figure 3 which depicts the make up of the look up controller 37 of Figure 1. In Figure 3 the lines of the DAL bus 31 which carry data signals are separated out and appear as a data bus 107, while the lines of the DAL bus 31 which carry address signals are separated out and appear as an address bus 109.

It will be recalled from the discussion of the operation of the circuitry of Figure 1 that when the LANCE advises the microprocessor 21 that a mes sage is ready to be processed, the destination address signals of the message are fetched from the buffer RAM and brought to the memory controller.

Those destination address signals arrive on the data bus 107 of Figure 3. Prior thereto the microprocessor 21 has sent instruction signals over the bus 109, along channel 111 to the control circuitry 113. The control circuit 113 in a preferred embodiment is a 16136 Prograrnable Array Logic manufactured by Monolithic Memories. The control circuit 113 pro vides a control signal to the transceiver 115 and hence the destination address signals are passed through the transceiver 115 and loaded into the compare register 117. In the preferred embodiment the transceivers are 74LS245 devices manufactured by Signetics, while the register 117 is composed of 16114 PAL devices manufactured by Monolithic Memories. The register 117 in a preferred embodi ment is a 48 bit register but is should be understood that other bit length registers could be used, if other address configurations so required.

The look up controller circuit of Figure 3 under takes the comparison operation on its own, in response to starting address signals on channel 109 and a command signal on line 119. By way of example if the look up RAM 39A were designed to accommodate 8000 addresses then the microproces sor could be programmed to provide a starting address of 4000. The address signals for the address 4000 would be provided to the address generator 121. In accordance with the control signal on line 119, the address 4000 would be transmitted to the look up RAM 39A and the destination address at address 4000 would be transmitted along channel 123 to the comparator circuit 125. In this preferred embodiment the comparator circuit 125 is composed 120 of 16134 PALs manufactured by Monolithic Memor ies. The comparator circuit 125 does a parallel signal comparison with the destination address signals in register 117 and a result signal, indicating either "greaterthan" or "equal to" is transmitted on Channel 127 to the control circuit 113. If the result signal is "greater than",meaning thatthe destina tion address in the look up RAM is greaterthan the destination address from the buffer RAM, then the address generator in response to a control signal on line 119 will provide a second address of, for instance, 2000to hopefully find a closer match. If the result signal indicated neither "greater than" nor "equal to", the system would recognize that the destination address brought from the look up RAM 39A is "less than" the destination address from the buffer RAM and hence the address generator (in response to a control signal from control circuit 113) would generate a higher signal, perhaps the address 6000. This process would continue until the selected destination addresses in the look up RAM 39A have been compared with the destination address in the register 117. Two possible results can occur. In a first instance there could be a match somewhere during the comparison and at that time an "equal to" signal would be generated on line 127. In response to the "equal to" signal the address generator would halt generating new addresses and would hold the last address for further use. In response to the "equal to' result the address generator 121 sends the address it has stored but also the RAM 39B so that the destination address with the additional information (i.e. location as to A or B network and clock value) from the RAM 3913, is sent to the microprocessor.

The destination address from the address generator 121 is transmitted over channel 128, through transceiver 130, along channel 107 to the microprocessor. The transceiver is controlled by a control signal on line 132. The additional information is transmitted from the RAM 3913, along channel 131,to the bus 107 and therealong to the microprocessor.

When the source address is compared, as explained in the discussion of the circuitry of Figure 1, if there is neither an "equal to" nor a - greater than" in response to a predetermined number of comparison tries, then the system will assume that the source address is not present in the RAM 39A and will take steps to add the source address to the look up RAM as an additional destination address. In a preferred embodiment this predetermined number (of comparison tries) is the log to the base 2 of the number of entry positions in the RAM 39A. If the predetermined number is reached and no match has been found then the control circuit sends a signal on line 111, back to the microprocessor which turn fetches the source address from the buffer RAM 39 to the new source RAM 35. However at that time there is "additional information" entered into the new source RAM to accompany the source address.

The additional information hereinafter called the additional address is the address located in the address generator 121 when the "comparison tries" become exhausted. The system assumes that such an address is as close as the system can get and should be used for a starting address during the routine when that said source address is added to the RAM 39A. At some point in time, either because it is deliberately programmed, or when the microprocessor is programmed to recognize some "non busy" time, the micr ' oprocessor will reorganize the entire RAM 39A and during that reorganization add the station addresses from the new source RAM 35, in response to said additional addresses, associated with those station addresses. This operation is accomplished using the circuit of Figure 3 as de- 6 GB 2 149 625 A 6 scribed below.

Starting with the high order addresses generated by the address generator (and in response to control signals on line 119), the destination addresses and their respective additional information are fetched from RAMS 39A and 39B. The destination addresses from the RAM 39A are transmitted to the register 117 while the additional information is transmitted along channel 131 to the bus 107. The additional informa tion is transmitted to the microprocessor and is examined in the microprocessor for zero value in the clock portion of the additional information. If the destination address is still viable, the additional information is returned on Channel 107 and both the destination address in register 117 and the addition- 80 al information are returned to the address provided by the address generator 121, which address loca tion is one address location higher than it was when the information was fetched from RAMs 39A and 39B. In this way the entire content of the RAM may be moved one address space at a time toward the higher address locations of memory. This is possible because the unused part of memory is at the high order end. The address information from register 117 is transmitted through the transceiver 94, along channel 127 to the look up RAM 39A.

However when the microprocessor is in the reor ganization mode for source address entry, it ex amines the address generator address at each step and when the address, in the address generator, is equal to an "additional address" of a source address, (as described above) in the new source address RAM, that source address is added to the RAMS 39A and 39B, at the address location present in the address generator. In effect the new destina tion address (from the source RAM) which is added to RAMS 39A and 39B is in the best location as determined during the source comparison (ex plained above). If there are, for instance, three new source addresses to be added during a reorganiza tion, the microprocessor can be programmed to cause the address generator 121 to generate a first address which is three address positions higher than the high order address. When the address in the address generator equals an "additional address" of a source address, the pattern of the address gener ator will be changed to provide an address of two higher, and upon a second match to provide an address of one higher, and upon a third match to provide no change. Diff erent formats for reorganiz ing the RAM could be employed and programmed forthe microcomputer. The significant matter is that the look up controller provides data paths and control signals to effect a loop operation, with destination memory addresses to provide a reorga nization.

It should also be understood that the circuitry of Figure 3 can be used to examine the entire contents of RAMS 39A and 39B and purge the RAMS 39A and 39B of non viable addresses. The manner in which this is done is that the address generator, under instruction from the control circuit 113, and a starting address on channel 109, starts at the lower order address of the RAMS 39A and 39B. As explained before the additional information from 130 39B is examined and if the clock value is zero, the address counter is advanced to the next higher address but the information from the register 117 is not read out and is in fact written over. This non read out is effected by a control signal on line 133. The destination address from the next higher address in the look up RAM is reloaded into the previous address (by having the address generator decremented one address after detecting the first zero clock value). The address generator will follow a program from the miroprocessor to fill in the vacant positions in the RAMS 39A and 39B as non viable destination addresses are dropped as explained above. Accordingly the RAMS 39A and 39B get purged of non-viable destination addresses.

Claims (14)

1. Abridge circuit for interfacing at least first and second local networks, each of which networks has a plurality of stations and each of which stations is formed to send messages that include at least a destination address and a source address, comprising in combination: first logic circuitry means, including tridirectional data transmission path means, connected to said first and second local networks to receive data messages therefrom and formed to have a first data storage means to temporarily store said messages, said first logic circuitry further formed to examine a message sent thereto to determine if said message should be further considered for further transmission, at least to the one of said local networks not sending said message, and still further formed to generate interrupt signals, respectively indicative of which of said first or second local networks is transmitting said message; data processor means connected to said first logic circuitry and having at least two interrupt signal ports and including means to enable said data processor to be programmable; first memory means which has stored therein destination addresses, and network data indicative of which network is associated with each destination address, for at least part of the stations connected to said local networks; second logic circuitry connected to said first memory means, and to said first logic circuitry, and to said data processor whereby in the event it is determined that said message should be further considered, said data processor will cause at lqast said destination address portion of said message to be brought from said first data storage means to said second logic circuitry whereat it will be compared with said destination addresses stored in said first memory means to determine whether said message should be sent to a station connected to a network which did not initiate said message.

2. Abridge circuit according to Claim 1 wherein said first logic circuitry includes a first signal bus, as part of said tridirectional data transmission path means and wherein said data processor and said second logic circuitry.are connected to said first signal bus.

3. Abridge circuit according to Claim 2 wherein there is further included a second data storage means connected to said first signal bus and wherein said data processor is formed to address said first 7 GB 2 149 625 A 7 data storage means to fetch therefrom source address information to be sent to said second logic circuit whereat it is compared with said destination addresses stored in said first memory means and if no match is found said source address information is 70 sent and stored in said second data storage means.

4. Abridge circuit according to Claim 3 wherein said data processor is formed to generate said network information for said source address to be stored therewith in said second data storage means. 75

5. Abridge circuit according to Claim 1, 2 or3, wherein said data processor is formed to add time value information to said destination address infor mation as stored in said first memory and formed to decrement said time value periodically to provide a basis for determining the activeness of destination addresses so stored.

6. Abridge circuit according to Claim 5 wherein there is further included a timer circuit means to generate periodic interrupt signals, said timer circuit means connected to a third interrupt port of said data processor whereby said data processor eff ects said clecrementing in response to said interrupt signals from said timer circuit means.

7. Abridge circuit according to Claim 2, or any of Claims 3 to 6 when appendant thereto, wherein said first logic circuitry means includes first and second controller circuits for local area networks (LANCES) with each LANCE respectively connected to first and second date-address buses (DALs) and wherein each of said first and second DALs is connected bidirec tionally through control logic to said first data storage whereby if it is determined that a message should be sent to a station on a network which did not initiate said message, said message will be fetched from said first data storage and transmitted to the DAL of said network not initiating said message.

8. Abridge circuit according to Claim 7 wherein each of said LANCES is formed to generate address signals which when sent to said first data storage means will cause said message to be fetched from said first data storage means.

9. Abridge circuit according to Claim 8 wherein said first data storage means includes a second signal bus to which at least a portion of said first control logic is connected and wherein there is further included second control logic disposed to connect said second signal bus to said first signal bus whereby said data processor can send instruc tion signals to said first and second LANCES to cause each of them at an appropriate time to send address signals to said first data storage means.

10. Abridge circuit according to any preceding Claim, wherein said second logic circuitry includes comparator means and register means connected thereto whereby address information signals from said first data storage means are received by said register and destination address information signals from said memory means are received by said comparator to be compared with said address signals in said register and wherein said comparator is formed to generate a result signal.

11. Abridge circuit according to Claim 10 where in there is further included a comparator control circuit connected to said comparator to receive said result signals and in response thereto generate control signals which will cause said second logic circuitry to continue making comparisons and alternatively to terminate said comparisons.

12. Abridge circuit according to Claim 11 wherein said second logic circuitry includes an address signal generator connected to said memory means to generate address signals therefor and transmit them thereto and wherein said address signal generator is connected to said comparator control circuit to cause said address signal generator to continue to generate new addresses and alternatively to terminate generating new addresses.

13. Abridge circuit according to Claim 12 wherein said data processor is formed to cause said address generator to start generating addresses at a high order address and shift the destination address information signals through said second logic cir- cuitry to higher order addresses until a source address in said second data storage means is equal to a vacated address in said memory means and whereby said source address information signals will be stored in said vacated address.

14. Abridge circuit substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.

Printed in the UK for HMSO, D8818935,4,85,7102. Published by The Patent Office, 25Southampton Buildings, London, WC2A lAY, from which copies may be obtained.