GB2148562A - Computers - Google Patents

Abstract

Conventional computers are based on the architecture devised by Von Neumann et al. The main stumbling block in computer design at the moment appears to be program control; it is not easy to match this to the requirements of a rule-based expert system. The invention proposes a method of controlling a computer in which all program control is performed by a "pseudo-associative" process, a fast table lookup technique being implemented (preferably in hardware) (2) to select the correct rule, whereupon the application of the rule modifies the conditions and the pseudo-associative process is used to find a new rule . . . and so on. The procedure to be performed at any given time is selected, from a limited number of possible procedures, upon the basis solely of the result of the previous procedure, this result being available (26) as a number value (the computer's "state" after affecting the previous procedure) that is hashed (24) according to some predetermined algorithm to identify the correct following procedure. <IMAGE>

Description

SPECIFICATION Computers This invention concerns computers, and relates in particular to a novel way of constructing and controlling a computer.

The term "computer is commonly used to mean a stored program binary digital electronic computing device. More generally, however, a computer is merely a device that accepts an input of some sort, does something with that input in accordance with certain rules, and then provides as a result an output of some sort-a distinguishing feature of the computer over other machines fulfilling these criteria being that at the more basic levels the operations a computer carries out are calculations of a numerical nature. It is not so far from the truth to say that the almost unbelievable complexity of modern computing systems is based upon nothing more than the ability to add and subtract numbers extremely quickly.

The trend in computer programming is towards the so-called "expert systems'', and one of the favoured approaches to expert system programming is the rule-based method, in which there is set up a collection of rules of the type: "if this is so and that is so then do . . . ''. There is a separate rule for each situation, and the expert system works by finding the correct rule at any time and applying it. Often the choice of rule is ambiguous, and several "chains" of reasoning have to be followed until the best solution is found.

Conventional computers are based on the architecture devised by Von Neumann et al in the 1 940s and 1 950s. At the time the emphasis in computer applications was on calculation (computer power was expressed in terms of the speed in which complex expressions could be evaluated), but around the 1 960s it became apparent that other applications were feasible, and the modern general purpose computers came into being. The main stumbling block in computer design at the moment appears to be program control, and when there are considered the requirements of a rule-based expert system the shortcomings are obvious. Conceptually, a rulebased system is a set of unconnected rules in no particular order, and when a condition is matched the appropriate rule is executed.This is not so easy on a conventional computer, in which the rules are held in a table which has to be searched a slow process-to locate the correct rule, even when the whole is speeded up by using an 'associative' memory to hold the rules.

The invention concerns a method of controlling a computer in which all program control is performed by a "pseudo-associative" process, a fast table lookup technique being implemented (preferably in hardware) to select the correct rule, whereupon the application of the rule modifies the conditions and the pseudo-associative process is used to find a new rule. . and so on. This approach may have applications in many fields-for example, in pattern recognition, speech recognition and artificial intelligence in general.

Modern electronic computers are all constructed in much the same way. In a gross sense they are composed of four main parts, namely an input device, a store, a processor and an output device. The input device (a keyboard, for example) allows data and instructions to be fed into the computer; the store (the computer's memory) allows data and instructions to be kept handy until required; the processor does the actual manipulation of the data in accordance with the instructions; and the output device (a television-type visual display unit, for example, or a teleprinter) allows the computer to display the results of its computation. Each of these four parts is itself a combination of suitably inter-connected parts.For example, the processor---com- monly known either as the Central Processing Unit (CPU) or Data Processing Unit (DPU}is generally composed of an Arithmetic and Logic Unit (ALU), which contains both a register (a store-type device) known as the Accumulator, in which are held the numbers on which the ALU is presently working, and a Sequence Control Unit (SCU); this latter includes a Program Counter (PC), also known as a Sequence Register (SR), and an Instruction Decoder.

These various parts are employed in the performance of the operations the computer is required to carry out, and it is convenient at this point to describe the various levels of operation that are effected by or within a computer.

1. At the highest, or user, level, the computer is merely a tool, performing some job or task at the bidding of the user. The job might be searching for new Prime Numbers, running a Nuclear Power Station, or playing Space Invaders.

2. Next is the high level language level, at which the computer receives and acts upon instructions provided in a human-like language, each such instruction, or statement, needing to be translated into a multiplicity of much simpler instructions at the next lowest level, the machine code level. Typical high level language instructions are to display text on a video screen, to asign some value to a variable name, or to open a data file for reading information therefrom.

3) The machine code level is the level of the low level language, in which one instruction to the computer causes it to perform (more or less directly) one action. It is at this level that the operations a computer performs start to become dependent upon the computer itselfupon the way it is constructed and operates internally. Typical machine code instructions are load a storage register with a number, read the data present at an input port, or add into one storage register the contents of another.

4) The Fetch/Execute cycle level follows the machine code instruction level. Before any machine code instruction can be carried out it must be read in and a decoded to find out what it means. To do this, the computer-more specifically, the Central Processing Unit-performs a Fetch/Execute Cycle in which there is Fetched the instruction, it is decoded, and it is then Executed. This may mean reading in some data associated with the instruction.

5) While one machine code instruction does indeed cause one Fetch/Execute cycle, the fetching and execution themselves involve many operations at the next lowest level-the bit level in which bits (individual on/off signals) are transferred around the components of the computer to cause data to be shuttled in, through and/or out of storage registers. Typical operations at the bit level are putting an address on the address bus, connecting a storage location to the data bus, copying data in one register to another, shifting all the bits in one register up one, or performing a logic operation upon the contents of two registers.

6, 7) Beyond the bit level lies the logic circuit level a collection of individual logic gates that is used to store or control the flow of bits (depending upon their typeFwhile at the level of the gates themselves are found collections of individual switching devices (nowadays semiconductive devices such as diodes and transistors) that enable signals to be routed one way or another through the gate.

8) Finally, beyond the gate level lies the switch level, at which a first flow of electrons in a device is used to control a second flow of electrons in the device (the diode or tranmitter itself).

It will be apparent that the switch, gate and logic circuit levels are concerned primarily with the hardware of the computer, while the bit, Fetch/Execute cycle, machine code and high level language levels are concerned primarily with the software overseeing the operation of the computer. This invention is not concerned with operations performed within a computer at the hardware levels, nor is it concerned with operations performed with or by a computer at the user level. It is instead concerned with such operations as take place at the software levels.These are the levels at which the computer recognisably receives and carries out instructions; at the bit level single circuit switching operations-the microcode are effected, at the Fetch/Execute cycle level collections of bit level operations are effected, at the machine code level collections of Fetch/Execute cycle operations are effected, and at the high level language level collections of machine code level operations are effected.

As pointed out hereinbefore, present-day computers have various interconnected parts one of which is a Sequence Control Unit. This SCU determines at the bit and Fetch/Execute cycle level which operation the computer will execute next, and in today's computers this is affected by the SCR using a special-purpose Register known as the Program Counter which contains a number identifying the Memory Location holding the (or the start of the) next instruction the Processor is to obey. This matter of a Program Counter, central to the invention, is now explained in more detail.

Computer Programs may either be written in a low level language (machine code, or its slightly more human-readable version, assembler) or in a high level language. High level languages are designed to be more or less readily understood by humans, and contain instructions each of which results in many operations at the machine level; they therefore have to be translated (compiled) or interpreted before the machine can understand them. A machine code language, on the other hand, is one in which each instruction given to the computer matches much more closely an operation the computer is able to effect more or less directly, without translation or interpretation, as a result of the way it is constructed.Machine code languages commonly employ numbers (which may be binary, octal, decimal or hexadecimal, for example) to identify the instructions; modern electronic computers actually operate in binary, and thus the computer's structure incorporates both a number conversion system, converting where necessary the instruction number to binary format, and an Instruction Decoder (mentioned above) that selects the particular bit level operation (or set of operations) identified by that number. A significant step in the development of computing devices was the realisation that there is no intrinsic difference between numbers defining the data the device is to work on and the numbers defining the instructions--the Program-telling it what to do with that data. As a result, a modern computer is a "stored Program" device, in that it contains within itself a store, analogous to human memory, in which it retains, distinguished merely by their location, both the data and the Program. By way of illustrating this idea, the following Program, written in a mythical machine-code-type language for a mythical computer, shows how two numbers may be added and the result stored by this type of computer.

Location Content Store (Instruction Decoded Instruction Location Code or data) (if appropriate) X 1 Copy into the Accumulator the number in the Store Location having the number in the next Store Location 2 15 3 3 Add to the number in the Accumulator the number in the next Store Location 4 2 5 2 Copy the number in the Accumulator into the Store Location having the number in the next Store Location 6 16 7 20 Stop 8 0 Do nothing 9 0 Do nothing 15 1 16 0 The instructions to the computer are represented by numbers (0, 1, 2, 3... 20) that are intrinsically indistinguishable from the numbers used as the data upon which the computer's processor is to operate.The processor knows which is which, however, because each instruction implies whether the next number is to be treated as data or not (and if not it is also an instruction); the first number in the sequence is always treated as an instruction. Thus, the instruction with the code 1 (meaning "Copy into the Accumulator the number in the Store Location having the number in the next Store Location") is a two-location instuction, and the number in the second location is not the code for an instuction but is instead data (the number-the address--of the Store Location that is holding the number to be added to the Accumulator). On the other hand, the code 20, meaning "Stop", is a one-location instruction.

In this simple example it is assumed that the processor operates upon the contents of the Store Locations (some as instructions, some as data), taking the locations in sequence 1, 2, 3... 6, 7. It is in fact a counter-the Program Counter (PC9in the Sequence Control Unit (SCU) that dictates which Store Location is accessed next, and the PC is automatically incremented as each location is accessed.In what is known as a "Fetch/Execute cycle" the processor fetches the number stored in the Location presently pointed at by the PC, then the PC is automatically incremented to point to the next Store Location, and then the processor executes the instruction it has received-which may be to fetch the next number (the number in the next Store Location) or it may be to do something, perhaps with the numbers it has already fetched. Possibly the key to the whole concept of present-day computing is the fact that the operation the processor executes may change the value held in the PC itself, so causing the PC to point, and the Program to "jump", not to the next Store Location in the original sequence but to some quite different Location.This jump may be conditional upon some event; in the previous simple example the following steps could replace those originally given (from 7 on) and so continue the addition until the result was greater than 100.

Location Content Store (Instruction Decoded Instruction Location Code or data) (if appropriate) 7. 10 Compare the number in the Accumulator with the number in the next Store Location 8 100 9 15 If the Accumulator number is less, jump to the Store Location having the number in the next Store Location, and treat its contents as an instruction. Otherwise, jump to the next-but-one Store Location, and treat its contents as an instruction 10 3 11 20 Stop 12 0 Do nothing 13 0 Do nothing 14 0 Do nothing 15 1 16 0 Assuming that the Program is at a stage when the number in the Accumulator is less than 100 (the number in Store Location 8), the two-location instruction in Locations 9 and 10 is dealt with as follows.

(i) The PC is at 9.

(ii) The number in Store Location 9 is fetched.

(iii) The PC is incremented to 10.

(iv) The fetched number is known to be an instruction. It is therefore decoded, and found to mean (in part) "Fetch the number in the next Store Location".

(v) The number (3) in Store Location 10 is fetched.

(vi) The PC is incremented to 11.

(vii) The full instruction is now executed-the check is made, the Accumulator number is less, and so the PC is altered to 3.

And here the Program jumps backwards, and continues as follows: (viii) the number in Store Location 3 is fetched.

(ix) The PC is incremented to 4.

(x) The fetched number is known to be an instruction. It is therefore decoded, and found to mean (in part) "Fetch the number in the next Store Location".

And so on. The loop around locations 3-10 continues until the Accumulator number is not less than 100, whereupon the SCU remains unchanged at 11, and Program Execution continues by fetching the number (known to be an instruction code) in Location 11.

Most present-day computers work in this fashion. At this level they perform a sequence of operations each of which consists of a Fetch/Execute cycle in which the Processor fetches from Store (or perhaps from an input device, such as a keyboard) a number that is interpreted as either an instruction code or data (as appropriate; an Execute may involve none, one, two or more subsequent Fetches all combined with the original one into respectively a one-, two-, three-part... instruction), and each time one such Fetch is effected a Counter in a Sequence Control Unit is automatically incremented to point to the next Store Location, so identifying where the next Fetch goes to. At this Fetch/Execute cycle level, then, the operation of the computer is the sequence: 1. Fetch the next instruction (from the location currently pointed at by the Program Counter); 2.Increment the PC; 3. Decode the instruction; 4. Execute the instruction-which may involve further fetches and PC increments, and may finally involve resetting the PC to point not to the incrementally-next location but to some quite different location.

And so back to Stage 1), and Fetching the next instruction.

Almost without exception any complex task may be broken down into simpler and simpler parts, and eventually into parts that can in turn be broken down into individual instructions and thus Fetch/Execute cycle operations--of this nature. Moreover, in just the same manner each Fetch/Execute cycle operation can by and is-broken down to the final "software" level, the bit level, (which software may either be "hard wired" or be a microprogram stored in a a special area of memory) at which the transferring of data signals within the computer around its circuitry is actually carried out.

Bit level is the level within a computer at which data is "transferred" from one location to another-the level at which the contents of registers are modified. There are, basically, only a relatively limited number of things that can occur at this level, and some of these are as follows: Connect a Register to the Address Bus (so putting the contents of that Register on the Bus as an address, and having the system prepare to direct Data to or from whatever Register, Memory Location, I/O port, device etc. is represented by that address).

Connect a Register to the Data Bus (so enabling the system to direct Data to or from that Register).

Issue a "perform" signal of the appropriate kind (for example, a Read/Write signal to Memory will cause the Memory Management System to copy Data from an addressed Memory location onto the Data bus, or to copy Data from the Data Bus to an addressed Memory Location).

Perform a Combinational Logic operation upon the contents of two Registers (e.g., add, subtract, AND or OR the contents).

Operations at the bit level are operations that transfer data internally around the computer, and involve the modification of the contents of individual Registers. It is these operations that the invention at its most basic seeks to control, and for the purposes of this Specification the term "procedure" is used to mean a sequence of bit level operations that results in the contents of a Register being modified. It will be apparent that a procedure may contain one only bit level operation (incrementing a Register, say), may contain a few such operations (as in a Fetch/Execute cycle) or may contain many (as in the series of sequential Fetch/Execute cycles necessary to interpret and act upon a single high level level language instruction).

It should by now be apparent that the operation of present-day computers is dominated by the use of a Sequence Control Unit (SCU) containing a Program Counter that is incremented automatically, to point to the next Store Location (at which is stored either the next machine code instruction to be effected or the Data on which the present instruction is to work) until it is reset by the operation of the Program itself causing a jump to some other location. Such a jump may or may not be dependent upon the result of the procedure most recently carried out, but in either event the Program either makes the jump or continues with the procedure beginning with the instruction in the relevant next subsequent Store Location.Thus, it is normally the case that at any level a Program has a Kernel in the form of a sequence of instructions to be carried out one after the other, and that on occasion control is transferred from one part of this sequence to another (or perhaps to a second Program sequence a "subroutine' 'at the end of which it is transferred back again to the next instruction in the main sequence). This type of arrangement, satisfactory though it has proven so far, is, as pointed out hereinbefore, not ideally suited to the modern rule-based Programs used in expert systems, for overall such Programs are made up of a set of unconnected procedures, in no particular order, without any need for a conventional instruction sequence Kernel binding them together. The present invention seeks to provide a novel design of computer, and mode of control of computer operation, in which by contrast the next procedure is not determined by its position in a sequence of procedures (thus, by its being defined in the next series of Store Locations), and instead the procedure to be performed at any given time is selected, from a limited number of possible procedures, upon the basis solely of the result of the previous procedure, this result being available as a number value (the computer's "state" after effecting the previous procedure) that is hashed according to some predetermined algorithm to identify the correct following procedure.

In one aspect, therefore, the invention provides a method of controlling the internal operation of a computer, in which: a) all possible valid internal operations to be carried out by the computer are defined as a set of procedures (as hereinbefore defined); b) the result of each procedure determines the state of the computer following that procedure, and the next procedure is selected on the basis solely of the current state; c) the selection of the next procedure is effected by hashing the current state, and using the result to identify the next procedure; and d) initialisation of the next procedure so identified is dependent upon a check that it correctly follows the current procedure, and failure of this check causes a re-hash and re-selection, this being repeated until either the correct next procedure or an empty (error) procedure is found.

Where there is no preceding procedurc that is, when the computer is started (initialized) and the procedure to be selected is the first procedure an artificial "result" of the (non-existent) preceding procedure is constructed in some predetermined fashion. Specifically, it is arranged that on switch-on the computer's state is set to some predetermined value. An embodiment of this is discussed in more detail hereinafter.

The term "computer" generally means, as mentioned hereinbefore, a computing device that accepts an input, has a processor operating upon that input, and provides as a result an output.

More specifically, but not exclusively, it means a stored program binary digital electronic computing device having an input means, a store, a processor, and an output means, and these parts may be like any of those used or suggested for use in the Art save that any Sequence Control Unit in the processor will not rely solely upon an automatically-incremented Program Counter for determining which instruction is next to be effected.

As has been mentioned above, the Central Processing Unit (CPU) of a present-day electronic computer commonly consists of an Arithmetic and Logic Unit (ALU), several arithmetic Registers, an Instruction Decoder (ID) and a Sequence Control Unit (SCU) which itself contains a Program Counter (PC) and an Instruction Register (IR). All these components are interconnected in various ways, and the CPU is itself connected both to Memory (by Address and Data Buses) and to a number of "external" devices (such as a VDU, a keyboard, and a Printer). The effective structure of the CPU of a computer operated in accordance with the invention, however, is somewhat different-it is reorganised internally to perform different operations.Thus, it contains what may be called a Data Processing Unit (DPU), generally corresponding to the ALU and its associated arithmetic Register, an Instruction Decoder (ID) and a Sequence Control Unit (SCU-also referred to as an Address Processing Unit, APU), and the SCU/APU itself contains an Instruction Register (IR), a Hash Function Generator (HFG) and a number of State Registers (SR). Moreover, Memory is divided into a conventional Data area and a Hash Table area. The interconnection of these components is such that the SR sends data to the HFG, the HFG can address, and so send data to and receive it from the Hash Table area of Memory, and the HFG can address the Data area of Memory. The mode of operation of a CPU in accordance with the invention is described in more detail hereinafter.

While the computer's processor does not make use of a Sequence Control Unit having a Program Counter in the accepted sense for pointing to the Store Location where there is held the first operation to be performed in carrying out the next procedure, nevertheless it may use a Program Counter for the operations within each procedure, and in a very similar fashion it must necessarily be able to use the result of the preceding procedure to indicate which procedure is next to be effected. Accordingly, it does employ a Sequence Control Unit (SCU), and the SCU contains one or more counter (Register) one of which may be a Program Counter, and the values in some or all of these counters are adjusted, as part of the preceding procedures, to indicate the new state and thus which is the next procedure to be effected.The contents of these SCU Registers therefore correspond toand are in effect analogous tithe actual result of the procedure; in the following, they are referred to as the "state" of the computer, and it is this state that defines which procedure is next to be effected.

As pointed out above, upon initialization there is constructed a predetermined state (the "result" of the non-existent preceding procedureFthat is, the relevant State Registers in the SCU are given predetermined contents, so causing the computer always to start with a defined state, and thus always to perform the same first procedure. It will usually be the case that, upon start-up, the Registers will automatically hold zero (their power-off condition), so that the first procedure the computer is to perform can reliably be that defined by a "zero" state.

In the method of the invention all possible valid operations to be carried out by the computer are defined as a set of procedures (these thus being the only procedures defined). At the bit and Fetch/Execute levels the operations/procedures the computer carries out are those associated with its routine internal working, such as scanning the keyboard for a keypress input, writing data to some external device (a VDU screen, say, or a printer), or checking an internal timer to find out whether to execute an interrupt routine. At the machine code and High Level Language levels the procedures are of course more complex (though eventually they break down into a sequence of the lower level operations), and depend upon the Program the computer is running, and thus on the purpose for which the computer is being used.Examples of High Level Language procedures are displaying on a VDU the contents of a variable, reading into memory a disk file, and evaluating some arithmetical expression.

Regardless of the nature and complexity of the procedures, however, each may be regarded simply as a rule defining how and under what circumstances one particular start state is changed into a corresponding end state. Each such rule may then be depicted as the two states plus the relevant conditions-for example, < NEW STATE > < < OLD STATE > < CONDITIONS > (in which the content of the terms is self-evident) means that under the identified conditions the new state results from the old state (confusingly, but for historical reasons, and to fit in with the useage in Formal Language Theory, the arrow points not to be result but to the initial situation!).

This symbology is used in the Example discussed herinafter.

In accordance with the invention the result of each procedure determines the state of the computer following that procedure, and the next procedure is selected on the basis of the current procedure's state. This part of the method of the invention may perhaps more easily be understood from the following simple example in which six procedures each of which manipulate the variables A and B are applicable, and which is chosen is dependent upon the value for the variable A at the end of the previous manipulation (that is, the state is defined by the value of A). The example is shown in two forms-first (and not in accordance with the invention) as an endless loop through a series of conditional statements wherein the values of A and B are tested and manipulated, and next, achieving exactly the same results but this time in accordance with one feature of the invention, as a series of procedures selected by jumping at the end of each procedure, in accordance with the state, to that procedure having the number corresponding to the value of A. In both cases the initialisation on switch on is omitted, and it is assumed that the initial state (the very first value of A) is always zero.

Endless loop Condition Manipulation Results/State Directive START HERE: IF A=0 1) Assugn randomly to A ) the value of any ) positive integer less ) than 6. A=? ) 2) Set the value of B ) to zero. B=0 ) ) IF A=1 Double A. A=2 ) ) IF A=2 Square A. A=4 ) ) IF A=3 1) Add to A the value ) Go to Start of B. A=? ) 2) Increment the value ) of B. B=? ) 3) If the value of B ) exceeds two, reduce ) it to two. ) ) IF A=4 Decrement the value of ) A by one. A=3 ) ) IF A=5 Set the value of A to ) zero. A=0 ) Procedure Next No.Manipulation Result/State Procedure O 1)A = Random Positive Integer < 6 A = 2)B = O B = 0 1 A 2A A = 2 2 2 A t A2 A = 4 4 3 1)A = A+B A = 2)B = B+1 B = 31f B > 2 then B = 2 4 A = A-1 A = 3 3 5 A=O A=O O At the Start A can randomly be set to 1, 2, 3, 4, or 5. If set to 1, the sequence occurring is as follows: A values B values old new old new 0 1 0 0 (i) 1 2 0 0 (ii) 2 4 o o (iv) 4 3 0 0 (iii) 3 3 0 1 3 4 1 2 4 3 2 2 3 5 2 2 (v) 5 0 2 2 (select new random A) In this particular case, if the randomly chosen value of A is 2, 4 or 5 then the sequence occurring is that starting at (ii), (iii), (iv), or (v) respectively.

The example just given is a trivial one, but nevertheless illustrates how the choice of the procedure next to be carried out is selected upon the basis solely of the result of the preceding procedure. A more complicated example is discussed in greater detail herinafter.

The method of the invention requires that the selection of the next procedure be effected by hashing the current procedure's state, and using the result to identify the next procedure. This may be explained as follows.

In the example just given it is postulated that the result of any procedure is a number the actual value of which is used directly to identify the next procedure. Thus, if the result is 4 then the next procedure to be implemented is procedure 4. It is convenient hereinafter to consider that the instructions for each procedure are kept in a box, and the boxes have simple consecutive addresses1, 2, 3. . etc. Thus, procedure 4 is kept in box 4, and all that is necessary is to go to box 4, take out the instuctions, execute them, find out what procedure is identified by the result, go to that box, . . . and so on.

The simple example uses six procedures (0 to 5), so there are in effect six boxes, and it assumes that the range of the numbers generated by each procedure (that is, the range of values for the "state" of the computer after each procedure has been executed) is the same as the number of boxes-that is to say, if the generated number can be any whole number in the range 0 to 5, so that there are six numbers in all, then there are six boxes. In reality, however, this "coincidence" is unlikely to occur; a simplified but more realistic situation would be one wherein the generated numbers were 0, 2, 4, 6, 8 and 10 still only six numbers, so requiring only six boxes, but having a range (0 to 10) of eleven.If then, there is to be a box with a number the same as each generated number, and yet these boxes are to be in a series of boxes having consecutive addresses, there must also be boxes with the numbers 1, 3, 5, 7 and 9and these odd-numbered boxes, which are empty (because all allowable procedures result in even numbers, not in odd numbers) may represent a significant quantity of wasted memory. The solution to this problem is in principle simple: it is to manipulate the generated numbers in such a way as to form a new set of numbers the range of which does correspond---or more nearly corresponds-to the maximum necessary number of boxes.In this particular case the manipulation is simple, for if each generated number is halved then the resulting series of numbers is the six numbers 0 to 5, which exactly fits with only six boxes also numbered 0 to 5.

This method of reducing the range of one set of number to match more closely a second set of numbers with a smaller range a concept referred to as "mapping" one set onto the other-is known as "hashing", and the formula chosen to convert each number in the former range to its corresponding value in the latter range is the "hashing algorithm". The mapping of one set of numbers onto another using the hashing technique is well known in the Art, and a useful discussion of it is given in "Compiler Construction for Digital Computers" by D. Gries (published by Wiley). Nevertheless, as it is a central part of the present invention it is worth considering further at this point.

In the invention, the state at the end of one procedure is hashed to identify the next procedure. The identity of this next procedure is stored as an entry in a hash table; the table consists of a whole series of entries each one preceded by a tag representing the state value that should have been hashed to reach that entry. Implementation of the identified procedure is only begun after a check that it is indeed the correct procedure and if the check reveals that it is not then, as described hereinafter, the present state is rehashed to identify another procedure which, it is hoped, will be the correct one.

There are dozens of different types of hashing algorithms, and some fit a problem better than others. In the simple one mentioned above the algorithm was merely to halve the generated number, but in reality it is unlikely that the generated numbers will be so conveniently arranged, which means that more complicated algorithms will be needed. One such, commonly used, is to decide how many generated numbers there can be, find the nearest prime number greater than that number of generated numbers, and then divide each generated number by that prime number and use the remainder as the identifying value (because the next greatest prime is chosen, the number of possible remainders will always be greater than the number of possible numbers).For example, if there are 8 possible generated numbers (let us say, 1, 5, 7, 10, 13, 15, 19 and 22), the nearest greater-than-8 prime number is 11, each actual generated number is divided by 11 to give a remainder (in this case, 1, 5, 7, 10, 2, 4, 8, 0; using mathematical terms these are the remainder modulo 1 1), and it is the remainder that identifies the original number. So, whereas the range of the generated numbers is from 1 to 20, even though there are only eight of them, the hashing technique has reduced this to from 1 to 11.The two sets of numbers may be displayed in tabular form (the result is known as a "hash function"), thus: Hash Function Original Hashed Number Value 1 1 5 5 7 7 10 10 13 2 15 4 19 8 22 0 Finally, the method of the invention requires, as is so in all hashing system, that initialization of the next procedure so identified be dependent upon a check that it correctly follows the current procedure, failure of this check causing a re-hash and re-selection which is repeated until either the correct next procedure or an empty (error) procedure is found. In this simple case discussed so far care has been taken to avoid having two original number that hash to the same value (as both 5 and 16 hash to 5, this being referred to as a "collision"). In reality, however, collisions are usually unavoidable, and while the hashing algorithm is chosen to minimise the chances of them occuring steps must be taken to deal with them when they do occur. One convenient way to deal with collisions is to allow one of the two numbers to have the colliding hash value, and to re-hash the other using another algorithm that produces a different hash value and to keep re-hashing until there is no longer a collision. A possible re-hash in the above example is simply to add one to the second original value (16 + 1 = 17) and hash again using the same algorithm (remainder modulo 11), giving the value 6, which does not collide with any other hash value.If, however, the original number 22 had instead been 29, this would first have hashed to 7 (and collided with the hash value for 7), then it would have rehashed to 8 (29 + 1 = 30, remainder modulo 11 = 8), which collides with the hash value for 19), and finally would have re-hashed again to 9 (29 + 1 + 1 = 31, remainder modulo 11 = 9), which does not collide with any previously-computed hash value. So, with the original numbers 1, 5, 7, 10, 13, 16, 19 and 29 the hash function would be: Hash Function Original Hashed Number Value 1 1 5 5 7 7 10 10 13 2 16 6* 19 8 29 the asterisks signifying the number of re-hashes necessary to find the correct hash value.

Hashing (and re-hashing) may result in there being found an empty entry-that is, a box with nothing in it-which is clearly an "error", indicating that the state generated by the current procedure results from some incorrect input or earlier state. It might be, however, that an erroneous state hashed, and re-hashed, to a whole series of values none of which identified an empty entry-indeed, that the whole hashing operation became circular, going round and round endlessly. While it may be possible to design a hashing (and re-hashing) algorithm that avoids this, another-and probably better-solution is to count the number of re-hashes needed to find the entry for any particular state, and to declare that state an error state if a relevant entry has not been found within a specified maximum number of re-hashes.

The use the of hashing technique has so far been described as a way of finding an entry in a hash table that has already been filled with entries. A very similar technique can be used to make that table in the first place; essentially, each state (in some defined sequence) is hashed, and when there is found an empty entry in the table the identity of the relevant next procedure is inserted into that entry. Naturally, if on hashing the entry is already full, then the rehashing technique is carried out until the first empty entry is found.

The invention is a method of operating a computer, It may be summarised as: having defined a set of procedures to cover all possible operations, select and identify the next procedure solely on the basis of a (checked) hash of the preceding procedure's results. This is fundamentally different from the way in which present-day computers operate, dominated as they are by the use of a Sequence Control Unit and a Program Counter that points to the location of the next operation in the sequence of operations that consitutes a Program. Thus, despite branches to different segments, and the use of apparently separate subroutines, modern computers are controlled by a Program in the form of a single sequence of instructions.Though not accurate, the sequence may be likened to a railway network; the network contains points to sidings, but overall is a unified whole any part of which physically leads eventually to any other part. The system of the present invention, however, is like a series of physically quite unconnected lengths of railway track; the only way from the end of one to the start of any other is through hyperspace (or, in the light of present knowledge of space time, by magic!).

Various aspects of the invention are now described, though by way of illustration only, with reference to the accompanying Drawings, in which: Figures IA, B and C show in block form the general principle of the method of invention; Figures 2A, B and C also show the general principle of the invention, but in Program flow form; Figures 3A, B and C show in block form various aspects of the hardware required for the method of invention; Figures 4 to 8 are Diagrams and Tables relating to Example 1 hereinafter;; Fig. 1A shows in block diagram form the basic concept of the invention, in which the State (11) of the system at the end of a procedure determines the next procedure (12) to be performed, and the manner in which the former gives rise to the latter involves hashing (13) the State 11, and then performing the procedure identified by the hash result.

This concept is elaborated in Fig. 1B, where in addition there is firstly effected a check (14) that the determined next procedure is the one correctly following the present procedure (the check involves comparing a "tag" associated with the hash result, which "tag" identifies the procedure that should have given rise to that particular hash result), and if it does not then the present procedure State is rehashed-and so on until the correct next procedure is identified.

The concept is elaborated further in this Figure, for it shows that an ERROR State (15) can be entered if either the present State hashes/rehashes to an "empty" value (one with no check tag) or if the number of rehashes exceeds a predetermined maximum.

In Fig. 1C there is shown the Fig. 1B elaboration in a "learning" mode, in which it is being fed with information defining the Program. As each procedure ends so its State is hashed/rehashed to find the next procedure, and where an empty State results the system checks (16) to see whether this particular State has already been designated an ERROR State, and if not then it requests an input (17) defining the pointers to the procedure that should come next.

Figs. 2A and B show pictorially Program flow diagrams for respectively a computer operating according to the Prior Art and one operating in accordance with the invention. Neither flow diagram represents any particular Program; they merely doemonstrate how a Prior Art system is a connected whole while an inventive system is an unconnected collection of routines.

The Prior Art system of Fig. 2A comprises a main sequence of instructions (none of which are shown individually), extending directly from START to STOP, at various points (50, 51) along which there are either jumps to a subroutine (SR) or branches (52, 53, 54, 55) to alternative sections of the Program. On the other hand, the inventive system of Fig. 2B comprises a number (only three, in this case, in order to simplify things a little) of unconnected Program segments (procedures P1, P2, P3).

In the Fig. 2A system execution proceeds remorselessly along a line until a branch is encountered, at which either the one or other route is chosen (and most likely on the basis of the "results" so far). At the machine level each line can only branch into two lines, never more, for at that novel the only available instructions are of the type "IF such-and-such is true THEN do one thing ELSE do something different".For example, while going round a loop during which a counter is continuously incremented the Program might check whether the counter had reached a particular value (COMPARE WITH ., which commonly entails subtracting the counter value from the chosen value) and jump out of the loop if it had (JUMP if ZERO TO...), otherwise jumping back to the beginning of the loop (an unconditional JUMP TO . . . ) to continue going round it (such a Program segment was illustrated hereinbefore, though in a slightly different format).

In two places (50, 51) in Fig. 2A the Program transfers control to a subroutine quite separate from the main Program, butas is the essence of subroutines--control is transferred back again as soon as the subroutine is finished.

The structure of the inventive Fig. 2B system, however, is totally different. There are three quite separate procedures-segments of Program and at the end of each the procedure to be used next is chosen purely on the basis of the results "so far" (the State at that point), these results being hashed not merely to identify the next procedure but to cause control to be transferred directly to that procedure. In this Example it is imagined that procedure P1 can only have results A and B (which cause transfer to procedure P2 and P1 respectively), that procedure P2 can only have results C, D and E (which cause transfer to procedures P1, P3 and STOP respectively), and that procedure P3 can only have results F and G (which cause transfer to procedures P1 and P2 respectively).

The system of Fig. 2B can be rearranged to look more like a conventional flow diagram, and this has been done in Fig. 2C. It should be borne in mind, however, that Fig. 2C (and, indeed, Fig. 2B) is bearable mainly because there are only three Program procedures and each of these has only a few possible results! As Figs. 1A, B and C and 2A, B and C illustrate the principle of the invention, so Figs. 3A, B and C show it in the more usual hardware terms.

Fig. 3A shows a block diagram of a computing system which incorporates the essential features of this invention. The heat of the system is the Data Processing Unit (DPU 22) which is connected by a first data bus (27) to a Control Store (21) and by a second data bus (20 to a Data Store (23). The Control Store 21 holds the code defining the operations making up the procedures the system is to perform, and each procedure is identified by a tag denoting the system State giving rise to that procedure. The rest of the Figure is best described with reference to the system operations as follows: At the end of procedure in the DPU 22 signalled by the FINISH signal (33), the outputs (25) of the State Registers (26) are aplied to the hash function generator (24) which produces an address (38) for the control store 21. The tag part (36) of the control store word so selected is applied to the comparator (27), as is the State (25). The comparator has three outputs: (i) empty (35), which indicates that the tag is empty, which in turn implies that the procedure is undefined and therefore the State is illegal: (ii) equal (31), which means the comparison has succeeded and the procedure part of the control store word (37) may be applied to the DPU as the new procedure specification, and (iii) not equal (32), which indicates the comparison has failed and the hash function generator 24 must "rehash" the state.

If a rehash operation is requested, the hash function generator 24 must check to see whether an excessive number of rehashes has been requested by the current state. If so, the output (34) triggers the Illegal State control (28).

A simple implementation of a hash function generator is shown in Fig. 3B. The State input (25) is loaded into an n bit shift register (43) by the hash input (33) which also resets a counter (40). The shift register output (29) is applied to a hash array (41) which generates the address (38). The rehash signal (32) circularly shifts the shift register and increments the counter (40); this will generate a different address (unless the State is zero--this can be over-come by keeping State Zero as an error state). When the counter 40 reaches the value n (i.e. the shift register 43 has gone through all possible permutations) it asserts its = n output (44); a further rehash command will be gated (22) with this, and produce the hash overflow (34) illegal state.

Fig. 3C shows a possible implementation of the hash array 41. This particular embodiment reduces an n bit state to an n bit address.

2 The following Example is now given, though only by way of illustration, to show details of various embodiments of the invention.

Example This Example is of a Program that relates to the recognition of the three words RED, BLUE and BLACK as they might be typed in from a keyboard. The overall sequence of events is shown in Fig. 4, and the Program operates broadly as follows: 1)At start-up (START) a waiting state (WAIT 1) is automatically entered during which the Program is waiting for a character to be typed.

2) When a character is typed the Program checks to see whether it is a space (-), whereupon it enters a second waiting state (WAIT 2) during which it awaits another character.

3) a) If the next character is a space the Program continues in Wait 2.

b) If the character is one of the letters R or B it proceeds to the relevant one of two states RED 1 or BL 1 (it could be either Blue or Black).

4) In the RED 1 state the Program awaits the next character.

a) If the character is E the Program continues to state RED 2.

b) If the character is any other then the Program signals an error and returns to WAIT 1.

Following the RED input through to its end: 5) In the RED 2 state the Program awaits the next character.

a) If the character is D the Program continues to the state RED 3.

b) If the character is any other the Program signals an error and returns to WAIT 1.

6) In the Red 3 state the Program awaits the next character.

a) If the character is a space the Program continues to state RED (in which, though it is not shown, it takes some action not defined in this Example), and thereafter returns directly to WAIT 1 for a fresh input cycle.

b) If the character is any other then the Program signals an error and returns to WAIT 2.

In the same way BL1 progressed to BL2, which progresses either to BLUE 1 or BLACK 1 depending upon whether the input character was U or A, and thence to BLUE 2 and BLUE on the one hand and BLACK 2, BLACK 3 and BLACK on the other, in either case returning to WAIT 2 after the final (BLUE or BLACK) state. The sequence of events shown in Fig. 1 may be put in the form of a set of rules defining the only allowable occurrences within the Program. Such a Rule Set is shown in the Table of Fig. 5, using the format < NEW STATE > o < OLD STATE > < lNPUT CHARACTER > which means that the new state is derived from a combination of the old state and the character input during that old state.

The Program is completely defined by a number of procedures, the result of each procedure determining the next procedure. More specifically, the procedures are stored in memory, their start points being known so that the procedure may be carried out simply by jumping there and following the instructions, and the final operation of each procedure is to determine, upon the basis of the results just obtained, the next procedure to be carried out, and to jump directly to it.

It is convenient to imagine each procedure as being defined in a "word", these words being stored in memory at store locations 0, 1, 2, 3... 56, 57, 58... etc (in this Example the Locations are 0, 1, 2... 34, 35, 36); it is necessary merely to jump the relevant location in order to start executing the procedure defined in the word held at that location.

In accordance with the invention the Program determines the next procedure solely upon the basis of the results of the present procedure. More specifically, the results of the present procedure set (or reset) a number of Registers that define the State of the system at that point, and the value in some or all of these Registers is used to identify the store location for the next procedure. The method of so using the Register numbers is to hash them according to some predetermined hashing algorithm (formula) specifically chosen to allow the many possible Register values to hash to--to map onto--a much smaller number of store locations without an excessive need to rehash when a hash operation maps the Register values onto a store location already allotted to a different set of register values.The hashing algorithm chosen for this Example was derived (in a rather simple fashion) as follows.

i) First there was selected a prime number-37-somewhat greater than the maximum number20of valid states (WAIT 1 + WAIT 2 + RED 1 + ...).

ii) Then each allowable input character (space, A, B, C, D, E,. K. . ., null) was (arbitrarily) assigned a unique value (41, 42, 43... 52). In operation this value would be held in one of the State Registers involved in the procedure during which the character was input.

iii) And each allowable state (START, ERROR, WAIT 1, WAIT 2..., BLACK) was also (arbritrarily) assigned a unique value (1 6, 1 7, 1 8... 32). This value also would be held, in operation, in one of the State Registers involved in the procedure.

iv) Finally, the Word Address (Store Location) for any procedure was defined as Word ( State Character Address = (remainder of Value + Value + n) 37 where the State Value and Character Value are those giving rise to this particular word (as RED 1 and E give rise to RED 2), and n is the number of times the hashing algorithm had originally to be applied before a "free" address was found. This algorithm allows 37 possible word Addresses, from 0 to 36.

A full list of the State and Character Values used in the Program of the Example is shown in the Table of Fig. 6.

In the event that one particular State can be the result of several other State/Character combinations (as WAIT 2 can be the result of WAIT 1 < SPACE > , WAIT 2 < SPACE > , RED < NULL > , BLUE < NULL > , and BLACK < NULL > ) then, while it might be possible to arrange for the States to hash to the same value, it is simpler, and not usually too wasteful of memory, to allow the values to be different, giving different Word Addresses, and then to have the resulting State procedure stored several times over, once at each Word Address.

The definition of n in the hashing algorithm can best be understood from a description of how the Addresses are selected in the programming stage. This is, in fact, very simple.

With a blank memory and n initially set at 1, there is hashed the State resulting from start-up (START) combined with the allowable input (null).

State Value (of START) = 16 Input Value (of null) = 52 n= 1 Word Address = Rem. of (16 + 52 + 1) 37 = Rem. of 69 37 = 32 The State associated with START < null > is WAIT 1. Hence the word defining the WAIT 1 state, and what is involved in it, is stored at address 23.

In the same way there may be calculated the Address for the words defining all the allowable states, and these are shown in the Table (a hash Table) of Fig. 7.

On occasion the hashing algorithm as initially applied during programming might lead to a Word Address that is not free but instead already has a word stored there.

For example, to find the Address for RED 3 (solely derivable from RED 2 plus D) the algorithm as initially applied, using Address = Remainder of (Old (State (Value + Character Input + n) 37 gives Address = Rem. of 21 + 45 + 1 37 = Rem. of 67 37 = 30 However, 30 is already the Address of RED 2 (though not too relevant for this Example, it would normally be arranged that procedures liable to be employed most often are programmed first, to reduce access time wasted in rehashing thus, Rem. of 20 + 46 + 1 = 30 37 so the State is rehashed, but this time with n incremea . (to 2), so that Address = Rem. of 21 + 45 + 2 37 = 31 Address 31 is empty, and hence the Address of RED 3 is 31 and ntakes the value of how many times the hashing algorithm needs to be applied to find a free Address.

Returning, now, to the operation of the Program, the next procedure to be carried out is selected by hashing the State achieved by the present procedure and jumping to the indicated Address, handing over control to the procedure there stored. However, the handover clearly must not be inevitabic for as shown above two or more States may hash to the same Address, and an automatic handover could then cause the wrong procedure to be effected--but must be dependent upon the procedure at the Address being the correct next procedure for the particular state of the present procedure.Accordingly, each procedure starts with an identification of the procedure that should have preceded it (on occasion more than one procedure may validly precede a particular procedureWand conveniently this is a "tag" part of the word defining the procedurc and before releasing control the hashing routine of the present procedure always checks this identification against the present procedure. If in the event, it turns out that the next procedure is not the correct one then the present procedure's state is rehashed, and the jump is made to the new next procedure, again with the same identity check. Eventually one of four things happens: 1) The identity matches.

2) A maximum allowable number of hashes has been effected.

3) Every possible Address has been tried without success.

4) An empty Address is encountered.

Cases 2 and 3 may in practice be the same the maximum allowable number of hashes may be equal to the number of Addresses.

lh case 1 the new procedure will take over. In cases 2, 3 and 4 an appropriate error routine will be entered.

In case 1, where control is released to the new procedure, is easily understood and needs no more comment. However, the remaining cases, giving rise to an error routine, are worthy of further description.

In case 2 it is assumed that for one reason or another a limit has been set on the number of hashes that can be effected in an effort to find the Word Address holding the "matching" procedure. It is, of course, possible that the sought-after procedure does not exist-the present state is in fact an error-but that the particular hashing algorithm chosen is repeating without having accessed all possible Addresses. Alternatively, it may be again that there is no matching procedure (the present state is erroneous), that there are very many possible Addresses, but that it is known (from the programming stage) that no State ever needs to be hashed more than a relatively few number of times before finding the matching procedure.In either event it is clearly necessary to stop the system wasting time searching, and to break out of the hashing routine (with an error message, say), and then return to a more useful state (WAIT 1 in the Example), The hashing algorithm of the Example is such that it will never, regardless of the present state and input, find itself in a rehash cycle in which certain addresses are unreachable. However, the algorithm is cyclic-starting at 0, say, the algorithm is cyclic-starting at 0, say, the algorithm produces all the remainder numbers up to 36 and then starts again at 0 and thus another useful check on an error state is to break the cycle (going to the error routine followed by WAIT 1) whenever the number of hashes equals the number of possible Addresses.

Finally, unless the situation is very simple, or one is very lucky, there will always be more possible Addresses than there are valid states. Accordingly, some Addresses will remain empty---and this (the mere absence of the "tag" used to match procedures) may itself be used as an indication that the present state is erroneous; the very fact that there is nothing at the Address means that during programming, when all valid states were assigned an Address for their procedures, there was no such state giving rise to this Address so this state is an invalid one! The Program of this Example may now be run on paper using as the input the character string j -BLUE--RDE BZU..

The sequence of events is shown in the Table of Fig. 8, and may be explained (in part) as follows: 1) At start-up the system state is START < NULL > , giving rise to a hash value of 31, meaning the new state WAIT 1. The hashing routine jumps to Address 31, reads the tag, and finds that the procedure there is indeed the next procedure after START < NULL > . Accordingly control is released to this new procedure.

2) In WAIT 1 the system receives a space (-). Hashing the state (WAIT 1 = 18, space = 41, n= 1, (18 + 41 + 1) hash value = Rem of = 23 37 produces the Address (23) of the "next" procedure, and jumping to that Address the routine finds from the tag that it does indeed hold the correct procedure to follow WAIT 1, namely WAIT 2.

3) In the same way the system progresses to BL1, and thence to BL2, BLUE 1, BLUE 2 and BLUE (at which point a real system might output something suitable), whereupon it jumps back WAIT 2. During the course of this, however, it passes from BLUE 2 to BLUE via three consecutive hashesthrne attempts to find the correct next procedure.

Thus, the first attempt starts from BLUE 2 and SPACE, with n = 1. The hash value is: Rem. of (BLUE 2 + SPACE + n) 37 =Rem. of (27+41+1) 37 =Rem. of (69) 37 = 32 However, 32 is the ADDRESS for WAIT 1 (following START), not BLUE (which latter is the only valid procedure following BLUE 2), so a rehash is performed-n 2 and2nd the rehash value is: Rem. of (27 + 41 + 2) 37 = 33 But 33 is the Address for the RED 1 procedure, so a second rehash-n = 3is performed, and the rehash value is: Rem. of (27 + 41 + 3) 37 = 34 This Address does indeed hold the correct next prncedurn-BLUEand control is released to that procedure.

4) After BLUE and WAIT 2, the input character is a space, followed by R. This changes the state to RED 1waiting for an E-but the next character is, instead a D. Hashing the state provides a hash value of: Rem. of (RED 1 + D + 1) 37 = Rem. of (20 + 45 + 1) 37 = Rem. of (66) 37 = 29 But Address 29 is empty, and therefore an error routine is entered immediately, and the system then returns to WAIT 1. And so on.

Claims (8)

1. A method of controlling the internal operation of a computer, in which: a) all possible valid internal operations to be carried out by the computer are defined as a set of procedures (as hereinbefore defined); b) the result of each procedure determines the state of the computer following that procedure, and the next procedure is selected on the basis solely of the current state; c) the selection of the next procedure is effected by hashing the current state, and using the result to identify the next procedure; and d) initialisation of the next procedure so identified is dependent upon a check that it correctly follows the current procedure, and failure of this check causes a re-hash and re-selection, this being repeated until either the correct next procedure or an empty (error) procedure is found.

2. A method as claimed in Claim 1, in which, when the computer is started (initialized) and the procedure to be selected is the first procedure, an artificial "result" of the (non-existent) preceding procedure is constructed in some predetermined fashion, the computer's initial state being set to some predetermined value.

3. A method as claimed in either of the preceding Claims, which is for use with a computer containing a Sequence Control Unit that contains one or more counter (register) one of which may be a Program Counter, and the values in some or all of these counters are adjusted, as part of the preceding procedure, to define the new state and thus which is the next procedure to be effected.

4. A method as claimed in any of the preceding Claims, in which there are counted the number of rehashes needed to find the entry for any particular state, and that state is declared an error state if a relevant entry has not been found within a specified maximum number of hashes.

5. A method of controlling the internal operation of a computer as claimed in any of the preceding Claims and substantially as described herinbefore.

6. A computer whenever controlled by a method as claimed in any of the preceding Claims.

7. A computer, for operation in accordance with a method as claimed in any of Claims 1 to 5, wherein: there is a Central Processing Unit (CPU), which includes a Data Processing Unit (DPU), an Instruction Decoder (ID) and a Sequence Control Unit (SCU also referred to as an Address Processing Unit, APU); the SCU/APU itself contains an Instruction Register (IR), a Hash Function Generator (HFG) and a number of State Registers (SR); and the computer has a Memory that is divided into a conventional Data area and a Hash Table area; and wherein these components are interconnected such that the SR sends data to the HFG, the HFG can address, and so send data to and receive it from the Hash Table area of Memory, and the HFG can address the Data area of memory.

8. A computer as claimed in Claim 7 and substantially as described hereinbefore