GB2145583A - Inverter firing control with compensation for variable switching delay - Google Patents

Abstract

A pole switch firing control for a pulse width modulated inverter controls pole switch operation under steady state operating conditions such that the inverter output duplicates a reference signal waveform P, Fig 1A, after a fixed time delay T. Pole switch operating time D1, D2, D3, Fig 1D, for a given pulse in an inverter output cycle is measured and subtracted from a fixed time interval T to get a delay time TS1,TS2, TS3, Fig 1E. In the succeeding output cycle Fig. 2, the corresponding pulse is produced by initiating the pole switch operating sequence after the delay time TS1, TS2, TS3, thereby causing the pole switch to operate a fixed time T following the reference signal P. <IMAGE>

Description

SPECIFICATION Inverterfiring control with compensation for variable switching delay This invention relates generally to electrical inver ters and more particularly to circuits for controlling power pole switching in pulse width modulated inverters.

Pulsewidth modulated D.C. to A.C. inverters approximate sine-wave outputs by switching power pole switches at a rate higher than the fundamental sine-wave frequency. In the design of pulse width modulated D.C. to A.C. inverters, it is desirable to switch the power stage in a manner which reduces certain harmonics to low values so as to ease the burden offiltering the output power to obtain a sinusoidal voltage wave. Fairly small errors in switching times can produce harmonic voltages manytimes greaterthan desired. This usually results in the circuit filter being made considerably largerthantheoretically necessaryto suppress these harmonics.

In a transistor inverter, forexample, it is necessary to provide an underlay condition to preventshootthrough during switching. operation. This means that to switch an output pointfrom one polarity to another, there must be a delay after the conducting transistor isturned off, to be sure it is no longer conducting, before the other transistor is turned on.

Many times load'conditions are such that the second transistor doesnot conduct at all since load current is shunted through a commutating diode, thereby shortening theswitching timeto that ofthetransistor turn-offtime. Thus the switching time is quite variable depending on-tlie instantaneous load current as well as the transEstorturn-off characteristic. Therefore,the prescribed switching schedule is not met, resulting in unpredicted harmonics.

It is the principal object of the present invention to reduce switching errors.

The invention resides broadly in a pole switch firing control circuitforcontrnlling a pulse width modulated inverter in accordance with a reference pulse signal, said control circuit comprising: measuring circuitryformeasuring the switching time of a pole switch for a given pulse in a first output cycle; subtracting circuitry for subtracting said switching time from a given time interval to obtain a delaytime; and control signal generating circuitryforgenerating a control signal for initiating a pole switch switching sequence after a period equal to said delaytime for a second pulse corresponding to said given pulse in a second output cycle.

The preferred embodiment of the present invention reduces output distortion due to switching errors by predicting the switching time required for each switching point and using this prediction to adjustthe starting time for each switching period so that switching is accomplished on schedule. In general a reference waveform which is to be reproduced at the power pole outputwill be available to the switching control circuitry. Pulses within the reference wave are to be reproduced at the power pole output after a preselected time interval.

This delayed switching schedule is accomplished by measuring the power cycle and subtracting the measured switching time from the preselected time interval to obtain a delay time. The switching period for the corresponding pulse in the succeeding output cycle is then initiated at a point equal to the delay time, as obtained from the previous cycle, following the appropriate reference waveform pulse. This process is repeated for each power pole output pulse. During steady state operation, it is reasonable to expectthat switching periods will be the same length at corresponding switching points in each subsequent cycle.

Therefore, the power pole will switch after a preselected time interval following the reference wave pulses.

Acontrol circuitconstructed in accordance with this invention includes means for measuring switching time, means for determining the difference between a preselected time interval and the measured switching time to obtain a delay time, and means for initiating the power pole switching sequenceforthe corresponding pulse in the succeeding output cycle after the delay time following an appropriate pulse in the reference waveform. By appropriately timing the switching function, multiple phase inverters can be controlled by a single control circuit.

D.C. content of the inverter output is controlled by sensing D.C. content, generating a compensation signal, and varying pulse width of the output pulses in response to the compensation signal. A circuit which accomplishes this compensation includes an integratorwhich senses D.C. contentofthe output and produces a compensation signal and a comparator which compares the compensation signal to the power pole outputvoltage which has been reduced by a voltage divider and modified to have controlled rise and fall times. The comparatorthen produces a signal representing the phase voltage modified in pulse width depending on D.C. content. When the modified phase voltage signal is fed backto the firing control circuit, the firing circuit alters the power pulse width to eliminatethe D.C. component ofthe output.

Figure lisa series ofwaveforms illustrative ofthe function of an inverterfiring control in accordance with the present invention; Figure 2 is a series of waveforms illustrative ofthe function of an inverterfiring control in accordance with the present invention, for an inverter output cycle succeeding the output cycle represented by Figure 1; Figure 3 is a schematic diagram of an inverterfiring control circuit constructed in accordance with one embodiment of the present invention; Figure 4 is a schematic diagram of a test circuit for use with the inverterfiring control represented by Figure 3; Figure 5 is a schematic diagram of a D.C. compensation circuit in accordance with oneembodimentofthe present invention; and This print takes account of ceplacement documents later filed to enable the application to comply with the formal requirements of the Patents Rules 1978.

Figure 6 is a series ofwaveforms illustrative ofthe function ofthe D.C. compensation circuit of Figure 5.

Referring to the drawings, the waveforms of Figure 1 illustrate the operation of the inverter firing control method and apparatus of this invention for a portion of a single output cycle of a pulse width modulated inverter. Figure 1 A shows a pulse wave P which is part of a reference signal that is to be reproduced at the inverter power pole output. The reference signal may be generated within the inverterfiring control circuitry or may be received from an external source. A fixed time interval T is shown with respect to each transition point of pulse wave P. This invention acts to make the inverter power pole switch at the end of each period T, thereby causing the inverter output to reproduce the reference signal. To maintain properfiring control function, time interval T must be at least as long asthe maximum switching time of the power pole.

Pulse wave TS of Figure 1 B contains a history ofthe switching times for each switching point in the previous inverter output cycle. The length of each pulse in pulse wave TS corresponds to the difference between a power pole switching time and fixed time interval T.

Control signal CN of Figure 1 C responds to the completion of each pulse in pulse wave TS, and is used to initiate the power pole switching sequence.

During steady state operation, it is reasonable to expect that switching times will be the same length at corresponding switching points in each subsequent cycle. Therefore if a switching sequence is initiated after a delayTS which is equivalent to the difference between a fixed time interval T and the previous cycle switching time, actual switching should occur after a full time interval T.

The means used to achieve this result are illustrated by otherwaveforms of Figure 1. Asignal OP representing the inverter output pole voltage is shown in Figure 1D. Switching delays D1, D2 and D3 are indicated following each transition of control signal CN.

Curve TC of Figure 1 E represents a time keeper which measures switching time ofthe power pole.

Thisfunction can be accomplished buy a down counter which starts at a count representative of fixed time intervalTand begins to count down upon the occurrence of a transition of control signal CN.

Counting stops when the power pole switches, leaving a count equivalent to delay time TS, to be used to control a pulse during the next output cycle. This count is then stored in a memory element such as a random access memory or shift register. Alternative ly, an up counter can be used as in Figure 3. In either case, the maximum count ofthe counterwill corres pondtothelength of fixed time interval T.

Pulse wave W of Figure 1 F causes data from the counter needed in the next output cycle to be entered into a memory element such as a shift registerwhich advances and displays data appropriate to the next switching operation. The number of stages in the shift register is equal to the number of power pole switching operations in an inverter output cycle. Pulse wave R of Figure e 1G resets the counter after its data have been entered into the shift register.

The waveforms of Figure 2 illustrate the function of the invention for an inverter output cycle succeeding the output cycle represented by Figure 1. The first transition of control signal CN is delayed by a delay timeTS1 which was stored in the memory' element based on the power pole switch performance forthe corresponding pulse ofthe previous cycle as illustrated in Figure 1. For steady state operation,the switch operating time for a given pulse in a cycle should equal the switch operating time for the corresponding pulse in the previous cycle. Therefore, the inverter output OP switches after a delay D1 following the first transition of control signal CN.This results in a switching delay equal to fixed time interval Tfollowing a transition of reference signal pulse wave P.

Under steady state conditions, the process con tinuesforeach pulse in the output cycle with the sum ofthe control signal delayTS and the switching delay D always equaling the fixed time interval T. This is readily apparent in Figure 2 where (TS1 +D1) = (TS2+D2) = (TS3+D3) = T. An examination ofthe waveforms of Figure 1 reveals that the output OP does notswitch after a fixed time interval Tfollowing a transition in reference pulse wave P. This illustrates the circuit response when a transient condition occurs just prior to the observed sample. When steady state conditions return, the switching schedule will be satisfied.

Figure 3 is a schematic diagram of a firing control circuit constructed in accordance with one embodiment of the invention. Reference signal P and control signal CN areconnected tothe inputterminals of exclusive OR gate Z3A. The output signal of gate Z3A is delay signal TS. Assuming thatthe inverter has been operating and the load has been changed just before the current cycle begins, a logic word representing the length of each pulse in delay signal TS for the previous inverter output cycle will be stored in memory element 10 ofthe circuit. In this embodiment the memory element loins a shift register comprising gates Z5, Z6, Z7, Z8, Z9 and Z10. For explanatory purposes, assume that initially reference signal P and control signal CN are both high.When P goes low,the delaysignalTS goes high. SinceTS is connected through logic inverterZ21 to the reset terminal R of counterZ2, and also to an input of AND gate Z1A, counterZ2will begin the countclock pulses being received from terminal C via AND gate Z1 A, as long as the output of NAND gate Z1 9 is high. The function of NAND gate Z19 is discussed below.

The output of counter Z2 is a logic data word which is connected to the input of comparator 20 as is the output of memory element 10 which is a logic data word representing the length ofthe corresponding inverteroutputpulsedelaytime in the preceding cycle. Comparator 20 comprises a plurality of exclusive OR gates Z3C, Z3D and Z4 and a plurality of AND gates Z1 5 connected such that an output signal develops when the output data words from counter Z2 and memory 10 become binary complementary. If a down counter were used for counterZ13, a comparatorwould be used which develops an output signal when the data words from counterZ2 and memory 10 are equivalent. The comparator output is connected to atype Dflip-flop Z16which gives an output control signal CN agreeing with reference P. The control signal CN and reference P are then in agreementatthe input of exclusive OR gate Z3A. This drives delay signal TS low, which instructs AND gate Z1 A to stop transmitting clock pulses to counter Z2.

Control signal CN is connected to the inverter pole where it acts to trigger switching and is also connected to an input of exclusive OR gate Z3B. A plurality of NAND gates Z19 is connected to receive inverter output signals PHA, PHB and PHC. The outputs of Z19 are connected through AND gate ZiCto exclusive OR gate Z3B. As a result exclusive OR gate Z3B produces a high output when control signal CN and the inverter output signals disagree.This high output passes through a plurality of NOR gates Z1 8 and AND gate Z1 Bto enable counter 213. Clock pulses which enter counterZ13from terminal Cthrough AND gate Z1 B are counted by counter Z1 3 until control signal CN and the inverteroutputs agree. Atthattime, one ofthe inputstoAND gate Z1 B goes low, stopping the transmission of clock pulses to counter Zl 3. This results in counterZl3counting upto a data word which represents the switching delay time of the power pole switch in the inverter.

NAND gate Z12 receives inputs from all but one output data line of counter 213 and produces a logic low output should all butthe least significant of the data lines become logic highs. This stops the trans mission of clack pulses through AND gate Zl B, thereby stopping the count in counterZ13 one short of its maximum value which corresponds to the length of fixed time interval T. This assures that counter Z13 will notcountthrough its maximum count and recycle.

When the inverter output and control signal CN agree, the output of gate Z18 goes to a logic low. This signal. passes to one-shot multivibratorZ14Athrough logic inverterZ20. The Q output of one-shot Z14A is connected to memory element 10 and causes memory 1 Oto shiftthe data to the next cell and store new data from counter Z13. The Q output of one-shot Z1 4A is connected to the input of one-shot multivibratorZ14B which produces an outputQto resetcounterZ13 after one-shotZ14Ahastimed out, providing atime delay which allows the shifting memory 10 before resetting of counter Zl3.

NOR gate Z11 has inputs connected to each output of counterZ13 and provides a logic high to coupling circuit 30 when the output of counter Z1 3 is all zeros.

When counterZ13 begins two count NOR gate Z1 1 goes to logic low causing one-shotZ17Ato produce a logic high pulse at itsQ output and logic inverter Z22 to also produce a logic high. NAND gate Z19 responds to its two high inputs by producing a logic low outputwhich is fed to AND gate ZlAthus inhibiting transmission of clock pulses to counter Z2forthe duration of the counting sequence of counter Z1 3. This lock-out of counter Z2 assures the proper operating sequence of the two counters.Once counterZ13 has counted and has been reset producing logic zeros at all its output terminals. NOR gate Z11 produces a logic high which is transmitted through coupling circuit 30 to AND gate Z1Atherebyallowing clockpulsesto reach counterZ2 at the appropriate time. Coupling circuit 30 is included only to ensure proper start-up of the control circuit.

One-shotZ17A provides a relatively long output pulse so as to not interfere with signals initiated by counter Z13. Coupling circuit 30 assuresthatthe clock signal to counter Z2 cannot be permanently inhibited in case counterZl 3 does not contain all zeros when the circuit is first turned on.

Terminals Vcc are connected to a D.C. voltage supply which is 1 Svolts in this embodiment. The number of data bits used in the counters and shift register determines the resolution ofthe circuit. It should be apparentthatcounters and shift registers can be selected to providethe resolution required in a specific circuit application. Capacitors C1 through C4 in conjunction with resistors R1 through R4setthe output pluse times of the circuit one-shot multivibrators.

It is usual in the operation of switching inverters to establish a running condition of the control circuits before turning on the power stage. This not only sets the stage for stable operation, but also provides a means for monitoring the operation of the control circuits. The control circuit can be made to operate in the absence of a switched output by providing a substitute signal. In Figure3,aterminal labeled D provides a means of choosing between two signals to allowthe operation of counter Z13. When terminal D is connected to a logic low signal, circuit operation proceeds as described above. When terminal D is connected to a logic high signal, the normal signal inputto gate Z18 is blocked, and a substitute signal is allowed to operate AND gate Z1 B.The substitute signal is derived by one shot multivibrator Z1 7B starting with each change of control signal CN. Then the control circuit operates in the normal manner with the delay between reference signal P and control signal CN determined by the length of the output pulse of one shotZ17B.

Although the waveforms of Figures 1 and 2 are concerned with a single pole inverterwherethe output signal OP represents the pole switching characteristic, the circuit of Figure 3 shows an example of multiple pole operation. In the circuit shown in Figure 3, terminals PHA, PHB and PHC are connected to signals which represent a pole switching characteristic of each pole in a three phase system. Multiplexing these signals permits a single control circuit to control all three pole switches.

One modulation pattern for a three phase inverter would switch a given pole only during a period of less than 60 degrees. Then that pole would be held in a constant state for more than 120 degrees before being switched again. During the 120 degrees non-switched period, each ofthe other phases may be switched in sequence. Thus all three phases are switched in identical patterns, but only one at a time in sequence.

The output signal OP therefore represents the output of one pole, then another, etc. By steering the control signal CN to each phase atthe proper time in 60 degree segments all three phases may be controlled.

As shown in Figure 3, the output signal OP may be derived using simple majority logic such as gate array Z1 9, since at the time that any phase is being switched, the othertwo phases are opposite in polarity and steady.

Figure 4 is a schematic diagram of a test circuitto be used with the circuit of Figure 3. Control signal CN is received via terminal Sand used to produce a simulated phase output signal PHA'. When the simu lated output signal is connected to a phase input of Figure 3, such as terminal PHAwith PHB and PHC logically opposite, the circuit will function as if it were controlling an inverter having delayed switching of its poles.

lnverterswhich utilize control circuits in accordance with this invention should exhibit only a small amount of D.C. voltage in the output due to switching fidelity.

Nevertheless, a small amount of D.C. content is likely to be present because ofslightswitching errors and differences in switch voltage drops.

Figure 5 is a schematic diagram of a circuitfor detecting direct voltage in the inverter output relative to the center ofthe D.C. source and for providing a compensation signal which modifies the apparent switching points ofthe inverter output and is fed as the pole signal inputto the circuit of Figure 3. The inverter D.C. source is connected between terminals +DC and -DC. Transistors Q1 and Q2 are the switching elements for POLE A of the inverter. Capacitor C6 is connected to POLE Athrough resistor R7.The bulk of the A.C. component of the pole voltage is dropped in resistorR7,whilethe D.C. componentappears on capacitor C6. An integrator comprising capacitorC8, resistor R8, amplifierOP1, and diodes CR3 and CR4, accumulates D.C. volt-seconds from capacitor C6 and produces a compensation signal which is clamped by diodes CR3 and CR4 to less than the pole voltage signal. The combination of resistors R9 and R10 and amplifier OP2 provides a D.C. neutral voltage signal to the non-inverting input of amplifier OP1.

The compensation signal produced bythe integrator is fed to the inverting input of comparator OP3 as a reference signal. The non-inverting input of compara torOP3isconnectedto POLEA by means of a voltage dividercomprising resistors R11 and R1 2. Capacitor C7 provides a controlled slope on the pole voltage signal appliedtothe comparator. In multiple pole inverters, the circuit of Figure 5 would be duplicated for each pole.

The operation ofthe compensation signal is illustrated by the waveforms of Figure 6. Figure 6Ashows a controlled slope waveform representative ofthe output for pole A which contains a positive D.C. error voltage. In response to this error,the circuit of Figure 5 will produce a D.C. compensation signal CS1 with a magnitude E due to the D.C. error voltage but of opposite polarity. The output signal ofthe circuit of Figure 5, PHA, changes atthe crossover points ofthe pole voltage and the D.C. compensation signal. This is illustrated bythe pulse compensation signal of Figure 6B. Without compensation, pole signal PHAwould switch when the pole voltage crossed the zero axis. It should be apparent that the addition ofthe D.C.

compensation signal has increased the positive pulse width of PHA and decreased the negative pulse width.

The actual pulse width ofthe inverter power pole depends on the level of D.C. compensation signal.

When the modified PHA signal is fed to the circuit of Figure 3, the positive pulse width ofthe inverter output pulses will be reduced, thereby reducing the positive D.C. error in the inverter output. Once the D.C. content of the inverter output becomes zero, the D.C. com pensation signal from the integrator remains constant until a D.C. component appears again in the output voltage.

Figure 6C shows an example of a pulse compensation signal CS2 forthe case wherethe output of pole A contains a negative D.C. component. Compansation signalCS2hasa magnitude Fduetothe D.C. error voltage but of opposite polarity. Since switching occurs at the crossover points of the pole voltage and the compensation signal, the positive pulse width of PHAwould be decreased. When the modified PHA signal is fed back to the circuit of Figure 3, the positive pulse width ofthe inverter output will increase to compensate forthe negative D.C. error component.

While the preferred embodiment of the invention has been described, it will be apparent to those skilled in the artthatvarious modifications may be made therein without departing from the scope of the invention.

Claims (2)

1. A pole switch firing control circuitfor controlling a pulse width modulated inverter in accordance with a reference pulse signal, said control circuit comprising: measuring ci rcuitry for measuring the switching time of a pole switch for a given pulse in a first output cycle; subtracting circuitry for subtracting said switching time from a given time interval to obtain a delay time; and control signal generating circuitryforgenerating a control signal for initiating a pole switch switching sequence after a period equal to said delay time for a second pulse corresponding to said given pulse in a second output cycle.

2. A pole switch firing control circuit as recited in claim 1, wherein said means for measuring switch switching time: a first counterfor counting clock voltage pulses, said counter being enabled between a transition point in said control signal and a firing point of said pole switch in response to said transition point in said control signal.