GB2144283A - Demodulator - Google Patents

Abstract

A demodulator which is capable of demodulating a variety of frequency shifted signals including MSK and FFSK. The demodulator converts an analogue received signal to a digital signal and splits the signal into two quadrature baseband signal streams. The camer frequency of the received signal is derived from the signal streams and clock signals are produced from the derived frequency. The phase of the signal streams is corrected, the phase corrected signals are multiplied by waveforms derived from the clock signals, and the phase corrected and multiplied signals are integrated to provide a data output signal. The phase correction is effected by adding and subtracting the phase corrected and multiplied signal streams and integrating the resultant signals to provide two output signals each indicating the presence or absence of one of the positive and negative frequency shifts in the received signal, and correlating the frequency derived by the non-coherent frequency detector with the two outputs to derive a carrier phase error signal, the error signal controlling correction of the phase. <IMAGE>

Description

SPECIFICATION Demodulator The present invention related to a demodulator, and ín particularto a digital signal processing demodula torfor processing a variety offrequency shift signals.

The increasing density of R. F. signals within all frequency bands has led to the development of modulation techniques which require a reduced bandwidth. One of these techniques utilises minimum shift keyed (MSK) signals. Although MSK has been defined sufficientlyin terms of spectral response, there are numerous versions of how binary data should be encoded and modulated for MSKtransmission. One version is described in U.S. Patent No.

2977417, and another in IEEE Transactions, COM-22, pages 1525-1540,1974. Another reduced bandwidth modulation technique utilises fast frequency shift keyed (FFSK) signals, as described in IEEE Transac tions, COM-20, 429-435,1972. In fact MSK and FFSK techniques are similar and can be considered as special cases of continuous phase frequency shift keying (CPFSK).

It is an object of the present invention to provide a demodulator which is capable of processing a variety of FSKsignals.

According to the present invention, there is provided a demodulatorfordemodulating a received frequency shifted signal in which the signal is shifted in frequency positively or negatively in dependence upon the data to be transmitted, comprising means for converting the analogue signal to a digital signal and splitting the digital signal into two quadrature baseband signal streams, a non-coherent frequency detector means for deriving the frequency ofthe received signal from the signal streams, a clock signal generator means for generating clock signals from the output ofthe frequency detector, a carrier phase correction means which receives the signal streams and is responsive to a carrier phase error signal to providetwo phase corrected quadrature baseband signal streams, means for multiplying the phase corrected signal streams by waveforms derived from the clock signal generatorwith which it is intended thatthe phase corrected signal streams will be in phase, means for respectively adding and subtracting the phase corrected and multiplied signal streams and integrating the resultant signals to providetwooutput signals each indicating the presence or absence of one ofthe positive and negative frequency shifts in the received signals, means for correlating the frequency derived bythe non-coherent frequency detector means with the two outputs to derive the carrier phase error signal, and means for generating a data output signal by integration of the corrected and multiplied sigp:alis.tfearns.

The invention could be implemented by discrete circuits, but it is possible to provide a software based implementation developed around a single processor chip. Such a use of digital and software techniques on large scale integrated circuits provides both flexibility and economy of design in terms of size, cost and implementation.

An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawing.

In the drawing, a 100 baud MSK input signal centred on 1 .6kHz is applied to the demodulator input 1. The received signal thus has a + 25Hz frequency shift. This input signal is supplied from an appropriate IF stage (not shown) incorporating filters to suitthe particular application.The analogue carrier input is sampled by analogue to digital converter 2 atfour times the centre frequency and these samples are split into two quadrature baseband land Streams buy a quadrature splitting arrangement illustrated schematically at numeral 3. Asthe sampling is not lockedto the signal carrier the sampled quadrature channels are phase shifted with respect to the modulator land Q streams and so the quadrature signals are denoted by I' and Q'.

A high pass filter 4 is provided after the ADC 2 to reject any dc component of the inputsignal.

Each of the quadrature streams then passes through a respective low pass filterS which provides sharp cut off and linear phase response. Both the filtered streams are then fed to a non-coherent frequency detector and a carrier phase correction portion of a coherent detector.

Thefunction ofthe non-coherent frequency detector isto recover the data clock and to provide a frequency output to assist the phase synchronisation ofthe coherent detector. The frequency detector consists of a phase detector 6 followed buy a differentiator 7 to derive the frequency of the signal. A low pass filter 8 is used to reduce the quantisation noise. The voltage which represents the signal frequency is then limited positive for the upper frequency or negative for the lower frequency by a limiter 9 the output 10 of which provides a frequency signal fn.

A data tracking loop 11 also receivesthefrequency signal and locks its internal bitperiodcountertothe phase ofthe incoming data stream. The output from the loop 11 is divided down by four in divider 12 to produce two square waveswhich represent the land Q system clocks. The Q clock lags the I clock 90".

The baud rate ofthetransmitted signal is known very precisely and this is used to ensure that bit synchronisation is maintained during periods of interferenceorsignal loss.

The phase difference between the I' and 0' streams and the I and Q system clocks is detected in a carrier phase error detection circuit and the error output is used to apply suitable correction in a carrier phase correction circuit.

The land Q system clocks are applied to respective ramp generators 13the outputs of which drive sine wave generators 14. The resultant 25Hz sine waves are multiplied with the land 0 streams provided bythe carrier phase correction circuit in multipliers 15.

When the two multiplier outputs are either added or subtracted in circuits 16 ofthe carrier phase error detection circuitthis has the same effect as correlating with the positive shift frequency +25Hz, and the negative shift freq uency -25Hz respectively. An integration in circuits 17 over 1 bit period ofthese outputs can have one ofthree possible states, that is +K, -K & O. These correspond to the respective frequency being present with phase shifts of 0 and 1800 or in the case of a zero output the other frequency was being transmitted.Thuswhen the signal has a shift of +25Hzthe output ofthe +25Hz integrate and dump circuit 17 will be +K or -K and the output of the -25Hz integrate and dump circuit 17 should be 0. This is true if there is no phase error between the signal and the local system clocks. Phase errors produce a non-zero output from the detectorforthefrequency which was nottransmitted and this is used as an error signal to correct the carrier phase. To determine which ofthe outputs should be treated asthe phase error signal the frequency fn detected by the non-coherent demodulator is fed into a phase error detect circuit 18 for correlation. A slope detect circuit is used to multiplythe output of circuit 17 by +1 or -1 to normalise the signal.

The signal provided by the phase error detect circuit 18 is applied to a loop filter 19. Carrier phase correction is then accomplished by multiplying the complex baseband input signal, (I' + j Q') by a unit magnitude phase correction vector, (cos 8 + j sin IZi).

This is achieved by generating cosine and sine signals from the carrier phase error signal in circuits 20 and 21 respectively, multiplying the resultant signals in multipliers 22 with the I' and 0' signals, and then adding and subtracting the resultant signals in circuits 23. The corrected signal (I + jO) should now be in phase with the 25Hz signals ILO and QLO derived from the land 0 system clocks. The corrected signal is fed to the coherent detection stage. Phase ambiguities of 90" are eliminated by using thefrequencydetermined by the non-coherent frequency detector in the generation ofthe phase error signal as described above. The remaining ambiguity of 1800 gives rise to the possibility of inversion of the output data stream.This can be resolved by suitable differential encoding and decoding in the general case. in the present system a known pattern interleaved with the information bits is used to detect and correct any inversions ofthe data stream.

The phase correction mechanism will not be affected bythe marklspace ratio ofthetransmitted data as long as bit synchronisation is maintained. This is an improvement overtechniques involving frequency doubling and a pair of phase locked loops (PLL) to extractthe second harmonics ofthe upper and lower frequencies, which would suffer from drifting of the PLL's if one frequency were transmitted for an extended period. Whilethe major contribution to phase error is probably due to changes in the propagation path length, the present system should also be able to cope with small frequency errors due to errors in frequency conversion processes in the receiver.

The multiplied phase corrected baseband signals are outputfrom multipliers 15 and integrated in integrators 24 over double bit periods. These integrated values determine the polarityofthel a nd O signal streams and are limited in limiters 25 and interleaved in symbol detector 26 to give the data output. Differential decoding may be applied in decoder 27 at this pointforsome versions of FFSK or MSK. The detection process is fundamentallythe same as that described by 'de Buda' in IEEETransactions COM-20, pages 429-435,1972 and the same error rate performance for equal SNR's and filter bandwidths should be achieved.

A data output circuit 28 receives the output ofthe decoder 27, the frequency signal fn derived from the non-coherentfrequency detector, and a control input 29. The data outputcirnuit 28 is in effect an assembly of gates by means of which the frequency or decoder inputs may be selected singly or in combination to provide the data output 30. For example, for conventional FSK received signals, onlythe information fn at the frequency input is uttlized. In this case, the sequence of frequency high or low is utilized to reconstructthe 5 unit teleprinter (Murray) code representing individual letters of text.For the various MSK systems, the representation of a "0" or "1" depends, not only on the instantaneous frequency of the received transmission, but also on whetherthis is the same or different from that which obtained during the previous data bit. In some systems the timing of the frequency change relative to what has previously been signalled determinesthe data bit output. Depending upon the signalling system being handled, the data output circuit 28 can be controlled to select the appropriate input or inputs required.

The described system allows the userto switch between the various modes to either accommodate future operational requirements orto compensate for changing propagation conditions during transmission. This is achieved without the need of additional hardware. In addition, it can cater four any version of MSK or FFSKwhether so far documented or foreseen, and thus eliminates any ambiguitywhich has previously occurred. The use of standard signal processing devices ensures minimal space requirements without affecting the inherent flexibility. In software implementations, a constant predictable performance is ensured. The software can eliminate the necessity forthe periodic re-adjustment of circuitrywhich is usually required with discrete components.

Claims (8)

1. Ademodulatorfor demodulating a received frequency shifted signal in which the signal is shifted in frequency positively or negatively in dependence upon the data to be transmitted, comprising means four converting the analogue signal to a digital signal and splitting the digital signal into two quadrature baseband signal streams nonsoherent frequency detector means for deriving the frequency of the received signal from the signal streams, a clock signal gener ator means for generating clock signals from the output of the frequency detector, a carrier phase correction meanswhich receives the signal streams and is responsive to acarrier phase error signal to provide two phase corrected quadrature baseband signal streams, means for multiplying the phase corrected signal streams by waveforms derived from the clock signal generator with which it is intended thatthe phase corrected signal streams will be in phase, means for respectively adding and subtracting the phase corrected and multiplied signal streams and integrating the resultant signals to provide two output signals each indicating the presence or absence of one of the positive and negative frequency shifts in the received signals, means for correlating the frequency derived by the non-coherentfrequency detector means with the two outputs to derive the carrier phase errorsignal, and means for generating a data output signal by integration of the corrected and multiplied sig nat streams.

2. Ademodulator according to claim 1,wherein the non-coherent frequency detector means compris- es a phase detector.

3. Ademodulatoraccording to claim 1 or2, wherein the carrier phase correction means comprises means for multiplying the two signal streams by a unit magnitude phase correction vector derived by sine and cosine conversionsofthe carrier phase error signal.

4. Ademodulatoraccording to claim 1,2 or3, wherein the means for multiplying the phase corrected signal streams comprises means for deriving two signals having a frequency which is one quarter that of the data clock and 90 out of phase with each other, means for generating ramp voltages from the two clocksignals, and meansfor effecting sine conversions ofthe respective outputs ofthe ramp generators to provide said waveforms.

5. A demodulator according to any preceding claim, werein the means for integrating the phase corrected and multiplied signal streams are operative to separately effect integration of each of the signal streams over one bit period to provide an output signal which is either positive, negative or nominally zero in respectofeach of the positive and negative frequency shifts, the positive and negative signals indicating the presence of the frequency to be detected and the nominally zero signal indicating the absence of the frequency to be detected, and the correlating means effective to selectthe output signal which is nominally zero to serve as the carrier phase error signal as determined by the frequency derived bythe non-coherent frequency detector.

6. A demodulator according to any preceding claim, wherein the data output signal generating means comprises means for integrating the corrected and multiplied signal streams overdouble bitperiods and the resultant signals are interleaved to give the data output.

7. A method for demodulating a received frequency shifted signal in which the signal is shifted in frequency positively or negatively in dependence upon the data to be transmitted, wherein the analogue signal is converted to a digital signal and split into two quadrature baseband signal streams,thefrequencyof the received signal is derived from the signal streams, clock signals are generated from the output of the frequency detecor, two phase corrected quadrature basebandsignal streams are derived from the signal streamsin response to a carrier phase error signal, the phase corrected signal streams are multiplied by waveforms derived from the clock signal generator with which it is intended that the phase corrected signal streams will be in phase, the phase corrected and multiplied signal streams are respectively added and subtracted and the resultant signals are integrated to provide two output signals each indicating the presence or absence of one of the positive and negative frequency shifts in the received signals, the frequency derived from the signal streams is correlated with the two outputs to derive the carrier phase error signal, and a data output signal is generated by integration ofthe corrected and multiplied signal streams.

8. A demodulator substantially as hereinbefore described with reference to the accompanying drawing.