GB2142506A - Telecommunications exchange alarm system - Google Patents

Abstract

The telecommunications alarm system is for use in a telecommunications exchange. The system includes a microprocessor MPROC having a data store containing digital information in respect of all alarm conditions. A monitoring means interconnects the microprocessor with the exchange so that detected alarm conditions are passed to the microprocessor. Store accessing means gain access to the information in the store appertaining to the detected alarm condition. The stored information is converted into an analog signal for driving a speaker PAS. <IMAGE>

Description

SPECIFICATION Telecommunications exchange alarm system The present invention relates to a telecommunications exchange alarm system for use in a telecommunications exchange.

The alarm system monitors the functions of the exchange and upon the occurrence of a fault immediately announces that fault and its location in the exchange.

The system offers the advantage in that the engineering personnel are immediately made aware of the fault and need not be tied to a central fault monitoring area in order to be made aware of the fault. The engineering personnel therefore have greater freedom within the exchange environment without a resulting loss in exchange performance.

According to the present invention there is provided a telecommunications alarm system, for use in a telecommunications exchange, including a microprocessing device having a data store containing digital information in respect of all alarm conditions, monitoring means interconnecting the microprocessing device with the exchange so that detected alarm conditions are passed to the microprocessing device, store accessing means for gaining access to the information contained in the store appertaining to the detected alarm condition, and information processing means for converting the accessed stored data into signals for driving an audible announcement device.

The invention will be more readily understood from the following description which should be read in conjunction with the following drawings wherein; Figure 1 shows a block diagram of a speaking alarm system, Figure 2 is a block circuit diagram of a multiplexing board, Figure 3 is a block circuit diagram of a microprocessor board, and, Figure 4 is a block circuit diagram of a speech board.

Referring to Figure 1,the speaking alarm system includes up to sixty-four interface boards IB each having up to sixty-four inputs IPI-64. The inputs are connected to the exchange equipment and the interface boards gather information about the alarms. The interface boards IB convert the information to standard logic levels for CMOS or TTL integrated circuits. The resulting logic levels are scanned by multiplexers MEX on a number of multiplexing boards of which there may be up to sixty-four. A three wire bus WB connects the multiplexing boards MEX with a microprocessor board MPROC. The bus WB consists of a clock wire CLK outgoing from the microprocessor board, MPROC, a reset wire RSTW outgoing from the microprocessor board MPROC, and an alarm wire ALM, incoming to the microprocessor board MPROC.The alarm information is placed onto the alarm wire ALM in time division multiplexed format by multiplexer boards MEX.

A synchronisation signal is sent by way of the clock wire CLK to ensure that only one multiplexing board MEX at any one time transmits information to the microprocessor board MPROC. A reset signal is sent to all multiplexing boards MEX after each scan of all the boards. When the microprocessor board MPROC receives the time multiplexed information, it initiates announcements when alarms occur. It does this by controlling a speech board SB which produces analogue speech signals, which may be switched by way of a microprocessor controlled switching device SW to a public address system PAS orto a communications link via a communications link interface CLI.

The link interface CLI is used to sense user requirements. The user may want to interrogate the alarm system and electrically transfer signals between the link and the microprocessor board MPROC. The alarm system can be switched from the announcement mode to the interrogation mode. In order for the system to be interrogated by the user, a keypad KPD is provided either near to the monitored exchange equipment or remotely therefrom and connected via a communications link. The system can be interrogated by the use of MF4tones generated by activation of the keypad KPD and decoded within the alarm system by a decoder DCR and passed to the microprocessor board MPROC.

A watchdog timer WDT is regularly sent pulses P by the microprocessor board MPROC, and a warning is sent to the communications link interface CLI via a tone generator TG, if the pulses cease due to system failure or power failure. The timer WDT also attempts to reset the microprocessor by sending a reset pulse RT in the event of a random error causing the program to be wrongly executed.

Referring to Figure 2, the multiplexer board will now be described. The board includes receivers RV2, RV1 for receiving the clock CLK and reset RST signals from the microprocessor board MPROC Figure 1, and are used to clock and reset the counter CTR. The counter CTR generates twelve output data bits 0-11. The output data bits 0-2 are all passed to each of eight multiplexers M0-M7 in order to select one of the multiplexers M0-M7. Each multiplexer is capable of receiving eight input signals from respective monitored exchange equipments.

The output data bits 3-5 of the counter CTR are used to address a decoder DEC having eight output lines 0-7, one of which is connected to a respective multiplexer M0-M7. Only one output line 0-7 is activated at any one time and the resulting signal is used to enable the respective one of the multiplexers M0-M7. The respective output lines of the multiplexers M0-M3 are connected to NAND gate G1 and the respective output lines of the multiplexers M4-M7 are connected to the NAND gate G2. The output from the gates G1 and G2 are presented to a 3-state line driver LD by way of a NOR gate G3, so that only one multiplexer at a time is allowed to present an output to the line driver LD in order to generate an alarm condition, ALARM.

The output data bits 6-9 of the counter CTR are passed to the respective inputs of the comparator COMP1, and the output data bits 10 and 11 of the counter CTR are passed to the respective inputs Al -A2 of comparator COMP2. The two comparators COMP1 and COMP2 are cascaded and their respective B inputs B1-B4 and B1, B2 are connected to a positive potential via resistor bank RB and to earth by way of a microprocessor controlled switching device MSD. When the signals presented to the A inputs equate to those presented to the B inputs, an A=B output signal is generated and is presented to the line driver LD in order to gate any alarm signal present at the output of gate G3 onto the alarm wire ALM of the wire bus WB, Figure 1.

Referring to Figure 3, the microprocessor board includes a microprocessor unit PROC which is driven by an oscillator OSC. The oscillator output CLK OUT of the microprocessor unit PROC is divided down by a divider chain DC in order to cause the microprocessor unit PROC to be interrupted every three minutes.

The microprocessor unit PROC is reset at power-on, and also at any time the reset switch RST SW is pressed and causes initialisation of the program.

When an alarm signal is generated by the multiplexing board, Figure 2, the microprocessor unit PROC processes the alarm informatjon and generates appropriate memory accessing signals in order to address the digital information associated with the alarm condition stored in the memory store MS, orthe memory provided in the input/output circuitry, I/O CCTY.

To this end the microprocessor unit PROC, generates address signals on lines A8-A15 which are decoded by an address decoder ADD DCC providing enable signals EN in order to select elements of the memory store MS or elements of the memory provided in the input/output circuitry I/O CCTY.

Eight lines AD0-AD7 are used to output addresses and also to input/output data. These separate functions are time multiplexed using an address latch enable signal ALE. The signal ALE is used to trigger an octal latch LTH so that the address informaton alone can be used, and under these circumstances the signals A0-A7 are used to address the memory store MS and the memory contained in the inputs output circuitry I/O CCTY. Data is then allowed to pass in either direction on the 8-bit data lines AD0-AD7 interconnecting the microprocessor unit PROC, memory store MS and the input/output circuitry I/O CCTY.The signal IO/M is used by the memory store MS and the input/output circuitry l/O CCTY to dictate which of them is to receive a given address, and the signal together with read and write signals RD, WR generated by the microprocessor unit PROC.

The input/output circuitry I/O CCTY also generates the reset signal Stand clock signal CLK which are despatched to the multiplexing board Figure 2 and receives the alarm signal ALARM from the multiplex ing board Figure 2. The circuitry I/O CCTY also receives user inputs and generates signals STAT LPS to drive status lamps. The circuitry I/O CCTYfurther generates the data signals, DATA and standby signals STB and ready signal RDY for transmission to the speech board Figure 4, and the pulse signal P.

and switch signal SW for transmission to the watchdog timer WDT and switch SW of Figure 1. The circuitry I/O CCTY receives the reset signal RTfrom the watchdog timer WDT of Figure 1 and input signals from the communication link interface of Figure 1.

The microprocessor PROC may be constituted by an INTEL 8085A device and the input/output circuitry I/O CCTY may be constituted by an INTEL 8155 device, although it will readily be understood that alternative devices would be equally suitable.

Referring to Figure 4, the digital signals obtained from the stores on the microprocessor board in accordance with the alarm condition are passed to the octal buffers and line driver circuits OBLD and received at inputs P0-P5 and 11,12. The signals at inputs P0-P5 are passed to a speech circuit SPCH which is controlled by signals 11 and 12 by way of latch circuits LS1 and LS2, and signal STB. The speech circuit SPCH produces an analogue output signal which is passed by way of a volume control circuit VOL to an amplifier AMP. The output of the amplifier AMP drives a speaker SPK which audibly announces the monitored alarm condition. The speech circuit SPCH is further provided with a pitch control circuit comprising resistors R1-R3 and a capacitor C.

Claims (8)

1. A telelcommunications alarm system, for use in a telecommunications exchange, including a microprocessing device having a data store containing digital information in respect of all alarm conditions, monitoring means interconnecting the microprocessing device with the exchange so that detected alarm conditions are passed to the microprocessing device, store accessing means for gaining access to the information contained in the store appertaining to the detected alarm condition, and information processing means for converting the accessed stored data into signals for driving an audible announcement device.

2. Atelecommunications alarm system as claimed in claim 1 wherein the monitoring means and the microprocessing device are interconnected by means of a three-wire bus, a first wire carries alarm signals from the monitoring means to the microprocessing device, a second wire carries clock signals to the monitoring means from the microp rocessing device, and a third wire carries a reset signal from the microprocessing device to the monitoring means.

3. A telecommunications alarm system as claimed in claim 2 wherein, the monitoring means comprises a plurality of interface circuits interconnecting the exchange with the bus by way of a plurality of multiplexers arranged so that a synchronisation signal is sent on the second wire to ensure that only one multiplexer at any one time transmits on the first wire, alarm information to the microprocessing device.

4. A telecommunications alarm system as claimed in claim 1, 2 or 3 wherein, the microproces sing device is provided with input and output circuitry by way of which alarm information is received, and digital data information is sent to a number of octal buffers and line driver circuits for driving a speech circuit producing an analogue output signal for driving a speaker in accordance with the addressed stored information.

5. A telecommunications alarm signal as claimed in claim 1,2,3 or 4 wherein, a communications interface is provided for sensing user requirements, said interface having key-pad for generating MF4 tones used to interrogate the system after the tones have been decoded by a decoder circuit and passed to the microprocessing device.

6. Atelecommunications alarm system as claimed in claim 5 wherein, a watchdog timer receives regular pulses from the microprocessing device, and emits a warning signal to the communications interface if the pulses cease due to system failure or power failure.

7. A telecommunicatons alarm system substantially as described herein.

8. A telecommunications alarm system substantially as described herein with reference to Figures 1, 2,3 and 4 of the accompanying drawings.