GB2140561A

GB2140561A - Ultrasonic testing apparatus and a method of ultrasonic testing

Info

Publication number: GB2140561A
Application number: GB08413321A
Authority: GB
Inventors: William Henry Bowyer; Robert Lye Crocker; Robert Barrett Phillips
Original assignee: Fulmer Research Institute Ltd
Current assignee: Fulmer Research Institute Ltd
Priority date: 1983-05-27
Filing date: 1984-05-24
Publication date: 1984-11-28
Also published as: GB8413321D0

Abstract

The apparatus comprises a flaw detector (1) and scanning head (2) for directing test ultrasonic pulses into a sample under test and for receiving ultrasonic signals from the sample. Analogue-to-digital converter means (4) are provided for converting analogue electrical signals from the flaw detector (1) into digital signals at the same rate as the ultrasonic signals are received by the flaw detector (1) and a plurality of memory means (6) are arranged to store temporarily digital signals output from the converter means. Control means (5) pass digital signals corresponding to the ultrasonic signals produced by a given test ultrasonic pulse into a respective memory means so that the digital signals corresponding to ultrasonic signals produced by successive ultrasonic pulses are stored in different memory means and means (7) are provided for comparing the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for producing an indication of any defect in the sample under test. The apparatus effectively reduces the "noise" or "grass" in the received ultrasonic signal, especially that due to grain boundaries in alloys. The received ultrasonic signal may be reduced in frequency before conversion to a digital signal. <IMAGE>

Description

SPECIFICATION Ultrasonic testing apparatus and a method of ultrasonic testing This invention relates to an ultrasonic testing apparatus and a method of ultrasonic testing.

The requirement for improved efficiency gas turbine engines has necessitated the use of high strength materials for the critical components, for example the element carrying the blades which operates at high stresses and high temperatures.

The successful development of reliable long-life components relies heavily on ensuring that the disc from which the element and the blades are machined is free of significant defects. The favoured method of determining the life of a component is based on a fracture mechanics approach which assesses the time likely to be taken, by the largest defect in the component, to reach a critical size. It is therefore necessary that a non-destructive test is employed which is able to detect and determine the size of these defects.

At present, samples of the material to be used to form a component are subjected to ultrasonic testing wherein a flaw detector scanned across one of two parallel planar prepared surfaces of a sample directs ultrasonic pulses into the sample and detects ultrasonic signals from the sample after a pulse has been directed into the sample. The flaw detector then converts the detected ultrasonic signals into electrical signals and, for each ultrasonic pulse directed into the sample, an "A scan", that is a graph of the amplitude of the signals detected by the flaw detector against time from the critical ultrasonic pulse until detection of the ultrasonic signal reflected from the back of the sample, is displayed on a cathode ray oscilloscope.

Any echo peaks in the "A scan" between the peaks representing the original ultrasonic pulse, or, where a water-immersion test is being carried out, the ultrasonic reflection from the front face of the sample and the peak representing the reflection from the back face of the sample, may be reflections from defects in the sample. One or more voltage reference levels are therefore compared with the voltages of any peaks between the front and back face reflection peaks and, if the voltage of a peak is above a given specified reference voltage level, the peak is classified as representing a defect of unacceptable size in the sample.

An alarm may be provided to draw an operator's attention to the presence of a defect and as a further check the "A scan" displayed on the cathode ray oscilloscope is checked against a standard so that the quality of a component can be determined by comparing the defect curves produced using the sample with the standards.

If the sample does not meet the required standards, it will be rejected. Clearly, in order to avoid unnecessary expense and time, it is important that the ultrasonic testing is accurate.

Although the above-described arrangement is sufficiently accurate for steels and like materials, problems occur where the material under test is a material having a relatively large grain size and grain boundaries which are not transparent to ultrasonic signals. One example of materials in which the grain boundaries are not transparent to ultrasonic signals are the nickel based super-alloys, for example Waspalloy, which are used for producing the ele mentswhich carry the turbine blades in gas turbine engines. The presence of such non-transparent grain boundaries in a material means that the "A scan" produced during ultrasonic testing of the material will contain a large number of structural noise signals or "grass" caused by reflections from the grain boundaries.The presence of such noise signals severely limits the minimum size of defect which can be detected. In particular, an "A scan" echo is at present considered to represent a flaw or defect if it rises more than 6 dB above the "grass" so that defects producing echos smaller than 6 dB will not be detected. Thus, at present defects which give signals equivalent to a 0.635mm (0.025") diameter perfect reflector are the smallest which can be detected with confidence although it would be desirable to detect defects giving signals equivalent to a 0.255mm (0.01") perfect reflector, that is a flat bottomed circular cross-section hole. Normally the reflectivity of a real defect can be up to 4 times less than that of a perfect reflector.Moreover, some of the "grass" signals peaks may be so high, that is over 6 dB, that they are incorrectly detected as defects or flaws and what could be a usable sample is therefore rejected.

It is an object of the present invention to overcome or at least mitigate the abovementioned disadvantages while also providing real-time data processing.

According to one aspect of the present invention, there is provided apparatus for processing analogue electrical signals output by transducing means receiving signals from a sample under test into-which test pulses are directed, the apparatus comprising: analogue-to-digital converter means for converting analogue electrical signals delivered by the transducing means into digital signals as the signals from the sample are received by the transducing means; a plurality of memory means for storing temporarily digital signals output from the converter means; control means for passing digital signals corresponding to the signals produced by a given test pulse into a respective memory means so that the digital signals corresponding to signals produced by successive test pulses are stored in different memory means; and means for comparing the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for providing an indication of any defect in the sample under test.

The comparing step may accomplished in several ways. Firstly corresponding components of sequential signals may be multiplied together, so that a significant product is obtained only when all the components multiplied together have a significant value. Alternatively an average of the corresponding components may be taken or the signals may be processed some other way.

According to a second aspect of the present invention, there is provided ultrasonic testing apparatus, comprising: means for directing test ultrasonic pulses into a sample under test; transducing means for receiving ultrasonic signals from the sample after a pulse has been directed into the sample and for converting the received ultrasonic signals into corresponding analogue electrical signals; analogue-todigital converter means for converting analogue electrical signals from the transducing means into digital signals as the ultrasonic signals are received by the transducing means; a plurality of memory means for storing temporarily digital signals output from the converter means; control means for passing digital signals corresponding to the ultrasonic signals produced by a given test ultrasonic pulse into a respective memory means so that the digital signals corresponding to ultrasonic signals produced by successive ultrasonic pulses are stored in different memory means; and means for comparing the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for providing an indication of any defect in the sample undertest.

In a third aspect, the present invention provides a method of processing analogue electrical signals output by transducing means receiving signals from a sample under test into which pulses are directed, the method comprising converting analogue electrical signals delivered by the transducing means into digital signals as the signals are received by the transducing means; passing digital signals corresponding to the ultrasonic signals produced by a given test pulse into a respective memory means so that the digital signals corresponding to signals produced by successive test pulses are temporarily stored in different memory means; and comparing in comparison means the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for providing an indication of any defect in the sample under test.

In a fourth aspect, the present invention provides a method of ultrasonic testing, comprising directing test ultrasonic pulses into a sample under test; receiving in transducing means ultrasonic signals from the sample after a pulse has been directed into the sample and converting the received ultrasonic signals into corresponding analogue electrical signals; converting analogue electrical signals from the transducing means into digital signals as the ultrasonic signals are received by the transducing means; passing digital signals corresponding to the ultrasonic signals produced by a given test ultrasonic pulse into a respective memory means so that the digital signals corresponding to ultrasonic signals produced by successive ultrasonic pulses are temporarily stored in different memory means; and comparing in comparison means the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for providing an indication of any defect in the sample under test.

The present invention also provides processed data whenever produced by the apparatus of the first or second aspect and/or a method in accordance with the third our fourth aspect.

In a preferred arrangement, means are provided for displaying the analogue electrical signals produced by the transducing means corresponding to the ultrasonic signals produced by a given test ultrasonic pulse and means may also be provided for displaying output digital signals produced by the comparison means.

Preferably, the analogue electrical signals and corresponding digital signals are displayed simultaneously.

Conveniently, each memory means is arranged to store digital signals as a plurality of words and, usually, the comparison means comprise means for multiplying together the digital signals temporarily stored in two or more memory means to produce output digital signals so that the multiplying means may be arranged to multiply together corresponding words of the digital signals temporarily stored in two or more memory means. Desirably, means are provided for removing the least significant bits of each word of the output digital signals to produce words of the same length as the words temporarily stored in the memory means and, in a convenient arrangement, the multiplying means comprises a look-up table.

In a preferred arrangement, the digital signals temporarily stored in three memory means are compared by first multiplying together the digital signals temporarily stored in two memory means to produce intermediate digital signals and then multiplying the intermediate signals with the digital signals stored in the other of the three means to produce output digital signals.

Conveniently, the analogue to digital conversion is carried out at the same rate as the signals from the sample are received by the transducer.

In one particular arrangement, the analogue electrical signals are pre-processed to shift the frequency of the signals downwards before analogue to digital conversion to enable the apparatus to cope with higherfrequency signals than could normally be handled by the analogue to digital conversion means.

Four a better understanding of the present invention and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is a schematic block diagram of apparatus in accordance with the invention; Figure 2 is a schematic block diagram in more detail of parts of the memory units and processing unit of the apparatus of Figure 1; Figures 3and 4 illustrate, respectively, three dimensioned representations of "A scans" produced from the outputs from a flaw detector and the processing unit; and Figure 5 is a schematic block diagram of a modified embodiment of the apparatus.

Referring now to the drawings, Figure 1 shows an ultrasonic testing apparatus in accordance with the invention.

The apparatus comprises a flaw detector 1, for example a SONIC MKIV flaw detector, although of course another type of flaw detector may be used, which is arranged to direct ultrasonic test pulses via a scanning head 2 at a frequency of, for example, 5 MHz into a sample (not shown) of, for example, Waspalloy and to receive ultrasonic signals reflected from the sample after an ultrasonic pulse has been directed into the sample. The scanning head 2 is scanned across the sample by scanning control apparatus (not shown) so that, in a complete scan, the whole of the upper or front surface of the sample is scanned. Of course, in order to avoid spurious reflections, the front and back surfaces of the sample must be prepared so as to be planar. That is, so that any surface irregularities are of smaller dimensions than the wavelength of the ultrasonic waves.

The pulse repetition frequency (PRF) for the ultrasonic pulses directed into the sample will be normally 1000 KHz. Of course, the pulse repetition frequency and the thickness of the sample (which may be, for example, a maximum of 4 inches (101 .6mm)) must be adjusted so that the reflection pulse from the back face of the sample corresponding to a predetermined ultrasonic pulse is received before the next pulse is directed into the sample. The speed atwhich the scanning head 2 is moved is normally 0.5 or 1 ms- so that the distance the scanning head 2 is moved across the sample between pulses is 0.5 or 1 mum.

The scanning head comprises a transducer for converting ultrasonic signals received by the scanning head into corresponding analogue electrical signals. The flaw detector 1 is connected to a display unit 3 in the form of a cathode ray oscilloscope on which, for each ultrasonic test pulse, a graph is displayed. The graph shows the amplitude of the analogue electrical signals corresponding to the ultrasonic signals against time, that is an A-scan, for the period between the original transmitter ultrasonic pulse, (or, where the sample is immersed in water during testing, detection of the ultrasonic signal reflected from the front face of the sample) and the detection of the ultrasonic signal reflected from the back face of the sample is displayed.

The analogue electrical signals produced by the flaw detector 1 are also input to an analogue to digital converter 4 arranged to produce digital signals at the same rate as the analogue signals are greater by the flaw detector 1. A control unit 5 is provided to control operation of the apparatus. Thus, the control unit 5 ensures that the digital pulses corresponding to the ultrasonic signals received by the flaw detector 1 in response to successive ultrasonic pulses input to the sample are temporarily stored in respective memory units 6 which are normally random access memory units. The digital signals stored in the memory units 6 are effectively compared in a processing unit 7 which supplies a digital output signal to a display unit 8 in the form of a cathode ray oscilloscope.The output of the processing unit may also be stored in a data storage unit 9, for example, a disc storage system.

In the arrangement shown in Figure 1, three memory units 6a, 6b and 6c are provided. However, the number of memory units used can be anything from two upwards. Although the accuracy of the results obtained increases with the number of memory units 6 used, the more memory units used the slower the processing time. It has been found that using three memory units provides both an acceptable processing time of a few micro seconds and accurate results.

Figure 2 illustrates in more detail, the memory units 6 and the processing unit 7. Each memory unit 6 has storage for 5128-bit words. The addresses of each memory unit 6 are divided into sixteen sections of thirty-two words each.

The processing unit 7 (Figure 1) comprises sixteen multiplying units 10 (only three of which are shown) each of which is associated with a corresponding one of the sixteen address sections of each of the three memory units 6. Thus, as shown in Figure 2, when the digital signals corresponding to three successive ultrasonic pulses scans have been stored in respective ones of the three memory units 6a, 6b and 6c, each multiplying unit 10 accesses the first address in the corresponding thirty-two word section of each of the three memory units 6 and multiplies the words stored in the first addresses of all the memory units 6 together.Thus, as shown in Figure 2, the multiplying unit 1 0a accesses the first address in the first thirty-two word section of each of the memory units 6a, 6b and 6c, that is address 1, and multiplies the three words together while the multiplying unit 1 0b accesses the first address in the second thirty-two word section of each memory unit, that is address 33 and multiples the three words together, and so on. In the particular arrangement being described, the digital ASC1 1 (American standard code for information interchange) characters representing the words stored in the memory means are multiplied. The multiplying unit may either actually effect the multiplications each time, or preferably, because there are only a limited number of combinations, a look-up table may be used.

The multiplied output from each multiplying unit 10 is passed to an output memory store 12 via a respective device 11 which acts to remove the least significant bits of the multipled output so as to form an 8-bit word. Each 8-bit word is stored in an address in the output memory store 12 corresponding to the address in which the digital signals were stored in the memories 6. The multiplying units 10 then access the address containing the next word in the corresponding thirty two word section of the memories 6 and multiply these three words together. Thus, the multiplying unit 1 0a accesses the address containing the second word of the respective 512 word stored in each of the memories 6, multiplying unit 10b accesses the address containing the thirty fourth word, multiplying unit 1 Oc accesses the address containing the sixty sixth word and so on. The process continues until each word of each memory 6 has been accessed and multiplied with the corresponding words in the other memories 6.

The resultant 8-bit words produced by the least significant bit removing devices are stored in the output memory 12 of the processing unit 7 at addresses corresponding to the addresses of the original words stored in the memories 6.

The described multiplying technique effectively a comparing technique. If any one of the three words multiplied together so zero or very small, the resultant product will be small. It is only if all three words are of significant size that a significant product is generated. Thus effectively the described arrangement compares the words in corresponding addresses in the samples and provides an indication when all three of the compared words have a significant value.

The words stored in the output memory 12 are output to a display circuit 8 in the form of a cathode ray oscilloscope which provides a modified "Ascan" of the output showing the presence of any defects more clearly than they are shown by the analogue electrical output of the flaw detector 1, because although the "grass" and noise signals may change from scan to scan, any defect signal remains relatively stable so that multiplying the digital signals together produces a modified "A-scan" in which the noise and "grass" signals are reduced relative to any defect signal. The A-scans shown on both the display unit 3 and the display unit 8 may be compared with reference voltage levels so that an audible visual alarm is provided to an operator when a peak of either "A scan" between the original and back reflection pulses exceeds a certain height.The display on the display unit 3 serves as a safe-guard so that the operator can check that the processing unit is operating correctly.

When the results of the comparison of the first three sets of digital signals corresponding to the first three ultrasonic pulses have been determined, the digital signals corresponding to the first ultrasonic pulse are removed from the memory 6a and replaced by the digital signals corresponding to the fourth ultrasonic pulse and the comparison is begun again. This process is repeated for each ultrasonic pulse with the signals that have been stored in the memory 6 for the longest period of time being replaced by the fresh signals, and the results of each comparison are displayed on the display unit 8.

The "A-scans" displayed on the output display unit 3 and the modified A-scan displayed on the display unit 8 may be stored in respective memories and a three dimensional graph may be produced illustrating the changes in the "A-scans" with distance along the sample produced for both the unprocessed data from the flaw detector and the processed data output by the processing unit 7. The display units 3 and 8 may be, for example, Textronix type 468 digital oscilloscopes although, of course, other suitable display units could be used. The three dimensional graphs may be built up on the respective visual display units or may be printed out, in plan view, by for example, a thermal or dot matrix printer which provides a higher ink density for higher peaks. Such a technique enables defects to be detected more accurately than previously and allows their size and position to be estimated.

Figure 3 is a three dimensioned graph of the "A-scans" produced against distance where the sample was formed of Waspalloy with a metal path of 38.1 mm. The sample had a 1.27 mm flatbottomed hole as a defect. Figure 4 is a three dimensional graph of the modified "A-scans" showing the reduction in the "grass" peaks and indicating clearly the presence of a defect.

Although the arrangement shown in Figures 1 and 2 can be used for processing "A-scans" produced using a 5MHz ultrasonic test pulse frequency, it is desirable that an arrangement be provided in which the processing time for processing the "A-scans" is as short as possible so that one complete set of "A-scans", that is three "A-scans", can be processed in one scan interval. Thus, with a typical scan rate of 1 scan per millisecond, a scan duration of 50 microseconds and an excitation or test pulse at 5 MHz of three microseconds duration, the apparatus must be able to multipy 3000 data values and output the modified "A-scans" in approximately 1 millisecond if the processing of the data is to keep pace with the in-coming "A scans".

Figure 5 is a schematic block diagram which illustrates a modified embodiment of the apparatus which is designed to be able to process one complete set of scans in one scan interval as described above.

Referring now to Figure 5 the returning ultrasonic signals received by the scanning head and converted into electrical signals by the transducer are supplied via a low-pass anti-aliasing filter 13 to an 8-bit analogue- to - digital convertor 14 which is a very fast monolithic circuit device of the flash convertor type having a sampling frequency of 20 MHz.

Digitised data output by the analogue - to - digital convertor 14 is supplied to one of three 8K random access memories (RAM) 15 under the control of a controller/-sequencer 16 clocked bythetrigger (not shown) which triggers excitation of the test ultrasonic pulse. Thus, under the control of the trigger, the controller/sequencer 16 will enable, in sequence, data representing a first "A-scan" to be written into a first one of the RAMS 15A, data representing a second "A-scan" to be written into a second one of the RAMS 15B and finally data representing a third "A-scan" to be written into a third one of the RAMS 1 SC by supplying appropriate write-enable signals to the RAM integrated circuits. An address counter 22 provides the appropriate address signals to the RAM 15.

A digital signal processing circuit 17 in the form of a single fast integrated circuit combining a multiplier and an accumulator is provided to multiply the "A-scans" stored in the RAM integrated circuits 15.

The digital signal processing integrated circuit 17 is capable of performing 8 x 8 bit multiplication processes in less than 500 nanoseconds and has a buffered output to permit chain multiplication.

Thus, in the arrangement shown in Figure 5, the digital processing circuit 17 first of all multiples the A-scans stored in RAMS 1 5A and 15B bit by bit. The result of this multiplication is fed back to the input of the digital processing integrated circuit 17 where it is multiplied with the "A-scan" data read from the other RAM integrated circuit 1 5C. The controller/ sequencer 16 provides an output enable signal to a gate 17A of the digital signal processing circuit 17 which is timed to occur when the two step multiplied cation process has been completed.The processed data is supplied via the gate 17A to an 8/12 bit digital - to - analogue convertor 18 operating at a sampling frequency of at least 1 MHz The analogue output of the digital - to - analogue convertor 18 is supplied to the video input of an osciloscope or similar visual display unit to display the modified "A-scan" to the operator. The output of the 8/12 bit digital - to analogue convertor 18 is also supplied to a threshold detector circuit 19 which comprises one or more gated threshold detectors 1 9A and logic for controlling the operational intervals thereof and for adjusting the threshold at which the threshold detectors 1 9A actuate a warning alarm (not shown) when a peak of the modified "A-scan" is higher than the threshold level indicating the presence of a defect.

The digital output of the digital signal processing integrated circuit 17 may also be supplied to an 8K random access memory 20. Preferably, writing into the memory 20 is enabled only when the threshold detector circuit 19 provides an alarm signal. Thus, when the threshold detector 19 provides an alarm signal indicating that a defect has been detected in the sample, the data for the modified "A-scan" in which the defect or flaw was detected can be stored in the memory 20 for further processing. Of course, additional memory space could be provided to enable several modified "A-scans" to be stored for additional processing. The contents of the memory 20 may be read and output via the digital - to analogue convertor 18 or alternatively, may be output in a digital form for supply, for example, to a computer.

As described above, the controller/sequencer circuit 16 is controlled by the trigger for the ultrasonic test pulse. It will, however, be appreciated that the processing technique relies on the variability of both the "grass" and noise signals and the relative stability of the defect signal and that, if the linear scanning speed of the flaw detector was reduced but the pulse repetition frequency was maintained at its previous frequency, then the processing efficiency would be reduced because there would be at least some correlation between the grass signals produced by the grain boundaries. The processing system described relies, of course, on the grass signals produced by the grain boundaries being essentially un-correlated so that these signals are minimised relative to any defect signals when adjacent A-scans are multiplied.Therefore, by taking A-scans at selected intervals (corresponding to a fixed linear scan distance) the maintanence of satisfactory operating and processing can be ensured. Accordingly, a divide-by-n by circuit 21 is preferably incorporated in the trigger circuit to allow the apparatus to skip a nominated number of scans between ones selected for processing. Thus, the divide-by-n circuit 21 allows the variability in scanning speeds and pulse repetition frequency which is found in practice to be catered for.

The use of a very fast monolithic integrated circuit device of the so-called flash-convertor type for the input analogue - to - digital convertor 14 and the use of a single fast integrated circuit combining a multiplier and an accumulatorto provide a digital circuit processing circuit which is capable of performing a multiplication process in less than 0.1 microseconds and, in addition, has other functions, notably, addition or subtraction functions, will permit expansion at a later date to more complex processing, for example, allowing the comparison or averaging of more than three scans or the provision of further functions, for example digital alarms.To support such an arrangement, it is envisaged that the entire apparatus will be provided in a very modular fashion and that conventional expansion facilities such as spare card slots, extra power supply capacity etc, will be provided in the apparatus.

The apparatus described above in relation to Figure 5 enables processing of "A-scan" data produced by an ultrasonic test pulse frequency of up to approximately 10 MHzto be carried out in "realtime". However, in view of the fact that the higher the test pulse frequency used, the better the "near surface" inspection of the sample and therefore the smaller the amount of material which must be removed from the sample after inspection to ensure that the sample is fault-free, it is desired to use as high a test pulse frequency as possible. Although the apparatus shown in Figure 5 could be modified by the addition of higher speed processing integrated circuits, such circuits are at the forefront of technology and the cost of using such circuits would considerably increase the overall cost of the apparatus.Accordingly, it is proposed to provide a pre-processing unit between the flaw detector 1 and the analogue - to - digital convertor to reduce the frequency of the signal supplied to the 8 bit analogue to digital convertor 14.

In practice, the return signals from the sample are not simple peaks and troughs of the form shown in Figures 3 and 4 but in fact are modulated by the frequency of the test pulse. Thus, if a test pulse frequency of 20 MHz is used, then a modulation at 20 MHz will be impressed upon the return signals from the sample received by the flaw detector. The Shannon or Nyquist sampling theorem dictates that a sampling frequency of at least twice, and in practice three times, the frequency of the signals being digitised must be used if correct results are to be obtained. Accordingly, in order to digitise return signals having a 20 MHz modulation inpressed thereon, a sampling frequency approaching 60 MHz would be required in practice. Thus, the ususal analogue to digital convertors which sample at approximately 15 or 25 MHz would not be suitable for sampling such a signal. Accordingly, an arrangement is necessary whereby the mean frequency, that is 20 MHz of the return signal can be reduced. It is therefore proposed to provide a pre-processorwhich in effect shifts the mean frequency of the return pulses from 20 MHz down to approximately zero by demodulating the return signals at 20 MHz. Thus, the original return signal which would, in frequency space, have had an essentially gaussian form centred on the 20 MHz frequency and a half-width of approximately 10 MHz is shifted to a signal centred on the zero frequency axis so that the two halves of the gaussian form overlap and the frequency spread of the signal is approximately 10 MHz which is within the processing capabilities of the analogue to digital convertor 14.

In particular, it is proposed to provide a preprocessing device in which the analogue electrical signals from the transducer are separately sampled or demodulated by a sinusoidal and a cosinusoidal signal at the 20 MHz frequency. Each sampled signal is then filtered by a low-pass filter passing frequencies in the range 0 to 7 MHz and the filtered signals are then squared and combined to produce the processed signal for supply to the analogue -to digital convertor 14.

With apparatus incorporating such a preprocessing device, ultrasonic test pulses having a frequency of up to 30 M Hz may be processed by the apparatus.

Thus, the apparatus and method described provides allows the data resulting from ultrasonic testing of a sample to be processed in real-time allowing an operator to determine almost immediately, with a higher degree of accuracy than provided herebefore, whether the sample contains any unacceptable defects. In particular, apparatus and a method embodying the invention may allow defects of at least down to 0.017 inches (0,.43 mm) to be detected.

Of course, alternative methods of combining the words stored in the memories 6 may be used, for example, the average of two or more A-scans may be taken. Moreover, the "A-scans" compared by the processing unit need not necessarily be adjacent scans.

Claims

1. Apparatus for processing analogue electrical signals output by transducing means receiving signals from a sample under test into which test pulses are directed, the apparatus comprising: analogue to - digital convertor means for converting analogue electrical signals delivered by the transducing means into digital signals as the signals from the sample are received by the transducing means; a plurality of memory means for storing temporarily digital signals output from the convertor means; control means for passing digital signals corresponding to the signals produced by a given test pulse into a respective memory means so that the digital signals corresponding to signals produced by successive test pulses are stored in different memory means; and means for comparing the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for providing an indication of any defect in the sample under test.

2. Ultrasonic testing apparatus, comprising: means for directing test ultrasonic pulses into a sample under test; transducing means for receiving ultrasonic signals from the sample after a pulse has been directed into the sample and for converting the received ultrasonic signals into corresonding analogue electrical signals; analogue - to - digital converter means for converting analogue electrical signals from the transducing means into digital signals as the ultrasonic signals are received by the transducing means; a plurality of memory means for storing temporarily digital signals output from the convertor means; control means for passing digital signals corresponding to the ultrasonic signals produced by a given test ultrasonic pulse into a respective memory means so that the digital signals corresponding to ultrasonic signals produced by successive ultrasonic pulses are stored in different memory means; and means for comparing the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for providing an indication of any defect in the sample under test.

3. Apparatus according to Claim 1 or 2, wherein means are provided for displaying the analogue electrical signals produced by the transducing means corresponding to the signals produced by a given test pulse.

4. Apparatus according to Claim 1,2 or 3, wherein means are provided for displaying output digital signals produced by the comparison means.

5. Apparatus according to Claim 1 or 2, wherein means are provided for displaying simultaneously the analogue electrical signals produced by the transducing means corresponding to the signals produced by a given test pulse and the corresponding output digital signals produced by the comparison means.

6. Apparatus according to any preceding claim wherein each memory means is arranged to store digital signals as a plurality of words.

7. Apparatus according to any preceding claim, wherein the comparison means comprise means for multiplying together the digital signals temporarily stored in two or more memory means to produce output digital signals.

8. Apparatus according to Claim 7 when dependent on Claim 6, wherein the multiplying means is arranged to multiply together corresponding words of the digital signals temporarily stored in two or more memory means.

9. Apparatus according to Claim 8, wherein means are provided for removing the least significant bits of each word of the output digital signals to produce words of the same length as the words temporarily stored in the memory means.

10. Apparatus according to Claim 7,8 or 9, wherein the multiplying means comprises a look-up table.

11. Apparatus according to Claim 7, wherein the plurality of memory means comprises three memory means and the multiplying means is arranged first to multiply together the digital signals temporarily stored in two memory means to produce an intermediate digital signal and then to multiply the intermediate digital signal with the digital signal temporarily stored in the other memory means to produce output digital signals.

12. Apparatus according to any preceding claim, wherein pre-processing means are provided to shift the frequency of the analogue electrical signals downwardly before supplying the same to the analogue-to-digital convertor means.

13. Apparatus according to any one of claims 1 to 12, wherein the analogue - to - digital converter means is arranged to convert analogue electrical signals into digital signals at the same rate as the signals from the sample are received by the transducing means.

14. A method of processing analogue electrical signals output by transducing means receiving signals from a sample under test into which test pulses are directed, the method comprising converting analogue electrical signals delivered by the transducing means into digital signals as the signals are received by the transducing means; passing digital signals corresponding to the signals produced by a given test pulse into a respective memory means so that the digital signals corresponding to signals produced by successive test pulses are temporarily stored in different memory means; and comparing in comparison means the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for providing an indication of any defect in the sample under test.

15. A method of ultrasonic testing, comprising: directing test ultrasonic pulses into a sample under test; receiving in transducing means ultrasonic signals from the sample after a pulse has been directed into the sample and converting the received ultrasonic signals into corresponding analogue electrical signals; converting analogue electrical signals from the transducing means into digital signals as the ultrasonic signals are received by the transducing means; passing digital signals corresponding to the ultrasonic signals produced by a given test ultrasonic pulse into a respective memory means so that the digital signals corresponding to ultrasonic signals produced by successive ultrasonic pulses are temporarily stored in different memory means; and comparing in comparison means the digital signals temporarily stored in one memory means with the digital signals temporarily stored in one or more other memory means to produce output digital signals for providing an indication of any defect in the sample under test.

16. A method according to Claim 14 or 15, further comprising displaying the analogue electrical signals produced by the transducing means corresponding to the signals produced by a given test pulse on display means.

17. A method according to claim 14, 15 or 16 further comprising displaying output digital signals produced by the comparison means on display means.

18. A method according to Claim 14 or 15 wherein the analogue electrical signals produced by the transducing means corresponding to the signals produced by a given test pulse and the corresponding output digital signals produced by the comparison means are displayed simultaneously on display means.

19. A method according to any one of Claims 14 to 18, wherein each memory means temporarily stores the digital signals as a plurality of words.

20. A method according to any one of Claims 14 to 19, wherein the step of comparing the digital signals temporarily stored in the memory means comprises multiplying together the digital signals temporarily stored in two or more memory means to produce output digital signals.

21. A method according to Claim 20 when de pendant on Claim 19, wherein corresponding words of the digital signals temporarily stored in two or more memory means are multiplied together.

22. A method according to Claim 21, wherein the least significant bits of each word of the output digital signals are removed to produce words the same length as the words temporarily stored in the memory means.

23. A method according to Claim 20,21 or 22, the multiplying step comprises using a look-up table.

24. A method according to Claim 19, wherein the step of comparing the digital signals comprises first multiplying together the digital signals temporarily stored in two memory means to produce intermediate digital signals and then multiplying the intermediate digital signals with the digital signals temporarily stored in another memory means to produce output digital signals.

25. A method according to any one of claims 14 to 25, further comprising pre-processing the analogue electrical signals to shift the frequency of the analogue electrical signals downwardly before converting the analogue electrical signals into digital signals.

26. A method according to any one of claims 14 to 24, therein the analogue electrical signals are converted into digital signals a the same rate as signals from the sample are received by the transducing means.

27. Apparatus for processing analogue electrical signals output by transducing means receiving signals from a sample under test into which test pulses are directed, substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

28. Ultrasonic testing apparatus substantially as hereinbefore described with reference to, and as illustrated in the accompanying drawings.

29. A method of processing analogue electrical signals output by transducing means receiving signals from a sample under test into which test pulses are directed, substantially as hereinbefore described with reference to the accompanying drawings.

30. A method of ultrasonic testing substantially as hereinbefore described with reference to the accompanying drawings.

31. Processed data whenever produced by the apparatus of any one of Claims 1 to 13,27 and 28 and/or a method in accordance with any one of Claims 14to 26, 29 and 30.

32. Any novel feature or combination of features described herein.