GB2139844A - Regulating scanning lines of an image reproducing system - Google Patents

Abstract

Image data, eg for facsimile reproduction, after digitizing is treated by matrix processing such as fast fourier transform, which requires several (N) successive scan lines of elements to be available at the same time. To avoid sequential loading and unloading lines of digital buffer memory, each line in turn is fed into latch 31a and directly out via latch 32a to a shift register. Simultaneously the line is also fed from latch 32a to the data input of line memory 31b. Memory 31b already holds the previous line, and as this is read out through latch 32b to the shift register and to memory line 31c, the next line is written in to 31b in its place. As each of the (N-1) memories are read out, they are refilled by the following line, the data stored in the last memory (31e) being discarded. After data has been loaded into the shift register, a processing circuit calculates according to the required algorithm. <IMAGE>

Description

SPECIFICATION A method and system for regulating image data of scanning lines of an image reproducing system Field of the invention This invention relates to a method and system for regulating image data of scanning lines of an image reproducing system in which image data of several scanning lines of an original picture are once stored in a buffer memory, and are output in parallel to undergo necessary processes, particularly to such a method and system in which the image data of scanning lines are put in due order in the buffer memory.

Background of the invention Conventionally in an image reproducing system such as a scanner or a facsimile, image data obtained by scanning an original picture undergo analog/digital conversion and are once stored in a buffer memory to be submitted to necessary processes.

In a case data of a pixel must be submitted to a process such as a two-dementional digital filtering process or a two-dementional FFT (fast fourier transformation) process in compliance with data of surrounding pixels of the pixel, image data of the pixels must be output from the buffer memory in due order of input scanning. The following explanation is based on a case data of one pixel located at the center of 3x3 pixels in matrix are processed. At first, digital image data obtained by an input device 1 are input via a multiplexer 2 to a buffer memory 3 composed of three line memories A, B and C, wherein data of the first, the second and the third scanning lines are stored in the line memories A, B and C respectively. Then the image data of each scanning line are read to a shift resister 4.However in this condition, there is no need to regulate the image data of their scanning order because they are already in the proper line memories. When image data of the pixels on the second scanning line are processed, the data of the second and the third scanning lines still reamin in the line memories B and C respectively. And image data of the fourth scanning line are brought to the line memory A. When the image data on the line memories A, B and C are read to the shift register 4 as they are, they are in order of that of 4th, 2nd and 3rd scanning lines. So a data order regulator 5 is provided in between the buffer memory 3 and the shift register 4 to rearrange the image data in order of that of 2nd, 3rd and 4th scanning lines.

Conventionally, there are several circuits as the data order regulator 5. One of them is as shown in Figure 2. In Figure 2, when the number of the scanning lines is n, n2 tri-state buffers 52(52a to 52i) are employed to regulate the image data of the scanning order. Precisely, the image data of the scanning lines stored in the buffer memory 3 are input to latches Sia, Sib and Sic respectively in order of their sampling order synchronizing with a system clock S. While a start signal S2 which is output from the input device 1 every time a new scanning line begins to be scanned is input to a trinary counter 53. A two bit signal from the trinary counter 53 is input to a decoder 54, wherein the output signal changes its data form for example from 01 to 10, 10 to 11.The decoder 54 opens the tri-state buffers 52a, 52d and 529 when the signal has the data form of "01", the tri-state buffers 52b, 52e and 52h when the signal has the data form of "10", or the 52c, 52f and 52when the signal has the data form of "11". Moreover output lines of the tri-state buffers 52a to 521 are connected as shown in Figure 2, image data from the latches 51a, Sib and Sic are output in due input scanning order.

However, this kind of circuit requires n2 tri-state buffers also bringing about higher cost of the systme in which it is employed.

To resolve the problem, a circuit which is permitted to haven tri-state buffers used time-sharingly can be employed as shown in Figure 3.

That is, at first data of each scanning line read from a buffer memory are brought to latches 55(55a,55b and 55c) on command of the system clock S1.

On the other hand, a control signal S5 having the three-fold frequency of the system clock S, is input to a trinary counter 59A of a control circuit 59.

A decoder 59B decodes an output from the trinary counter 59A to open tri-state buffers 56(56a, 56b and 56c) time-sharingly.

Furthermore, the control signal S5 is input to another trinary counter 59D too. A decoder 59E decodes an output from the trinary counter 59D to control latches 57(57a, 57b and 57c). Namely, the image data output from the tri-state buffers 56 time-sharingly are brought to the latches 57 time-sharingly by the output signal of the decoder 59E. Every time a start signal S2 is input to the counter 59c, an output signal from the trinary counter 59c changes its data form for example from a transition of (a) 01 - 10 - 11 to (b) a transition of 10 - 11 01, from (b) the transition of 10 - ii - 01 to (c) a transition of 11 - 01 - 10. Opening timing of the latches 57 are controlled according to the transition of the output data form of the counter 59c to regulate the data order for the latches 57.Therefore the latches 57 hold the image data regulated of the sampling order, and the data are brought to latches 58(58a,58b and 58c) synchronizing with the system clock Si.

However, supposing that n scanning line data are regulated in a sampling cycle V, the minimum time To of the time the data from the buffer memory are brought via the tri-state buffers 56 to the latches 57 must satisfy the equation Vo < Vln. So if the value n is great enough, this circuit might lose management of the regulation work.

Figure 4(a)(b) show another regulator and timing pulses for controlling the regulator respectively.

That is, data of each scanning line read from a buffer memory are brought to latches 60(60a, 60b and 60c) synchronizing with the system clock S, are input to multiplexers 61(61 a, Sib and 61c) which is controlled by a selection signal S6. When the terminal A of the multiplexers 61 are selected by the selection pulse S (for example time ti to t2 or t3 tot4), the data of each scanning line from the latches 60 are input to latches 62(62a, 62b and 62c). When the terminal B of the multiplexers 61 are selected (for example time t2 to t3 or t4 to 5), the data of each scanning line from the latches 62 are transferred to respective adjacent data lines on command of a control signal Sg output from an AND-gate 64.This AND-gate 64 is opened by a mode signal S7-i (S7 0, S71 and S72), which becomes S7-2 when no transfer is required, becomes S7-1 when one-time transfer is required, becomes S70 when two-times transfer is required. Thus regulated image data of each scanning line are brought to latches 63(63a, 63b and 63c) to be output to the next shift register on command of the system clock S.

However, even this circuit loses its capability of the regulation work when Vln (n: the number of scanning lines being processed together, V: sampling cycle) is not more than To (To: a time the image data are transferred from the latches 60 to the latches 63).

As against to the abovementioned three methods in which image data of each scanning line are once stored in a buffer memory and undergo order regulation process when they are read from the buffer memory, conventionally a circuit as shown in Figure 5 is also used as a data order regulator.

In the circuit shown in Figure 5, image data of each scanning line from the input device are transferred to a charge coupled device (CCD) 71b having a capacity corresponding to that of image data of one scanning line via three latches 72a", 72a' and 72a provided in a shifting circuit 72 in series on command of the system clock S, in the sampling order. Then the image data held on the CCD 71b are transferred to a CCD 71c via three latches 72,0,72,0' and 72b provided behind the CCD 716. When the image data of the third scanning line are output from the latch 72a, the image data of the second and the first scanning lines are output from the latches 72b and 72c respectively.At the same time, the data of the third and the second scanning lines are transferred to the CCD 71b and CCD 71c respectively. Consequently, image data regulated of the sampling order are output from the latches 72a, 72b and 72c.

However, as the CCD is ordinarily fixed to have a capacity equivalent to data capacity of one scanning line, if the data capacity varies, additional CCDs are necessary, which is also a defect. In addition, the CCD can only afford to output image data in due order, which also means the CCD can't perform random access reading of the image data. Even if a CCD having a random access function is used instead, it can operates in about 100 sec, which means no suitability of the CCD for a real time processing.

Furthermore, the CCD can output data of a pixel only when data of another pixel are input to it. In this, the CCD can operates only in a condition the writing speed of the data into the CCD is equivalent to the sampling speed.

Summary of the invention The method of this invention is proposed in reflection to abovementioned problems.

A main object of this invention is to employ a random-access buffer memory as a constituents of a data order regulator.

The principle of this invention is at first image data of each scanning line are held on respective line memories, and then the image data of each scanning line are output in parallel simultaneously from the line memories. At the same time, the image data of each scanning line are transferred to the adjacent line memory (from which the data of the next youngest scanning line are just output).

In a case multiple (P) line memories are provided for processing data of one scanning line, a maximum of P pixel data can be processed at a time as far as T (the cycle time of the buffer memory) 'P (the sampling time).

In this, a latch can be substituted for the line memory for the present scanning line.

The above and other objects and features of this invention can be appreciated more fully from the following detailed description when read with reference to the accompanying drawings.

Brief description of the drawings Figure 1 shows a conventional data order regulation system.

Figure 2 shows a conventional data order regulator.

Figure 3 shows another conventional data order regulator.

Figure 4 shows yet another conventional data order regulator.

Figure 5 shows a conventional data order regulator in which charge coupled devices are employed.

Figure 6shows the conception of this invention.

Figure 7 shows the detail of an embodiment of this invention.

Figure 8 shows the timing chart of the circuit shown in Figure 7.

Figure 9 shows an embodiment of this invention for high-speed processing.

Figure 10 shows the timing chart of the embodiment shown in Figure 9.

Preferred embodiment of this invention Figure 6 shows an embodiment of an image reproducing system to which the method of this invention is applied.

In an input device 1, analog image data obtained by scanning an original picture (pictures or line-work drawings) for example placed on an original picture drum are converted into digital data, and the digital data are input to a buffer memory 30.

On the other hand, a rotary encoder is caoxially conecterd to the original picture drum. The rotary encoder outputs a one pulse every one revolution of the drum, and an pulse n times in one revolution of the drum to a timing pulse generator 6. The timing pulse generator 6 outputs a system clock signal S1 for controlling whole the system and a start signal S2 for designating scanning start timing of each scanning lines into an address counter 7.This address counter 7 generates an address signal Sa for writing or reading the image data into or from the buffer memory 30 according to said two signals S, and 52. While the timing pulse generator 6 generates a request signal S4 for controlling access timing of the image data to the buffer memory 30 and an enabling signal S3 for writing or reading the image data into or from the buffer memory.

The buffer memory 30 comprises S minus 1 line memories (S:; the number of data lines to be regulated together) and a latch for the data of the present scanning line. In thus constructed circuit, image data of each scanning line are regulated of the sampling order to be output to a shift register 4.

In the case of Figure 4, image data corresponding to the number of necessary data lines in the main and subscanning directions (in this case, it is 5x5 in matrix) are input to a processing circuit 8 to undergo necessary processes according to the type of used system. For example in a color scanner, a halftone dot generator 9 generates a signal corresponding to a contact screen by using the image data and the signal is input to an output head 10 to drive a recording beam.

Figure 7 shows a detailed embodiment of the buffer memory 30 in which image data of five scanning lines are regulated at a time, and Figure 8 shows the timing chart of the buffrer memory shown in Figure 7.

The buffer memory 30 comprises one latch 31a and S minus 1 line memories (S: the number of data lines to be regulated together) 31b to 31e. Assuming that data of the 1st scanning line D11, D12 are input to the line memory 31e, data of the 2nd scanning line D21, D22 are input to the line memory 31 d, data of the 3rd scanning line D3a, D32 are input to the lineD41, D42 are input to the line memory 31b, and data of the 5th (present) scanning line D51, D52...are transferred to the latch 31a successively (the formation profcess of this condition is omitted), the data are processed as follows.

The image data of scanning lines li to 14 are output from the line memories 31b to 31e respectively at the time ttime after when the cvontrol signal S3 is "H"(high) and the request signal S4 falls to "L"(low). Then the image data of each scanning lines are brought to latches 32a to 32e respectively when a system clock signal S,' rises.

Meanwhile image data of present scanning line 15 are brought to a latch 31 a synchronizing with the rise time of the system clock S1 and then transferred to a latch 32a synchronizing with the rise time of the system clock S,'.

The image data held on the latches 32a to 32e are output simultaneously to a shift register synchronizing with the fall time of the system clock Sa . At the same time, the data from the latches 32a to 32d are transferred to respective adjacent line memories 31b to 31e. Consequently, the image data of the scanning lines 15, 14, 13 and 12 are stored into line memories 31b to 31e respectively. Therefore, the image data regulated of their scanning line number are output from the line memories 31b to 31 e and the latch 31a via the latches 32a to 32e.

The data D51, D41, D31 and D21 of respective scanning lines are transferred from respective latches 32a, 32b, 32c and 32dto respective line memories 31b, 31c, 32dand 32e as follows.

In Figure 8, when the control signal S3 is "L" and the request signal S4 is "L" (the time T(b)), any data can be written into the line memories 31 b to 31e. When the address 1 of respective line memories 31 b to 31e are used then, they are vacant in the time Tta). Therefore, said data D51 to D21 are written into the line memories 31 b to 31e respectively in the time T(b). Likewise, the data D52 to D22 and the data D53 to D23 are transferred to the address 2 and 3 of respective line memories 31b to 31e. In this, the image data of the scanning line li stored in the line memory 31 e are not necessarily transferred to any other line memories, in other words they can be abndoned as far as for the purpose of data regulation.

Incidentally, the abovementioned embodiment lose its operation when the cycle time 2T of the buffer memory is more than one half of that of the system clock S1 for dominating the sampling frequency.

Figure 9 shows an embodiment of the method of this invention in which the sampling of image data is performed P times in a cycle time 2T of the buffer memory 30.

In Figure 9, a memory device comprises P latch units 33aw (i: 1, 2 P) to which image data as shown in Figure 10 are directly input synchronizing with the system clock Si and line memories 33b-i, 33,i.....(i: 33c- (i: 1,2 each of which has a capacity of more than I/P of that of the data on one scanning line.

Supposing that image data of each scanning line are stored in the line memories 33b-i, 33c-j...as shown in Table 1 (the formation process of the data are omitted here), the device shown in Figure 9 operates as follows.

Image data of the 5th scanning line 511 ...51 P, 521...52P are successively brought to the latches 33ai and input to latches 34b-iimultaneously synchronizing with a timing pulse S. in this, image data of 1st, 2nd, 3rd....Pth pixels on the 5th scanning line are brought to latch units 34be1, 34b-2, 34b-334b-P respectively synchronizing with the pulse S.

Then the line memories 33b-i, 33c j...output one pixel data in one cycle time 2T of the buffer memory (the P sampling cycle) to subsequent latchesa 35b-i,35c j...synchronizing with a timing pulse Ss. Namely, data can be output from each line memories during a time T)a), when the request signal S4 is "L" and the control signal S3 is "H".In this condition, the image data of 1st, 2nd, 3rd...Pth pixels of respective scanning lines 14, 13, 12, li are output from the memories at the time ttime after when the request signal 54 falls as shown in Figure 10, and are brought to the atches 35b4 354...synchronizing with a timing pulse Se. The image data held on the latches 35b.i, 35C j...are output via tri-state buffers 36buzz 36i...as follows during the cycle time 2T.

Said tri-state buffers 36b 364...are opened every cycle time 2T successively on command of a timing signal S7 j. Precisely, at first the tri-state buffers 36b 1,36C n ...are opened, secondly the tri-state buffers 36h-2 36c2...are opened, at last the tri-state buffers k36,,.p, 36c.p... are opened, and this process is repeated every cycle of the cycle time 2T. Consequently the image data of the pixels 111 to 11 P, 212 to 21 P, 311 to 31 P...of respective lstto 4th scanning lines are outputsuccessivelyfrom thetri-state buffers3S.i, 36b p...36b p...36C 1...36e p. On the other hand, as the image data of the pixel of the present scanning line 15 are successively brought to the latch 33a-1 and are output, the image data of the scanning lines 15, 14, 13, 12 and 11 are output in parallel as a result.

Meanwhile, the image data output from the line memories 33b-, 334...via the latches 35b-i, 3504...and the image data output from the latch 33a-1 are transferred to the addresses from which the last data are just output of the adjacent line memories 33b-i, 33c4.., Assuming that the image data of 1st, 2nd, 3rd...Pth pixels on each scanning line are transferred to each adjacent scanning line, the detail is as follows.

As shown in Figure 10, any data can be written into the line memories 33b-i, 33C-iess while the request signal S4 is "L" and the control signal S3 is "L". And the address 1 of each line memories 33h4 33C-P or are vacant because the previous data in the address 1 are already output in the time T)a)'. Therefore, image data 511 to 51 P...21 1 to 21 P read from the respective latches 33a-i, 35b-i, 35c-,'.. are transferred to the address 1 of each line memories 33b-1, 33c-j ...in the time T)b)'. In the next cycle time, consequently the data of the scanning lines 15, 14...are stored in the line memories 33b-i, 33-i... Of course the data of present scanning line 16 are output from the latch 33a-ir so image data regulated of the scanning line order can be obtained.

Although in the embodiment shown in Figure 9, image data of P pixels are written or read simultaneously into or from the buffer memory, such process can be carried out for each of the image data of P pixels in every cycle of 2T/P.

As mentioned above, the method of this invention is capable of putting image data of each scanning line in due order by using line memories provided in a buffer memory. Therefore, in the method of this invention, increase of the number of the buffer memory can cover increase of the number of the scanning lines to be processed without providing other circuits. In addition, use of the buffer memory brings about a shorter processing time and a random access function. When the sampling time of the image data is too rapid for the cycle time of the buffer memory, image data of one scanning line can be stored into P line memories (P: the number of sampling cycle in a cycle time of the buffer memory), and then output from each of the P line memories successively for the purpose of regulating data order.

TABLE 1 Input order of the Address number Line memories image data ofthe to be used of having the scanning lines each memory image data 14to li 11 12 13 14 111 211 311 411 1 (b-1)(c-1)..

11P 21P 31P 41P 1 (b-P)(c-P)...

121 221 321 421 2 (b-1)(c-1)...

12P 22P 32P 42P 2 (b-P)(c-P)...

131 231 331 431 3 (b-1)(c-1)...

13P 23P 33P 43P 3 (b-P)(c-P)...

I I

Claims (7)

1. A method of regulating image data of scanning lines of an image reproducing system in which data of plural scanning lines are stored in a buffer memory and then arranged in due scanning line order comprising steps of: (a) storing the image data of certain scanning lines in a buffer memory; (b) outputting the image data of the scanning lines from the buffer memory simultaneously; and (c) transferring the image data of each scanning line to an address from which the image data of respective previous scanning lines are output.

2. A method claimed in Claim 1 in which the image data of the scanning lines are stored in S minus 1 line memories where S is the number of the data lines to be regulated, and the image data of pixels of the present scanning line are brought to a latch in order of the input scanning.

3. A method claimed in claim 1 in which the image data of the scanning lines are stored into S minus 1 line memories, each of which is composed of P memory units (where P is the number of the sampling cycles in one cycle time of the buffer memory), and the image data of pixels on the present scanning line are brought to P lateches in order of the input scanning.

4. A system for regulating image data of scanning lines of an image reproducing system in which data of plural scanning lines are once stored into a buffer memory and then put into due scanning line order comprising: (a) a means for storing the image data of certain scanning lines to a buffer memory; (b) a means for outputting the image data of the scanning lines from the buffer memory simultaneously; and (c) a means for transferring the image data of each scanning line to the addresses from which the image data of respective previous scanning lines are output.

5. A system claimed in Claim 4 in which the buffer memory comprises S minus 1 line memories (S: the number of the data lines to be regulated) into which the image data of the scanning lines are stored, and a latch to which the image data of pixels of the present scanning line are brought.

6. A system claimed in Claim 4 in which S minus 1 line memories, each of which is composed of P memory units (P: the number of the sampling cycles in one cycle time of the buffer memory) into which the image data of the scanning lines are stored, and P latches to which the image data of pixels on the present scanning line are brought in order of the input scanning.

7. A method of regulating image data of scanning lines of an image reproducing system substantially as hereinbefore described with reference to Figures 6 to 10 of the accompanying drawings.