GB2139029A - Semiconductor device of the type in which a node is precharged in one clock state and selectively discharged in another - Google Patents

Semiconductor device of the type in which a node is precharged in one clock state and selectively discharged in another Download PDF

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Publication number
GB2139029A
GB2139029A GB08403873A GB8403873A GB2139029A GB 2139029 A GB2139029 A GB 2139029A GB 08403873 A GB08403873 A GB 08403873A GB 8403873 A GB8403873 A GB 8403873A GB 2139029 A GB2139029 A GB 2139029A
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United Kingdom
Prior art keywords
mos transistor
precharge
circuit
semiconductor device
node
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Granted
Application number
GB08403873A
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GB2139029B (en
GB8403873D0 (en
Inventor
Hideshi Miyatake
Kazuhiro Shimotori
Kazuyasu Fujishima
Hideyuki Ozaki
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of GB8403873D0 publication Critical patent/GB8403873D0/en
Publication of GB2139029A publication Critical patent/GB2139029A/en
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Publication of GB2139029B publication Critical patent/GB2139029B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01735—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by bootstrapping, i.e. by positive feed-back

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

An MOS transistor semiconductor device of the type in which a node is precharged in one clock state and selectively discharged in another in which circuit delay times are rendered substantially independent of variations in the power supply voltage. First and second MOS transistors are provided to form a leakage path circuit 100, so that the precharge node is charged to a voltage appreciably lower than the supply voltage. The drain of the first MOS transistor 101 is connected to a precharge node NP, while its source is connected to the drain of the second MOS transistor 102. A precharge signal phi P is applied to the gate of the first MOS transistor. The on resistance of the second MOS transistor is preferably about one-third that of the first MOS transistor. In this circuit arrangement, a decrease in the precharge level during the precharge period due, for instance, to a transient in the power supply level, is suppressed so that the ordinary circuit operation is carried out with a constant delay time. <IMAGE>

Description

SPECIFICATION Semiconductor device The present invention relates to a semiconductor circuit, especially a dynamic integrated circuit, which can operate correctly even when its supply voltage changes.
A conventional semiconductor device of this type is shown in Figure 1. This device, which is an example of a dynamic circuit, includes an input circuit which receives an input signal and a precharge signal used to maintain a precharge terminal at a high level at the time of precharging, and a bootstrap circuit which receives the input signal and the signal at the precharge terminal and controls the state of the output signal accordingly. In Figure 1, IN designates the input signal; Xp, the precharge signal; OUT, the output signal; VDD, a supply voltage; and 1 through 4, enhancement-type MOS transistors, these components forming the input circuit.
Further in Figure 1, reference numerals 5, 6 and 7 designate enhancement-type MOS transistors; and 10, a MOS capacitor, these components forming the bootstrap circuit. Furthermore in Figure 1, Np designates a precharge node; and NB, a bootstrap node.
The operation of the dynamic cirucit shown in Figure 1 will be described with reference to Figure 2.
During a precharge period, the precharge signal Xp is at the high level while the input signal IN is at the low level, the precharge node Np is maintained at VDD VT (where VT is the threshold voltage of an enhancement-type MOS transistor), and the output signal is maintained at the high level. When the circuit operation starts, the precharge signal fp falls while the input signal rises. The potential at the precharge terminal is removed using the MOS transistor 4 while the bootstrap terminal NB is charged through the MOS transistor 5. As a result, the capacitor 10 is charged with respect to ground. However, when the potential at the precharge node Np becomes lower than the threshold voltage VT, the MOS transistor 7 is turned off and the potential of the output signal OUT increases.This potential increase performs a so-called "bootstrap action", whereby through the capacive coupling of the capacitor 10, the potential at the bootstrap node increases above VDD + VTH and the output signal OUT is at the level of the supply voltage VDD, In the case when a positive-going transient occurs in the supply occurs in the supply voltage VDD during the precharge period when the circuit operation is being started, the circuit may not operate correctly.
This effect will be described with reference to the waveform diagram of Figure 2.
In Figure 2, the normal level of the supply voltage VDD(L) is indicated by the solid lines. The period of time which elapses from the time instant that the input signal rises after the precharge signal has reached the low level until the output signal reaches VDD(L) is a delay time t1, which is determined by the stray capacitances of the precharge node and the output terminal and by the transistor size of the input circuit and the bootstrap circuit.The waveforms of the signals in the case where the supply voltage momentarily increases to VDD(H) are indicated by dashed lines in Figure 2. (It should be noted that the parts of the waveform lines which overlap the solid lines are not specifically indicated.) As the level of the precharge signal Xp increases, the precharge level of the precharge node Np is increased to VDD(H) - VT from VDD(L) -VT. Thereafter, even when the supply voltage returns to VDD(L) and the level of the precharge signal pp returns to VDD(L), the precharge level of the precharge terminal Np is maintained at VDD(H) - VT. In the subsequent circuit operation, the input signal rises to discharge the level of the precharge node Np and to charge the bootstrap node.However, the level of the precharge node Np goes lower than VT later than in the normal operation. Therefore, the rise of the output signal OUT by the bootstrap circuit is later by t2 than in the normal operation.
Cascaded dynamic circuits of this type are often employed in high-density integrated circuits. Therefore, even if the delay time per circuit stage is short, the final circuit output may have a long delay time because of the accumulation of short delay times.
An object of the incention is thus to eliminate the above-described difficulties accompanying a conventional semiconductor device.
In accordance with the above and other objects, the invention provides a semiconductor device comprising: a first MOS transistor the drain of which is connected to a precharge node which is raised to a high level when an input signal is at a low level while a precharge signal is at a high level, said precharging signal being applied to the gate of said first MOS transistor; a second MOS transistor having a drain connected to the source of said first MOS transistor, a gate connected to a power supply and a source corrected to a ground terminal, the on resistance of said second MOS transistor being higher than the on resistance of said first MOS transistor; and an output circuit having an input connected to the drain of said first MOS transistor.
In the accompanying drawings: Figure 1 is a circuit diagram showing the arrangement of a conventional semiconductor device; Figure 2 is a waveform diagram used for a description of the operations of the circuit in Figure 1 in the case where the supply voltage changes and in the case where the supply voltage is maintained unchanged; Figure 3 is a circuit diagram showing a semicon ductordevice according to one embodiment of the invention; Figure 4 is a waveform diagram used for a description of the operations of the semiconductor device of the invention in Figure 3 in the case where the supply voltage changes and in the case where the supply voltage is maintained unchanged; Figure 5 is an explanatory diagram showing an example of the pattern layout of the circuit of the invention; and Figure 6 and 7 are circuit diagrams showing semiconductor devices according to other embodiments of the invention.
A preferred embodiment of the invention will now be described with reference to Figure 3.
As is apparent from comparing Figure 3 with Figure 1, a semiconductor device according to the invention is constructed by adding a leakage path circuit 100 to the semiconductor device in Figure 1.
The leakage path circuit 100 is composed of enhancement-type MOS transistors 101 and 102. The transistor 101 has a drain a connected to the precharge node Np, a gate to receive the precharge signal, and a source b connected to the drain of the other transistor 102. The transistor 102 has a gate connected to the power source VDD, and a source c grounded. The series "on" resistance of the MOS transistors 101 and 102, which forms the leakage resistance, is three times as high as the "on" resistance of the MOS transistor 3, which forms the drive resistance of the precharge circuit.
The operation of the semiconductor device thus constructed will be described with reference to Figure 4.
In Figure 4, the solid lines indicate the waveforms in the case where the supply voltage is constant at VDD(L), while the dashed lines indicate the waveforms in the case where the supply voltage rises to VDD(H) from VDD(L) and then falls to VDD(L) during the precharge period. (It should be noted that the broken lines partially overlap the solid lines in these waveforms.) In the normal operation of the circuit of Figure 3 where the supply voltage is constant at VDD(L), during the precharge period, the MOS transistor 101 conducts and a leakage path is formed by the MOS transistors 101 and 102. Therefore, the level of the precharge node is VDD(L) - VT V1, which is lower than VDD(L) - VT.Even when the precharge signal Xp reaches the low level thereafter and the MOS transistor 3 is therefore turned off, because the MOS transistor 101 is turned off, the precharge level is not removed through the leakage path before the input signal rises. Therefore, the provision of the leakage path will not cause erroneous operation. However, as the precharge level is lower by Via, the time interval which elapsed from the time instant that the input signal IN rises until the output signal reaches VDD(L) is t, which is shorter than t1 in the case of Figure 1.
If the precharge level falls below VT during the precharge period, the MOS transistor 7 is turned off before the input signal IN is applied, and the circuit will operate erroneously. However, if the series "on' resistance of the MOS transistors 101 and 102, which is the leakage resistance of the leakage path circuit, is made three times as high as the "on" resistance of the MOS transistor 3 which acts as the precharge drive resistor, the decrease (AV) of the precharge level is small, and the time interval which elapses from the time instant that the input signal IN rises until the output signal OUT reaches VDD(L) will be substantially equal to t. If the leakage resistance is further increased, then increase of the supply current due to the provision of the leakage path circuit will be more adequately suppressed.
In the case where the supply voltage undergoes a positive transient during the precharge period, the MOS transistor 101 conducts during the precharge period and a leakage path is formed by the MOS transistors 101 and 102. Therefore, if the supply voltage increases so that the precharge level is increased to VDD(H) - VT - AV2 (#VDD(H) -VT), and then falls back, due to the presence of the leakage path, the precharge level will fall to VDD(L) - VT - AV1 corresponding to that voltage. Thereafter, the time interval which elapses from the time instant that the input signal IN rises until the potential of the output signal OUT reaches VDD is t3. This is equivalent to the case where the voltage remains unchanged.
In the above-described embodiment, the gate voltage of the MOS transistor 102 is the supply voltage. However, instead of the supply voltage, a predetermined voltage capable of rendering the MOS transistor 102 conductive may be employed with the same effect.
In general, a dynamic circuit is implemented with enhancement-type MOS transistors. Therefore, a leakage path circuit composed of enhancement-type MOS transistors can be readily provided in the process of forming an integrated circuit.
In the above-described embodiment, the dimensions of the MOS transistors 101 and 102 are not particularly specified. However, the gate length and width of the MOS transistor 101 may be several microns and the high leakage resistance of the leakage path circuit may be obtained by forming the gate of the MOS transistor 102 in a zig-zag pattern. In this case, the effect is similar to that in the abovedescribed embodiment, and the load capacity of the precharge signal Xp is minimized, which is advantageous for high density integration.
In the above-described embodiment, the source region a of the MOS transistor 101 may, as shown in Figure 5, have a width of several microns extending near the VDD line and the ground line with the MOS transistor 102 being arranged over the VDD line and the ground line. In this case also the effect of the leakage path circuit is the same as that in the above-described embodiment because, when the input signal rises, the precharge signal #p is at the low level, and therefore the stray capacitance of the source region a of the MOS transistor 101 does not act as a stray capacitance of the precharge node Np and will not cause a delay in the circuit operation.
Furthermore, in this case, the leakage path circuit can be arranged in a vacant region in the pattern layout, which contributed to a high integration density.
In the above-described embodiment, the leakage path circuit is applied to a dynamic circuit including an input circuit which receives the input signal and a precharge signal used to maintain the precharge node at the high level at the time of precharge, and also a bootstrap circuit which receives the input signal and the signal at the precharge node to perform on-off control of the output signal. However, the same effect can be obtained by applying the leakage path circuit of the invention to a dynamic circuit which, as shown in Figure 6, includes an input circuit for receiving the output signal and the precharge signal to maintain the precharge node at the high level at the time of precharge, and a bootstrap circuit for receiving the input signal and the signal at the precharge node to perform on-off control of the output signal.Alternatively, the leakage path circuit may be applied to a dynamic circuit as shown in Figure 7 which receives the input signal and the precharge signal and outputs an inverted input signal.
The operation of the circuit in Figure 6 will be described. In Figure 6, reference numerals 1 and 2 designate enhancement-type MOS transistors forming forming the input circuit; 3 through 7, enhancement-type MOS transistors; 10, an MOS capcitance, with the circuit elements 3 through 7 and 10 forming the bootstrap circuit; and 100, the leakage path circuit. The remaining reference characters are the same as those in Figure 1.
During the precharge period, the precharge signal Xp is at the high level while the input signal IN is at the low level and the precharge node Np is maintained at VDD VT while the output signal OUT is maintained at the low level. When the circuit starts its operation, the precharge signal p falls while the input signal IN rises so that the MOS capacitor 10 is charged with respect to ground. As a result, the output signal starts rising and the voltage at the precharge node Np is removed through the MOS transistor 2 in the input circuit.When the potential at the precharge node Np becomes lowerthab VT, and accordingly the MOS transistor is turned off, the potential at the bootstrap terminal NB becomes higher than VDD + VT due to the capacitive coupling of the capacitor 10, as a result of which the output signal is at the potential VDD If the leakage path circuit were not provided, when the supply voltage increases to VDD(H) and then decreases to VDD(L) during the precharge period, the precharge node Np would be maintained at the high potential VDD(H) - VT. Thereafter, when the input signal IN rises and the circuit starts the operation, the potential at the precharge node Np would become lower than VT with a time delay.Therefore, the time interval which elapses from the time instant that the input signal IN rises until the output signal reaches the level VDD(L) is longer than that in the case where the supply voltage is maintained constant.
On the other hand, when the leakage path circuit is used, the ordinary circuit operation is carried out smoothly, and even if the supply voltage varies, the high potential VDD(H) - VT at the precharge node Np is removed through the leakage path circuit, being changed to VDD(L) - VT. Therefore, the time interval which elapses from the time instant that the input signal IN rises until the output signal OUT reaches the level VDD(L) is not excessively long, and is about equal to that in the case where the supply voltage does not change.
The circuit in Figure 7 will now be described. In Figure 7, reference numerals 1 and 2 designate enhancement-tpe MOS transistors; and 100, a leakage path circuit. In this case, the precharge node Np serves as the output terminal. The other reference characters are the same as those in Figure 1. During the precharge period, the precharge signal is at the high level while the input signal is at the low level, and the precharge node Np is maintained at VDD - VT.
As the circuit starts its operation, the precharge signal up falls while the input signal IN rises.
Therefore, the level of the precharge node Np, namely, the level of the output terminal, decreases so that an inverted output signal is provided.
If the leakage path circuit were not provided, when the supply voltage increases to VDD(H) and then decreses to VDD(L) during the precharge period, the high potential VDD(H) - VT would be held at the output terminal. Therefore, the time interval which elapses from the time instant that the input signal IN rises until the level at the output terminal falls below VT is longer than that in the case where the supply voltage is maintained unchanged. On the other hand, when the leakage path circuit is used, the ordinary circuit operation is carried out smoothly, and even when the supply voltage changes, the high potential VDD(H) - VT is discharged through the leakage path circuit as before.Therefore, the time interval which elapses from the time instant that the light input signal IN rises until the level of the output terminal falls below VT is again about the same as the case where the supply voltage is maintained constant.
As is apparent from the above description, in the semiconductor device according to the invention, first and second MOS transistors form a leakage path circuit. The drain of the first MOS transistor is connected to the precharge node while the source is connected to the drain of the second MOS transistor.
The precharge signal is applied to the gate of the first MOS transistor. The on resistance of the second MOS transistor is lower than that of the first MOS transistor. Therefore, any decrease of the precharge level during the precharge period due to erroneous operation of the circuit and increase of the supply current due to the provision of the leakage path circuit are suppressed so that the ordinary circuit operation is carried out smoothly. Furthermore, even when the supply voltage undergoes a transient during the precharge period, the precharge level follows the variation of the supply voltage. Accordingly, the circuit operation is correctly carried out without excessive delay.

Claims (6)

1. A semiconductor device, comprising: a first MOS transistor the drain of which is connected to a precharge node which is raised to a high level when an input signal is at a low level while a precharge signal is at high level, said precharging signal being applied to the gate of said first MOS transistor; a second MOS transistor having a drain connected to the source of said first MOS transistor, a gate connected to a power supply and a source corrected to a ground terminal, the on resistance of said second MOS transistor being higher than the on resistance of said first MOS transistor; and an output circuit having an input connected to the drain of said first MOS transistor.
2. The semiconductor device as claimed in claim 1, wherein the gate of said second MOS transistor has a zigzag form.
3. The semiconductor device as claimed in claim 1, wherein said output circuit comprises bootstap circuit means receiving said input signal and said precharge signal for performing on-off control of an output signal.
4. The semiconducor device as claimed in claim 1, wherein the source region of said first MOS transistor includes a line several microns in width extending near at least one of a power source line and a ground line.
5. The semiconductor device as claimed in claim 1,wherein said on resistance of said second MOS transistor is approximately three times said on resistance of said first MOS transistor.
6. The semiconductor device as claimed in claim 1, wherein said second MOS transistor is formed above a power source line.
GB08403873A 1983-02-16 1984-02-14 Semiconductor device of the type in which a node is precharged in one clock state and selectively discharged in another. Expired GB2139029B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58025596A JPS59149427A (en) 1983-02-16 1983-02-16 Semiconductor device

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GB8403873D0 GB8403873D0 (en) 1984-03-21
GB2139029A true GB2139029A (en) 1984-10-31
GB2139029B GB2139029B (en) 1987-03-04

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GB08403873A Expired GB2139029B (en) 1983-02-16 1984-02-14 Semiconductor device of the type in which a node is precharged in one clock state and selectively discharged in another.

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DE (1) DE3405600C2 (en)
GB (1) GB2139029B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920015363A (en) * 1991-01-22 1992-08-26 김광호 TTL input buffer circuit
DE19801887A1 (en) * 1998-01-20 1999-07-22 Mannesmann Vdo Ag Integrated circuit with at least one digital part

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL299911A (en) * 1951-08-02
US3714466A (en) * 1971-12-22 1973-01-30 North American Rockwell Clamp circuit for bootstrap field effect transistor
US3988617A (en) * 1974-12-23 1976-10-26 International Business Machines Corporation Field effect transistor bias circuit
US4016434A (en) * 1975-09-04 1977-04-05 International Business Machines Corporation Load gate compensator circuit
JPS5772429A (en) * 1980-10-22 1982-05-06 Toshiba Corp Semiconductor integrated circuit device

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DE3405600A1 (en) 1984-08-16
GB2139029B (en) 1987-03-04
JPS59149427A (en) 1984-08-27
DE3405600C2 (en) 1987-04-16
GB8403873D0 (en) 1984-03-21

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Effective date: 19951108

PCNP Patent ceased through non-payment of renewal fee

Effective date: 19970214