GB2132843A - Semiconductor memory - Google Patents

Abstract

The NOR decoders of a static random access memory are divided into two or more sets 23,24 only one of which is powered up at any one time. This significantly reduces the power dissipation of the memory and allows the device to be operational under high access speed conditions. <IMAGE>

Description

SPECIFICATION Semiconductor memory This invention relates to semiconductor memories, and in particular to random access memories of the static type.

In such a memory, the memory cells are arranged in a two-dimensional array of m rows and n columns. This array may be physically divided into 2 or more sub-arrays for layout or operating reasons.

A cell is accessed by means of X-decoders and Y-decoders which connect the cell to the input/ output circuitry. Thus there are m X-decoders and n Y-decoders.

It is a requirement of a static random access memory that the access time of any particular cell shall be as short as possible to ensure a high speed of operation. One of the limiting factors on operating speed is the particular construction and operation conditions of the decoder circuitry whereby individual cells of the memory array are accessed. In general the speed of operation of such a circuit is related to the quiescent current passed by the circuit.

An increase in this current corresponds to an increase in speed.

The disadvantage of this high speed operation is of course the excessive power drain that is experienced with the large decoder array required for a large memory. In such a situation this power requirement may prove a limitation on the access time of the memory.

The object of the present invention is to minimise or to overcome this disadvantage.

According to the invention there is provided a static random access memory, including sets of memory cells, said memory cells being divided logically into two or more sets, row-decoder sets one for each memory cell set whereby the cells of that set can be accessed, and means whereby, when a memory cell is accessed, power is supplied only to that one of the decoder sets corresponding to the accessed cell.

Since only a portion of the total decoder circuitry is powered up at any one time the constraints on power dissipation are considerably released without impairment to the operating speed of the memory.

Typically the memory cells are laid out in two similar arrays, but in some applications a larger number of subdivisions may be employed.

Typically the memory is fabricated by a high speed density n-channel HMOS process.

An embodiment of the invention will now be described with reference to the accompanying drawings in which: Figure 1 is a schematic diagram of the memory layout; and Figures 2 and 3 show the decoder circuitry employed in the memory of Figure 1.

Referring to Figure 1, the memory, which comprises a static random access memory, includes two similar arrays of memory cells 11 having a columnar array of X-decoders 12 disposed therebetween. Two similar sets of Y-decoders 13 are disposed at the one end of the cell arrays 11. An individual memory cell 11a is accessed by providing the decoders 12 and 13 with the corresponding X and Y address via Xaddress and Y-address buffers 14 and 15 respectively. Note that Figure 1 shows the physical rather than the electrical layout of the memory.

Typically, the memory is a 16K word by one bit memory with the memory cells physically arranged in two 128 by 64 arrays. Thus each array (11) has 128 X-decoders in the X-decoder array (12) and 64 Y-decoders in each of the Y-decoder arrays (13). This physical arrangement is the result of layout considerations. Electrically the array is not split in the Y direction.

Figures 2 and 3 illustrate the operation of the X-decoder circuits. To access a particular row of the memory an X-address in the form of a seven bit binary code is fed to the X-address decoders which comprise two sets of 64 seven input NOR gates, one set being used for each memory array. The address inputs are shown schematically as lo to 16 in Figure 2.

Six of these inputs receive row address information, i.e. bits Ao to A5, whilst the seventh, e.g. Is, receives a decoder select bit Ax. Since there are, in the present case, a total of 128, i.e. 27, rows of cells a seven bit binary signal contains sufficient information to define a particular row. Simultaneously with the Xaddress code a similar Y-address code is fed to the Y-decoders thereby defining the particular cell that is to be accessed.

The X-decoders are logically divided into two sub-sets (23,24) using the X-address (Ax) as the controlling bit. Selection of one or other of the memory arrays is effected via a pair of two input NOR gates 31,32 (Figure 3). When a memory row is accessed a corresponding logic signal Ax is applied to one input of one gate and its complement A, is applied to one input of the other NOR gate. The other inputs of the NOR gates are coupled together and receive an enable signal CE, normally generated 'on chip', whereby power up and power down of the decoders is effected. The memory is held in a low power mode whilst the CE signal is high and reverts the normal operation when the CE signal is low.

Thus an X-decoder array can be activated only during the period when the CE signal is in its low state. Under such conditions a high A, signal applied e.g. to the gate 31, and a corresponding low Ax signal applied to the gate 32 causes generation of low decoder disable signal DE2 at the output of gate 32 and a high decoder enable signal DE1 at the output of gate 31. DE1 and DE2 are used to power up X-decodersub-sets 1 and 2 respectively. If a Decoder Enable signal is high then the corresponding Xdecoder sub-set is powered up. If DE is low then the corresponding X-decoder sub-set reverts to a low power standby mode. In operation, if CE is high then both DEl and DE2 are constrained to be low and the X-decoders are powered down with the rest of the memory.If CE is low then the rest of the memory is powered up for normal operation. Under such conditions, e.g. a high Ax signal and a corresponding low Ax signal will result in the generation of a high DE1 signal and a low DE2 signal. Thus, for example, X-decoder sub-set 1 is powered up whilst sub-set 2 remains in low power standby. In this way only one of the decoder arrays corresponding to the required memory cell can be activated at any one time, and the decoder power requirements are thus effectively halved.

In a particularly advantageous arrangement the two arrays of X decoders are interleaved on the memory chip. This distributes the power dissipation and also minimises the effect of 'crosstalk' between adjacent decoders. It will of course be apparent to those skilled in the art that the physical division of the cells into two arrays does not correspond to their logical division into two or more sets of cells. It will also be clearly understood that although the arrangement is described with reference to the X-decoders where the greatest speed increase may be achieved it may also be applied to the Ydecoders.

Whilst the foregoing description refers to a memory with two arrays of cel Is it will be clear that the principles of operation described herein can be applied to memories with more than two cell arrays.

Typically the memories described herein will be used in computer and calculator applications where speed of access if a primary constraint on the memory design.

Claims (8)

1. A static random access memory, including sets of memory cells, said memory cells being divided logically into two of more sets, row-decoder sets one for each memory cell set whereby the cells of that set can be accessed, and means whereby, when a memory cell is accessed, power is supplied only to that one of the decoder sets corresponding to the accessed cell.

2. A memory as claimed in claim 1, wherein said decoder power supply means includes two-input NOR gates one for each memory cell set and to the inputs of which, in use, a power signal and an array select signal are fed.

3. A memory as claimed in claim 1 or 2, wherein said memory cells are disposed in first and second arrays with the row decoders arranged in a columnar array therebetween.

4. A memory as claimed in claim 3, wherein the individual decoders of the first and second sets are arranged alternatively in said columnar array.

5. A memory as claimed in any one of claims 1 to 4, and which is fabricated by an n-channel HMOS process.

6. A semiconductor memory substantially as described herein with reference to the accompanying drawings.

7. A computer of calculator incorporalting one or more memories are claimed in any one of claims 1 to 6.

8. A method of operating a static random access memory, which method is substantially as described herein with reference to the accompanying drawings.