GB2128386A - Apparatus for entering characters into a data processing system - Google Patents

Abstract

To enable a disabled person to enter characters into a microcomputer 22, input circuitry 45, which has one or more switches adapted to be operated by the user, is coupled to the data bus 36 of a central processor unit 29, operating in accordance with a program stored in a ROM 34, which controls a visual display 19 and a computer interface 44 in dependence upon input signals from the input circuitry 45. The user selects a computer character in the display 19 and the interface 44 gates the interrogating signals generated by the computer 22 for its own keyboard (which is not present) and thereby simulates at the sense lines 23 to the computer 22 the desired character code. A character can be entered by the combination of two switch operations in series. By selecting tape control regions of the display 19, the user can cause the CPU 29 to control relay circuits in tape control circuitry 46 which control rewind, play and record operations of a tape recorder 18 used as a serial data store. A reset region of the display 19 can be selected to cause a reset signal to be applied to the computer 22. An alternative embodiment has a keyboard unit instead of the display 19. <IMAGE>

Description

SPECIFICATION Apparatus for entering characters into a data processing system This invention relates to apparatus for entering characters into a data processing system, and especially, but not exclusively, to apparatus for entering characters into a microcomputer.

Microprocessor-based computers, known as microcomputers, are now popular and offer the user a means of familiarising himself with highlevel programming languages such as BASIC, and with the possibilities for problem solving and game playing which these computers have.

The input peripheral device usually included with a microcomputer is a keyboard. Such keyboards are frequently even more compact than a typewriter keyboard, and may require the user to operate two keys simultaneously for some purposes. These features, while acceptable to most users, constitute disadvantages or obstacles serious enough to render the microcomputer unusable by a group of potential users, namely disabled person whose disability prevents them from controlling such keyboards. It is therefore a primary object of the present invention to provide an apparatus for entering characters into a data processing system which apparatus has features which facilitate its use by disabled persons.

According to the present invention there is provided apparatus for entering characters into a data processing system, the apparatus comprising a first plurality of character indicators which can be selectively activated serially by a user, means for generating in response to activation of each indicator a respective first signal code, a memory storing a second plurality of mutually distinguishable second signal codes, means for retrieving from the memory a predetermined respective one of the mutually distinguishable second signal codes in response to generation of each of at least some of the first signal codes when generation of the respective first signal code is maintained for a predetermined time interval, and means for presenting an input determined at least partly by a retrieved second signal code to a data processing system.

In a preferred embodiment, the apparatus includes a significance modifier which can be selectively activated serially amongst the character indicators. Some of the character indicators have plural significance and the significance modifier can be activated before such a character indicator in order to alter its significance from that prevailing when the significance modifier has not been activated. The serial nature of this modifying action dispenses with the need for a user to operate two input members simultaneously which arises with the shift key arrangements in microcomputers.

In an embodiment of the invention, the duration of the said predetermined time interval can be long enough to ensure that a character indicator has been deliberately activated by a disabled user. Preferably this predetermined time interval is made adjustable to suit the needs of the particular user.

For severely physically disabled persons, the invention can be embodied in a visual display unit having a display area divided into regions, preferably panels, corresponding to the keys of keyboard input device which would normally be used with the data processing system but which is dispensed with for the present invention. Thus the display presents an array of character indicators. The display is preferably controlled by a one or two switch input switch device adapted to be operable by the user by, for example, being in the form of a breath-pressure activated unit or a pivoted plate switch unit.

For users who can operate depressable keys if large enough and widely spaced, the invention can be embodied in a keyboard unit having large, widely spaced keys and a number of indicator lights to help the user to be aware of the operating condition of the unit.

A feature of many microcomputers is the ability to use a tape recorder as a serial data store.

Accordingly, a preferred embodiment of the invention includes a number of special function indicators which can be selectively activated by a user, these indicators being associated with data store control functions, for example rewind, play and record, and possibly other special functions such as a system reset for the data processing system when coupled to the embodiment.

To inform the user of the activity of the apparatus when embodied in a keyboard unit, indicator lights are preferably provided to indicate such states as:- 1. A character indicator is activated but the predetermined time interval has not expired.

2. A character indicator is activated and the predetermined time interval has expired.

3. A significance modifier is operating.

4. Special function indicators controlling the operation of a serial data store such as a tape recorder are operating.

5. A reset indicator is operating which resets the data processing system.

Preferred features of the present invention are described in general terms in the dependent claims hereinafter.

The invention will now be described in more detail, solely by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a schematic perspective view of a data processing system with apparatus embodying the invention, Fig. 2 is a block diagram of a microcomputer coupled to apparatus embodying the invention and forming part of the system of Fig. 1; Fig. 3 is a simplified plan view of an indicator display overlay for the embodiment of Fig. 2; Fig. 4 is a more detailed block diagram of the apparatus of Fig. 2; Figs. 5 to 14 are circuit diagrams of parts of the apparatus of Fig. 4; Fig. 1 5 is a simplified perspective view of an expanded keyboard unit embodying the invention;; Fig. 1 6 is a partial circuit diagram of an input switch and diode matrix incorporated in the expanded keyboard unit of Fig. 15; Fig. 1 7 is a partial block diagram illustrating a modification of Fig. 4 for the embodiment of Fig.

1 5; and Figs. 1 8 to 67 are flow chart diagrams illustrating a program for the embodiments of Figs. 1 to 17.

In Fig. 1 there is shown a combined computer and LED matrix display unit 10 to which two input switches 11 and 12 are connected by a cable. A coaxial cable 1 3 couples a computer television display output of the unit 10 to the aerial socket of a colour television receiver 14. Record, play and control leads 15, 16 and 17 couple the unit 10 to a solenoid controlled cassette tape recorder 18.

The unit 10 contains a ZX Spectrum computer, which is produced by Sinclair Research Limited, of Stanhope Road, Camberley, Surrey, GU15 3PS, England, from which the keyboard and the associated key switches have been removed. The LED matrix display 19 of the unit 10 has an overlay divided graphically into fifty rectangular panels arranged in five rows of ten panels as illustrated by Fig. 3. The first four rows, starting with the bottom row, are arranged to resemble the forty keys of a ZX Spectrum keyboard, and each of the forty panels is used to indicate the same group of characters or instructions as the corresponding ZX Spectrum key, as illustrated partially in Fig. 3.The panels of the top row are for indicating a reference or starting position, HOME SQUARE, and a number of control functions of the unit 10 which do not directly involve the entering of data into the computer, namely control of the tape recorder 1 8 by rewind, play and record instructions to the recorder 18, and resetting of the computer.

Fig. 2 illustrates diagrammatically the equipment within the unit 10 and its connections to the tape recorder 1 8 and the input switches 11 and 12 and an alternative set of input switches 20.

The equipment includes simulator/interface circuitry 21 which controls the display 19 and the tape recorder 18 and supplies character codes to the computer 22 over sense lines 23. The simulator/interface circuitry 21 operates in response to the use of the input switches 11 and 12 or 20. When the set of eight input switches 20 is used instead of the two switches 1 ; and 12, the switches 11 and 1 2 and the cable connecting them to the unit 10 are replaced by an eight switch device, for example an eight-way joystick device, and its cable.Other input switch devices may be used to suit the abiiity of the particular user, suitable switch devices being, for example, those supplied by Possum Controls Limited as user input devices for environment control systems and communication systems.

In use, the input switch device can be operated to cause any one, and some combinations, of the panels of the display 19 to be illuminated by the respective LED or LEDs (light emitting diodes), and the unit 10 carries out operations associated with the user selected LED or LEDs. Selections of any one of the thirty-eight character key panels of the display 19, i.e. any one of the panels of the first four rows, except the CAPS SHIFT and SYMBOL SHIFT panels, causes entry of a ZX Spectrum character code to be entered into the computer 22 in accordance with the same rules as apply in the case of entry of a character by the depression of the corresponding ZX Spectrum key.Selection of the CAPS SHIFT panel causes the simulator/interface circuitry 21 to store a CAPS SHIFT code which is entered into the computer 22 at the entry of the next selected character that is not SYMBOL SHIFT, and is then cleared. In the same way, selection of the SYMBOL SHIFT causes the circuitry 21 to store a SYMBOL SHIFT code which is not CAPS SHIFT, and is then cleared. If CAPS SHIFT and SYMBOL SHIFT are selected, one immediately after the other in whichever order, a combined CAPS SHIFT and SYMBOL SHIFT code is entered into the computer 22 as soon as the selection of the second of the two SHIFT panels has been accepted by the circuitry 21, and the stored shift codes cleared.Thus the simulator/interface circuitry 21 converts serial entry operations, by the user, of shift commands into parallel entries into the computer 22, as required when the computer 22 is equipped with a ZX Spectrum keyboard and the associated key switches.

Consequently the unit 10 can be operated as described in the introductory booklet and the BASIC programming manual which are supplied by Sinclair Research Limited with each ZX Spectrum computer, except that it is not necessary for the CAPS SHIFT panel or the SYMBOL SHIFT panel to be selected simultaneously with the other panel whose code is to be modified by combination with the selected shift code.

It will be seen from Fig. 2 that the record and play leads 1 5 and 16 of the tape recorder 18 are connected to the computer 22. The record lead 1 5 connects the microphone input socket of the recorder 18 to a socket marked MIC on the ZX Spectrum computer 22. The play lead 1 6 connects the earphone output socket of the recorder 1 8 to a socket marked EAR on the computer 22. Thus the data input and data output connections between the computer 22 and the recorder 1 8 are as described in Chapter 6 of the ZX Spectrum introductory booklet by Steven Vickers and Robin Bradbeer, First Edition 1982, published by Sinclair Research Limited.

The tape recorder 1 8 is, in the present example a Sanyo TRC 8000Z, in which there are a rewind solenoid, a play solenoid and a record solenoid. To effect rewind, the rewind solenoid is energised. To effect play, the play solenoid is energised, and to effect record, both the record and play solenoids are energised.Energisation of these solenoids (not shown) is controlled by three respective switches within the circuitry 21, power being supplied in operation to the recorder 1 8 from a domestic a.c. power supply through a separate power lead (not shown) to the recorder 1 8. Power for the unit 10 is also supplied in operation from a domestic a.c. power supply through another separate power lead (not shown), the unit 10 including a supply circuit (not shown) which produces suitable low d.c. voltages such as +5 volts and +9 volts.

The cable 13 connects the computer 22 to the television receiver 14 in the same way as described for the ZX Spectrum in the introductory booklet referred to hereinbefore.

Thus the combination of an input switch device, for example the switches 11 and 12 in their common housing, and the unit 10 takes the place of a ZX Spectrum computer equipped with its keyboard.

Within the computer 22 there is a microprocessor (not shown), which in the case of the ZX Spectrum is a Zilog Z80 microprocessor, which has a reset terminal that, in operation, is normally held at a high signal level by a resistor (not shown). This reset terminal is also coupled to ground by a capacitor (not shown) so that on switching on the computer 20, its microprocessor is automatically reset. This reset circuitry (not shown) of the computer 22 is modified to allow resetting of the computer 22 by operation of the input switch device to select the RESET panel of the display 1 9 followed by operation to select the ENTER panel.The effect of these operations is to establish a reset signal on a reset line 24, which connects the display 1 9 to the reset terminal of the computer 22, by closure of a switch within the display 1 9. The selection of the ENTER panel immediately after the RESET panel does not result in the entry of the ENTER code into the computer 22, but is used in the circuitry 21 to establish the validity of the RESET command. Thus accidental selection of RESET does not affect the computer 22. It is furthermore arranged that selection of any panel other than ENTER after RESET results in cancellation of the sequence of control operations initiated by the selection of RESET.

To facilitate the use of the unit 10 by a disabled user, the circuitry 21 requires a selection operation at the input switch device by the user to be maintained for a suitable period of time before the selection is accepted. Thus accidental selections can be cancelled by abandonment of the selection operation before the expiry of a period referred to hereinafter as the actuate delay.

The actuate delay is an adjustable time set by a potentiometer with a manually operable control knob 25 on the unit 10.

Where a two switch input device is used with the unit 10 as in Fig. 1, the circuitry 21 operates the display 19 in one of a number of scanning modes in which the LED of the home square is initially energised and any other panel is selected by the user controlling a scanning process in which the LEDs of successive panels are energised until the chosen panel is reached. In controlling these scanning processes, the user is required only to initiate and stop successive energisation, usually in columns and rows of panels. To enable such control, the energisation of each LED is maintained for a period of time referred to hereinafter as the scan delay. The scan delay is an adjustable time set by another potentiometer with a manually operable control knob 26 on the unit 10.

Several different modes of scanning are possible with the unit 10, when used with a two switch input device, and other panel selection modes are possible with input devices having eight or more switches. To set the circuitry 21 in a condition to carry out appropriate panel selection operations in response to different modes of user operation depending on user preference and/or the nature of the input switch device a mode selection switch with a manually operable control knob 27 is provided in the unit 10.

The Spectrum keyboard, which is not used in the present invention, of a ZX Spectrum computer controls a cross-point matrix of switches, each key of the Spectrum keyboard being depressable to close a respective one of the forty switches of the cross-point matrix. To generate character codes and, shift signals for modifying the character codes, from user operation of the Spectrum keyboard, a ZX spectrum computer generates patterns of interrogating signals on a set of eight strobe terminals which are connected respectively to eight "row" conductors of the cross-point matrix, and senses the resultant output of the keyboard at five sense terminals which are connected respectively to five "column" conductors of the cross-point matrix.

Each of the forty switches of the cross-point matrix is arranged at a respective crossing point between a "row" conductor and a "column" conductor so that the sense terminals, each of which is coupled by a resistor to a "high" signal level, can be pulled to a "low" signal level if keys are depressed and the interrogating signals provide low signal levels. Different character codes can therefore be applied to the sense terminals in the form of five parallel bits one or more of which may be low and the others high.

The simulator/interface circuitry 21 simulates operation of a Spectrum keyboard by receiving the interrogating signals over a set of eight strobe lines 28, and selecting the required signals to be allowed to reach the sense lines 23, which are a set of five lines connected respectively to the five sense terminals of the computer 22. The computer 22 produces a low signal on only on strobe terminal at any particular time, thereby restricting the group of keys which would be interrogated to five each of which would be connected to a respective one of the sense terminals. Therefore to simulate depression of, for example, the A key, the circuitry 21 selects the low signal on the strobe line of the strobe terminal which would be connected to the A key switch and couples this signal to the sense line of the sense terminal which would be connected to the A key switch.It is found that this coupling must be maintained for a minimum time and this time is referred to hereinafter as the keystroke time.

The simulator/interface circuitry 21 is shown in block diagram form in Fig. 4, which also shows the computer 22 connected to units of the circuitry 21.

The circuitry 21 includes a central processor unit 29 which receives a system clock signal at an input terminal 30 from a clock generator comprising a crystal oscillator 31 driving a divideby-two circuit 32 coupled through an inverter 33.

The processor unit 29 operates in accordance with a program stored in an erasable programmable read only memory (EPROM) 34 to which it is coupled by an address bus 35 and a data bus 36. Temporary storage is provided, as required by the program, by a random access memory (RAM) 37 connected to the two buses 35 and 36.

The program includes an interrupt routine which is run at regular intervals, each run of the interrupt routine being triggered by an interrupt signal supplied to the processor unit 29 by an interrupt generator 38 driven by the crystal oscillator 31 through the divide-by-two circuit 32 and a scaling counter 39.

In operation, the processor unit 29 issues control signals over control lines 40 to a control logic unit 41 which gates these signals and an address line signal from the address bus 35 to produce further control signals to be applied to the EPROM 34, the RAM 37 and an input/output decoder 42 which also receives two address line signals from the address bus 35.

The input/output decoder 42 produces enabling signals for respective data input or output parts of a scan and actuate delays and scan mode selection circuitry 43, the display 19, a computer interface unit 44, user input circuitry 45 and tape recorder control circuitry and audio tone output control circuitry 46. An interrupt reset signal is also produced by the input/output decoder 42 at the beginning of each run of the interrupt routine and is supplied to the interrupt generator 38 to reset its output. The scan and actuate delays and scan mode selection circuitry 43 includes the potentiometers which can be adjusted by means of the control knobs 26 and 25, and the mode selection switch with the control knob 27.The tape control circuitry and audio tone output control circuitry 46 includes relays whose controlled switching contacts are connected to the control solenoids of the tape recorder 1 8 by the control lead 1 7 (which is not shown in Fig. 4), and means for generating an audio tone at a frequency determined by the rate at which the interrupt routine occurs.

The input circuitry 45 includes the user's input switch device which is arranged to supply signals to one or more of the lines of the data bus 36 depending upon how many switches of the device are used. Thus one or two or eight signals may be supplied, for example.

The computer interface unit 44 effects the controlled coupling of the strobe lines 28 to the sense lines 23 required to simulate character codes to be entered into the computer 22. An example of the computer interface unit 44 as shown in Fig. 5 in which the eight lines DO to D7 of an eight line data bus 36 are connected to the data input pins of an input port 47 in the form of octal D flip-flop circuit, type 74C374. A port enabling signal IW2 from the input/output decoder 42 is supplied to pin 11 of the port 47 whenever data is to be latched into the port.

Signals at the output pins of the port 47 are supplied through buffers to two switching unit 48 and 49 and two shift signal switches 50 and 51, the output pins 1 5, 12 and 9 being connected respectively to input pins 9, 10 and 11 of the unit 48, pins 6, 5 and 2 to input pins 9, 10 and 11 of the unit 49, and the pins 19 to 16 to respective control terminals of the switches 50 and 51. Each of the unit 48 and 49 is an 8-way multiplexing analog switch, type 4051. The eight output pins of the unit 48 are respectively connected to the eight strobe terminals ZXA8 to ZX1 5 of the computer 22, and five output pins, 13, 14, 1 5, 12 and 1, of the unit 49 are connected to the five sense terminals ZXDO to ZXD4 of the computer 22.In a ZX Spectrum keyboard cross-point matrix, the CAPS SHIFT key switch couples the ZXA8 strobe terminal to the ZXDO sense terminal.

Accordingly, the switch 50 is arranged to couple these two terminals. Similarly, to replace the SYMBOL SHIFT key switch, the switch 51 couples the strobe terminal ZXA1 5 to the sense terminal ZXD1.

In accordance with signals presented at their input pins 9, 10 and 11, the units 48 and 49 can selectively establish connection between any one of the sense terminals ZXDO to ZXD4 and any one of the strobe terminals ZXA8 to ZXA15 by way of a diode 52 coupling their respective pins 3, the interrogating signals from the computer 22 being low active. Diodes are provided for the switches 50 and 51 also, which are individual switches of a quad analog switch, type 4066.

The Spectrum computer 22 interprets the signals at the sense terminals ZXDO to ZXD4 as follows: 1) When ZXA8 is low: ZXDO low represents CAPS SHIFT key depressed; ZXD 1 low represents Z key depressed; ZXD2 low represents X key depressed; ZXD3 low represents C key depressed; ZXD4 low represents V key depressed.

2) When ZXA9 is low: ZXDO < A, i.e. ZXDO low represents A key depressed: ZXD1oS; ZXD2oD; ZXD3oF; ZXD4oG.

3) When ZXA10 is low: ZXDO < Q; ZXD 1 oW; ZXD2eE; ZXD3eR; ZXD4oT.

4) When ZXA11 is low: ZXDO-11; ZXD1e2; ZXD2o3; ZXD3o4; ZXD4e5.

5) When ZXA12 is low: ZXDOo; ZXD19; ZXD2e8; ZXD3 < 7; ZXD.4o6.

6) When ZXA13 is low: ZXDOoP; ZXD 1 o0: ZXD2e1; ZXD3oU; ZX DY.

(7) When ZXA14 is low: ZXDOoENTER; ZXD1L; ZXD2oK; ZXD3oJ; ZXD4sH.

8) When ZXA15 is low: ZXDOoSPACE; ZXD1oSYMBOL SHIFT; ZXD2oM; ZXD3oN; ZXD4oB.

To enter CAPS SHIFT and SYMBOL SHIFT simultaneously into the computer 22, in order to establish the extended mode of the ZX Spectrum computer, the two switches 50 and 51 are both closed for the keystroke delay. To enter a shifted character into the computer 22, the units 48 and 49 are controlled to connect the appropriate strobe terminal to the appropriate sense terminals for the Spectrum key associated with that character and the switch 50 or 51 is closed over the same keystroke delay, which switch 50 or 51 depending on whether the CAPS SHIFT or the SYMBOL SHIFT is required.

Fig. 6 shows part of the input circuitry 45 connected to the eight lines DO to D8 of the data bus 36. The circuitry 45 includes an input port 53 formed by eight tri-state buffers, each being a buffer of a hex tri-state buffer type 4503. The control terminals of these buffers are connected to a common control line 54 which receives a control signal lR4 from the input/output decoder 42. In operation, all the buffers 53 are either in their high impedance state or are presenting high or low signal levels to the eight lines of the data bus 36. The input terminal of each buffer 53 is coupled through a respective resistor 55, of 100 kilohms in particular example, to a respective one of eight input terminals 56. Each input terminal 56 is connected to one terminal of a respective one of the eight input switches 20, shown in Fig.

2, when an eight-switch input device is used. The two buffers 53 connected to the DO and D1 lines of the data bus 36 are also coupled through their resistors 55 to two other input terminals 58 and 57 which are respectively connected to one terminal of the input switch 12 and one terminal of the input switch 11 when a two-switch input device is used. The input terminals 56 are connected through respective resistors 59 to a high signal level voltage rail, in this example at 5 volts positive. Thus if all the input switches are open, or the switches 11 and 1 2 are present and open and the terminals 56 are not connected to any other input switch device, the input signal to each buffer 53 is a high signal which is applied to the respective data bus line when the control signal IR4 goes low.To apply a low signal to any buffer 53, the respective input terminal 56, or 57 or 58 in the case of the DO and D1 buffers, must be connected to ground, which can be effected, as will be seen from Fig. 2, by closing an input switch 20, or 11 or 12, connected to that input terminal.

Fig. 7 shows circuitry for the display 1 9 which includes a LED matrix 60 in which, for simplicity, only one LED 61 is indicated. The matrix 60 has five row conductors 62 and ten column conductors 63 providing fifty connection points for LEDs. The LED at any particular point in the matrix 60 is energised whenever a respective one of five row transistors 64 and a respective one of ten column transistors 65 are conductive, the row transistor 64, then providing a path from a positive voltage rail, of 9 volts in this example, through a resistor 66 to the anode of the LED, and the column transistor 65 providing a path from the cathode of the LED to ground.

Each LED of the matrix 60 is arranged to act as the means of illuminating a respective one of the fifty panels of the overlay of the display 19.

The row and column transistors 64 and 65 are field effect transistors operating as switches. The gate terminals of the row transistors 64 are connected to five output pins respectively of a row decoder 67, which in this example is a four line to sixteen line decoder and latch, type 4514, having four input pins coupled by respective buffers to receive data from the DO to D3 lines respectively of the data bus 36. A control signal IW1 from the input/output decoder 42 can also be applied to the row decoder 67 on a line 68 coupled through an inverter 69 and another buffer to clock input pin of the row decoder 67.The D4 to D7 lines and the control line 68 are coupled in the same way to corresponding input pins of a column decoder 70, which also is a four line to sixteen line decoder and latch, type 4514, having ten output pins connected respectively to the gate terminals of the ten column transistors 65, and another output pin connected to the gate terminal of a field effect transistor 71 serving as a reset switch, having its source connected to ground and its drain connected to the reset signal line 24 which connects the display to the computer 22.

Not all the output pins of the decoders 67 and 70 are shown in Fig. 7, and it will be apparent that a LED matrix larger than the matrix 60 could be controlled by the decoders 67 and 70, or additional functions controlled instead similarly to the reset switch transistor 71.

In operation, the row decoder 67, controlled by data on the DO to D3 data bus lines, determines which row conductor 62 is active. The column decoder 70, controlled by data on the D4 to D7 data bus lines, determines which column conductor 63 is active. Thus the data lines DO to D3 and the row decoder 67 can together be used to effect scanning in a "Y" direction in the matrix 60, and the data lines D4 to D7 and the column decoder 70 can together be used to effect scanning in an "X" direction in the matrix 60.

Also, by alternate enabling of the decoders 67 and 70 and suitable data on the data bus 36, "diagonal" scanning can be effected by alternate steps in the X and Y directions.

Each of the decoders 67 and 70 has in the present example an input pin for a disable signal, pin 23 in the type 4514, to which a disable signal can be applied if developed elsewhere in the system to indicate a condition in which it is required that the matrix 60 should be completely extinguished.

To obtain sufficient brightness from the LEDs of the matrix 60, a substantially higher than normal current is passed through any LED which is to be energised. To avoid damage to the LEDs, the high current is passed intermittently only, the interrupt routine of the program being such that the row and column conductors 62 and 63 of any LED which is to be energised are rendered active only once in every eight runs of the interrupt routine, the interrupt routine being run 1200 times per second. The resistor 66 may be, for the 9 volt supply indicated, a 39 ohm resistor with a maximum rating of 4 watts. Hence by multiplexing, more than one LED can appear to be energised a' the same time.

The circuitry 43 for scan and actuate delays and scan mode selection is shown in Fig. 8. Two monostable circuits 72 and 73, each including a unit of a dual precision monostable integrated circuit type 4538, are provided to set the scan delay and the actuate delay respectively. The scan delay circuit 72 includes a resistor arrangement 74 connected to a capacitor 75 and including a variable resistor 76 mechanically controlled by the knob 26 of the unit 10. The resistor arrangement 74 and the capacitor 75 together determine the time constant of the scan delay circuit 72 and hence the value of the scan delay.

The actuate delay circuit 73 is similarly constructed and includes a variable resistor 76 mechanically controlled by the knob 25 of the unit 10. The monostable circuits 72 and 73 can be triggered when a control signal IR3 on a line 77 from the input/output decoder 42 is low, the scan delay monostable circuit 72 being triggered by a signal on the AO address line of the address bus 35, and the actuate delay monostable circuit 73 being triggered by a signal on the Al address line of the address bus 35. The output terminals of the monostable circuits 72 and 73 are connected respectively to two of a set of eight tri-state buffers 78, type 4503, which are controlled by a control signal IR1 on a line 79 from the input/output decoder 42.The output terminals of the tri-state buffers 78 are connected to respective data lines of the data bus 36 as shown in Fig. 8, the output terminals of the circuits 72 and 73 being thus coupled to the data lines DO and D1.

The input terminals of the six buffers 78 connected to the data lines D2 to D7 are coupled to ground through respective resistors 80 of, for example, 100 kilohms. The buffers for lines D2 to D5 are also connected to respective fixed contacts 85, 84, 83 and 82 of a mode selector switch 86 having two other fixed contacts 81 and 87 isolated, and a movable contact 88 mechanically controlled by the knob 27 of the unit 10. The movable contact 88 can be set in electrical contact with any one of the six fixed contacts 81 to 85 and 87, which are associated with input modes 1 to 5, and an OFF condition respectively. The input modes 1,2 and 3 are scanning modes in which user operation of an input switch device with the two switches 11 and 1 2 results in a scanning operation of the LED matrix 60.Mode 4 is a mode of operation with an eight-switch input device in which successive closure of two of the switches 20 can be used to selectively energise any LED of the matrix 60.

Mode 5 is a mode of operation with a keyboard input device, described hereinafter, with which no use is made of the matrix 60. It will be seen from Fig. 8 that mode 1 is a default mode, the fixed contact 81 being isolated. Thus even if the switch 86 is set in the OFF position, in which the movable contact 88 touches the fixed contact 87, mode 1 operation can be effected. It will also be seen that for modes 2, 3, 4 and 5, a high signal level is applied from the movable contact 88 to the data lines D5, D4, D3 and D2 respectively.

In operation when the end of the scan delay or the actuate delay is being awaited, the buffers 78 are enabled sufficiently frequently by the control signal IR1 for there to be only a negligible error in the sensing of the occurrence of the end of the delay. In the operation described in detail hereinafter, the range of scan delay values provided by the variable resistor 76 of the scan delay circuit 72 is at least 0.2 secs to 2 seconds.

The same minimum extent applies to the range of actuate delay values provided by the variable resistor 76'. The capacitor 75 and the corresponding capacitor in the actuate delay circuit 73 is in this particular example 4.7 microfarads.

Fig. 9 shows the tape recorder control circuitry and audio tone output control circuitry 46. The circuitry 46 includes a latch unit 89, the example shown being an octal D flip-flop, type 74C374, having eight input pins connected respectively to the eight data bus lines DO to D7. An enabling signal 1W3 from the input/output decoder 42 can be supplied to the latch unit 89 on a line 90 connected thereto. Four of the output pins, at which signals on the data lines DO to D3 can be respectively latched, are connected respectively to the gate terminals of four field effect transistors 91 arranged to act as control switches for four relay windings 92 to 95 connected to a suitable supply (9 volts positive). The relay windings 92 to 95 respectively control relay contacts 96 to 99.

The winding 92 and contacts 96 comprise first relay, referred to hereinafter as relay 1, which controls energisation of the record solenoid (not shown) of the tape recorder 18; the winding 93 and contacts 97 comprise a second relay, referred to hereinafter as relay 2, which controls energisation of the rewind solenoid (not shown) of the recorder 1 8; the winding 94 and contacts 98 comprise a third relay, referred to hereinafter as relay 3, which controls energisation of the play solenoid (not shown) of the recorder 18; and the winding 95 and contacts 99 comprise a fourth relay which is not used in the present example but could be used to control energisation of a solenoid for controlling fast forward operation of a tape recorder.The contacts of the relays used are connected by the control lead 1 7 to the recorder 1 8 as indicated in Fig. 9. Back e.m.f. protection for the transistors 91 and the contacts 96 to 99 is provided by diodes and zener diodes pairs connected as shown.

The two output pins of the latch unit 89 at which signals on the data lines D6 and D7 can be latched are connected respectively to the two input terminals of a ceramic sounder 100, for example type AT-27 of Projects Unlimited. In operation, an audio tone is produced from the sounder 100 by toggling the sounder inputs at the rate of occurrence of the interrupt routine, so that in the example of operation described hereinafter the sounder 100 can produce a tone at 1200 hertz.

When the fast forward relay 4 is brought into use, a buzzer may be arranged to operate at the times when the winding 95 is energised by providing a grounding connection 101 for the buzzer circuit controlled by the field effect transistor 91 for data line D3.

Fig. 10 shows the central processor unit 29, which is a Zilog Z80 microprocessor from Zilog (U.K.) Limited of Babbage House, Maidenhead, Berkshire SL6 1 DU, and its connections to the output inverter 33 supplying system clock pulses, the interrupt generator 38 (at a line 102), the data bus 36, the address bus 35, and the four control lines 40 to the control logic 41. The conventional designations of Z80 control signals are shown in Fig.10 adjacent the input or output pins at which they occur in operation. It will be seen that the four control signals supplied to the control logic 41 are memory request MREQ, read RD, read RD, write WR and input/output request IORQ.The pins for the wait signal WAIT, non-maskable interrupt NM I, and bus request BUSRQ are connected to the high signal level, 5 volts positive, permanently. A resistance-capacitance reset signal generator 103 is connected to the reset pin so that the processor 29 receives a reset signal RESET automatically on switching on the power supply to the system.

Fig. 11 shows the circuitry of the crystal oscillator 31, divide-by-two circuit 32, counter 39 and interrupt generator 38. The crystal oscillator 31 has component values such that the frequency of oscillation is, in the particular example, 2.4576 megahertz, so that system clock frequency is 1.2288 megahertz, the output of the divide-bytwo circuit 32 being supplied on a line 104 to the inverter 33. The circuit 32 is a J-K flip-flop such as one unit of a dual J-K flip-flop type 74C107.

The other unit of this dual J-K flip flop is shown as the interrupt generator 38. The Q output of the circuit 32 is supplied as the clock input to a ripple counter, type 4040, serving as the counter 39. To obtain an output at 1200 hertz, the Q10 output of the counter 39 is taken and is supplied as the clock input to the interrupt generator 38. The reset signal produced by the input/output decoder 42 at the beginning of each interrupt routine is supplied as a signal IR2 to the reset pin of the generator 38 over a line 105.

Fig. 12 shows the control logic 41 which receives the control signals MREQ, RD, WR, and IORQ from the processor 29 over the lines 40, and is also connected to address bus line Al 2.

The individual lines 40 on which the signals M REQ, RD, WR and IORQ are transmitted are respectively referred to as lines 40a, 40b, 40c and 40d. The control logic 41 includes four OR-gates 106, 107, 108 and 109 so connected to the lines 40 that gate 106 receives the signals MREQ and RD as inputs gate 107 receives the signal MREQ and WR as inputs, gate 108 receives the signals IORQ and WR as inputs, and gate 109 receives the signals IORQ and RD as inputs. The output signals from the gates 106 to 108 are respectively referred to as the memory read signals MRD, the memory write signal MWR, the input write signal IWR and the input read signal IRD, which are produced on lines 100, 111, 112and 113.

The logic 41 includes two further OR-gates 114 and 11 5. The OR-gate 114 receives the address signal bit on line A12 and the memory read signal MRD as inputs and provide output signals on a line 116. The OR-gate 11 5 receives the memory request signal MREQ from the line 40a and the inversion of the address signal bit on line A12 through an inverter 117, and provides output signals on a line 118.

Fig. 13 shows the read only memory 34 and the random access memory 37. In the present example the read only memory 34 is an eight bit wide 4k EPROM, and the random access memory is an eight bit wide 2k RAM. All eight data lines DO to D7 are connected to the memories 34 and 37. However, it will be seen from Fig. 10 that only address lines AO to A12 form the address bus 35, and from Fig. 13 that of these AO to Al 1 are connected to the twelve address pins of the read only memory (ROM) 34 and AO to A10 are connected to the eleven address pins of the random access memory (RAM) 37. The memory read control signal MRD is low active, and the signals on address line A12 are used in the ORgate control logic 41 to control addressing of both memories 34 and 37.It will be seen from Figs. 12 and 13 that the ROM 34 can be read only when both the A12 address line signal and the memory read signal MRD are low, and that the RAM 37 can be read only when the memory read signal MRD on line 110 is low and the A12 address line signal is high and the memory request signal MREQ is low, the latter two signals ensuring a low output from the gate 11 5 on line 118 which is connected to the enable input pin of the RAM 37.

The purpose of the gating of the inverted Al 2 signal with the memory request signal MREQ is to ensure that the RAM 37 only consumes power when it is required to be read or written into.

Accordingly, the RAM 37 can only be written into when the signal on line 11 8 is low and the memory write signal MWR is low on line 111.

The memory location addresses in the ROM 35 run, in hexadecimal notation, from 0000 to OFFF, and the memory location addresses in the RAM 37 run from 1000 to 17FF.

If larger read only and random access memories are required, several EPROMS and RAM chips can be used addressed for example, by decoding address lines Al 0, Al 1 and Al 2 with a three to eight line decoder instead of the inverter arrangement between the address line A12 and the gate 11 5.

The control logic 41 supplies the input write control signal IWR on line 112 and the input read control signal IRD on line 113 as input signals to the input/output decoder 42 which is shown in detail in Fig. 14. The decoder 42 also receives the address bit signals on the A3 and A4 address lines, and produces on output lines 119 to 126 the control signals IW1, IW2, IW3, IR1, IR2, IR3 and IR4.

The input/output decoder 42 is formed by a pair of two-to-four line decoders 127 and 128, which in this example are a dual two-to-four line decoder type 4556. Both decoders 127 and 128 receive the A3 and A4 address line signals at their input line pins. The line 112 supplies the input write control signal IWR to the enable pin of the decoder 127, and the line 113 supplies the input read control signal IRD to the enable pin of the decoder 128. The 00, 01 and Q2 output pins of the decoder 127 are connected respectively to the lines 119,120 and 121,andtheQOtoQ4 output pins of the decoder 128 are connected respectively to the lines 123 to 126. The Q4 output pin of the decoder 127 is connected to the line 122 but no use made, in the present example, of the Q4 signals on this line.The lines 119 to 121, and 123 to 126 are connected as follows:- line 11 9 to the input terminal 68 of the inverter 69 of the display circuitry shown in Fig. 7; line 120 to the clock input pin of the latch unit 47 of the interface circuitry 44 shown in Fig. 5; line 121 to the clock input line 90 of the latch unit 89 in the relay control and audio tone output control circuitry 46 shown in Fig. 9; line 123 to the enable signal line 79 of the tristate buffers 78 of the delays and scan mode selection circuitry 43 shown in Fig. 8; line 124 to the reset signal line 105 of the interrupt generator 38 shown in Fig. 11; line 125 to the enable signal line 77 of the monostable circuits 72 and 73 of the delay circuitry shown in Fig. 8; and line 126 to the enable signal line 54 of the tristate buffers 53 of the input circuitry 45 shown in Fig. 6.

Thus the signals IW1, IW2 and IW3 are used as addressing or enabling signals to the data output ports of the display 19, the computer interface 44 and the tape control and audio tone output control circuitry 46, and the signals IR1, IR2, IR3 and IR4 are used as addressing or enabling signals to the data output port of the delays and scan mode selection circuitry 43, the interrupt generator 38, the scan delay and actuate delay monostables 72 and 73, and the data output port of the input circuitry 45.

It will be seen from the above description that the central processor unit 29 together with the clock and interrupt generating circuits, the memories, and control logic and input/output decoder, and the peripheral units connected to the data bus constitutes an apparatus for entering characters into the computer 22, which in the present example is a ZX Spectrum computer.

Another apparatus for entering characters into a computer is described in detail in our copending patent application no. 82 24960, in which the computer is a ZX81, and the apparatus has, instead of a unit with a LED matrix display, a keyboard.

Fig. 1 5 of the accompanying drawings illustrates a keyboard unit 1 29 which is an alternative to the unit 10 of the Fig. 1. The keyboard unit 129 has a housing 130 with five arcuate rows of ten circular apertures each giving access to a respective circular key 131 serving as a character indicator or as a special function indicator, the significances of the keys being the same as, and the keys being arranged in the same order as, the panels of the display 19, except that the top left hand key, given the reference 131' in Fig. 1 5, is spare, as are the next five keys to the right in the top row. Preferably the circular apertures are defined by inwardly curved edges in the housing 130 so that a user's finger can receive guidance towards the keys from the housing 1 30. The rows are centered on a point about four feet in front of the keyboard unit 129 so that the keys are arranged in arcs traceable by the hand of a user with his arm outstretched. Also mounted in the housing 1 30 are eight indicator lamps 132 to 139. Each of these lamps is controlled to light up to indicate the performance of some function or the occurrence of some condition associated with the entering of characters into the computer 22 which is, in this example, housed within the unit 129.

The lamp 132 is illuminated whenever a key 131 or 131' is pressed.

The lamp 133 is illuminated whenever a pressed key is accepted as an intended selection by the user.

The lamps 134 or 135 are respectively illuminated when CAPS SHIFT or SYMBOL SHIFT has been accepted and will apply to the next character selected.

The lamps 136, 137 and 138 are respectively illuminated to indicate the play, record and rewind function of the tape recorder 18.

The lamp 139 is illuminated to indicate that RESET is selected and accepted.

All the apparatus of Fig. 4, modified as will be described hereinafter with reference to Figs. 1 6 and 17, is housed in the keyboard unit 129 together with the ZX Spectrum computer 22. The knobs 25 and 27 are provided also (not shown in Fig. 15), but the knob 26 for scan delay adjustment is not required. Connection to the television receiver 14 and the tape recorder 1 8 are also provided. However, the connections to the input switch device are within the housing 1 30 with the input switch device itself which is in the form of a set of fifty switches 140, indicated in Fig. 1 6, controlling an eight by fifty diode matrix 141. Each key 131 or 131' controls a respective one of the switches 140.As shown in Fig.16, the switches 140 and the fifty conductors 142 to which they are connected are grouped in tens, each corresponding to a row of keys. Only some of the conductors 142 and switches 140 are shown in Fig. 16, and diodes are indicated schematically as at 143. The eight data conductors 144 of the matrix 141 are connected respectively to the eight input terminals 56 shown in Fig. 6, and the mode selector switch 86 of Fig. 8 is set to mode 5 (contact 85).

Fig, 1 7 shows a modification to Fig. 4 which is a feature of the keyboard unit 129. Instead of the display 19 of Fig. 4, the unit 29 has lamp drivers and reset circuitry 145 connected to the data bus 36. The lamp drivers and reset circuitry 145 produces the signals necessary for controlling the energisation of the indicator lamps 132 to 135 and 139 and for generating the reset signal for line 24.

The operation of the apparatus illustrated in Fig. 4 for entering characters into the computer 22 and controlling the tape recorder 1 8 will now be described in more detail.

The ROM 34 holds a program in which the Z80 processor unit 29 operates in its interrupt mode 1 in which in response to a low active interrupt signal (INT) the processor unit (CPU) 29 automatically branches to memory location 0038 (hexadecimal) after storing the return address of the main program in a stack region of the RAM 37. Operation of the Z80 microprocessor is described in Basic Principles and Practice of Microprocessors by D. E. Heffer, G. A. King and D.

C. Keith, published by Edward Arnold (Publishers) Limited, 41 Bedford Square, London WC1 B 3DQ in 1981, and other publications. Further details of the operation of the Z80 microprocessor can be obtained from Zilog (U.K.) Limited.

The interrupt routine of the program in the ROM 37 has an initial stem section in which a value stored in a temporary storage region, referred to hereinafter as TIMER1, is decremented, the condition (status) of the inputs of the ceramic sounder 100 is toggled, and one of eight different subroutines, referred to hereinafter as MODO, MOD 1, MOD2, MOD3, MOD4, MODS, MOD6 and MOD7 is carried out before the return to the main program. The value in TIMER1 is started from a number referred to hereinafter as TIME1 which when counted down at the 1200 hertz rate of the interrupt routine provides a time suitable for the duration of an audio tone output from the ceramic sounder 100. When the value in TIMER1 is zero, the interrupt routine jumps round the toggling of the inputs to the sounder 100, so that the sounder 100 is silent when TIMER1 contains zero.

The eight subroutines MODO to MOD7 control the operation of the LED matrix 60 of the display 19. To ensure that excessive power is not supplied to any LED, data commanding the illumination of LEDs in accordance with the user's input to the input circuitry 45 is not used directly to control the LEDs but is stored in seven temporary storage regions of the RAM 37 designated SLOTO, SLOT1, SLOT2, SLOT3, SLOT4, SLOTS and SLOT6, and is transferred, in a multiplexing operation effected by the interrupt routine in such a way as to ensure that no LED can be energised more than once in every eight passes of the interrupt routine, to seven further temporary storage regions of the RAM 37 designated MUXO, MUX1, MUX2, MUX3, MUX4, MUX5 and MUX6.The data stored in any of the regions SLOTO to SLOT6 and MUXO to MUX6 is the matrix coordinates of an LED of the matrix 60 or a blank code (FF hexadecimal). The presence of LED coordinates in any of MUXO to MUX6 results in energisation of the LED having those coordinates. The presence of the blank code FF in any of MUXO to MUX6 results in no LED of the matrix 60 being energised during a subroutine in which the contents of the MUX region containing the blank code are outputted. The seven subroutines MODO to MOD6 output the contents of the regions MUXO to MUX6 respectively. The subroutines MOD2, MOD3, MOD5 and MOD6 are concerned only with the outputting of the respective MUX contents.

Subroutine MOD 1 includes also the decrementing of the value held in a temporary storage region TIMER2 of the RAM 37, which will also be referred to as the keystroke timer and used to cause the computer interface 44 to present any character code to the computer 22 for sufficient time for the character code to be sensed by the computer 22. The starting value in the keystroke timer TIMER2 is designated KTIME and provides a time of substantially 125 milliseconds when counted down by MOD1 (i.e.

at a rate of 1 50 hertz).

MODO and MOD4 output the contents of MUXO and MUX4 respectively and also carry out the obtaining of input data from the input circuitry 45, including the debouncing of this data. Two forms of debounced data are produced, one form being appropriate for inputs from input switch devices in which only one switch can be operated at any time, such as the devices having the two switches 11 and 12 or the eight switches 20 mechanically shielded against concurrent operation, and the other form being appropriate for inputs from devices in which any number of switches can be operated at the same time, such as the switches of the keyboard unit 129. Four temporary storage regions of the RAM 37 are used, designated INSTAT, IPSTAT, DESTAT and DESTAT+ 1, in this process.The region IPSTAT is used as a debounce timer, being loaded at appropriate instants with a value, in this example OA (hexadecimal), which is decremented to give the debounce time. The data stored in INSTAT is the data from the buffers 53 of Fig. 6 present when the debounce timer last stopped running or present immediately after the first change in the data which occurred from the condition existing before the debounce timer started running from a non-running condition. The debounce timer starts running each time there is a change in the data from the buffers 53, so that if a change occurs while the debounce timer is running, the timer is re-started, i.e. the timer starts running from a running condition.

Consequently a sequence of changes in the data from the buffers 53 which occur sufficiently close together for the debounce timer to run continuously from the occurrence of the first change until the end of the debounce time after the last change causes the data in INSTAT to register only the data appearing after the first and last changes in the sequence. The data stored in DESTAT is debounced in a conventional manner, the current i put data from the buffer 53 only being stored in DESTAT when the debounce timer, IPSTAT, reaches zero. The region DESTAT+1 is used to temporarily store current input data for comparison purposes a change in the data from the buffers 53 being detected by comparing the current input data received from the buffers 53 with the data stored in DESTAT+1 at the previous run of a subroutine in which the debounce process is carried out, i.e. in MODO or MOD4.In the debounce process, in MODO, or MOD4, carries out the following steps: 1) The outputs of the buffers 53 are read (new input data).

2) The new input data is compared with the contents of DESTAT+1 (previous input data).

3) If the new and previous data are the same, the debounce timer is tested for expiry (contents of IPSTAT compared with zero).

4) If the debounce timer has expired, the new input data is stored in INSTAT and DESTAT.

5) If the debounce timer has not expired, the contents of IPSTAT are decremented.

6) If at the comparison in step 3 the new and previous data are different, the debounce timer is tested for expiry.

7) If the debounce timer has expired, the debounce timer is restarted (OA hexadecimal loaded into lPSTAT), then decremented.

8) The new input data is stored in INSTAT.

9) If in step 7 the debounce timer has not expired, the debounce timer is restarted, and then decremented. No further debounce action is then taken in this run of MODO or MOD4.

It will be seen that in this way, INSTAT is updated by a change in input occurring when the debounce timer is not running, and when there has been sufficient time since the last change while the timer was running for the timer to expire, and DESTAT is only updated in the latter circumstance.

Since MODO and MOD4 both contain the debounce process, the outputs of the buffers 53 are read 600 times per second. Changes which occur and disappear between two successive readings of the buffers 53 have no effect.

The subroutine MOD7 carries out two processes: a process which results in the LED whose coordinates are stored in SLOTO being flashed while a flash timer, which is a temporary store region designated TIMERL in the RAM 37, is running; and a process in which the contents of SLOTs 1 to 6 are transferred to MUX1 to 5 and MUXO respectively in accordance with priority rules which cause the blank code FF (hexadecimal) to be loaded into any one or more of MUX1 to 5 and MUXO if the coordinates stored in the corresponding SLOT are the same as those stored in a SLOT of higher priority. The order of priority is SLOTO, SLOT 1, SLOT2, SLOT3, SLOT4, SLOTS, SLOT6. In carrying out the flash process, MOD7 includes the step of decrementing the value in TIMERL, and testing for zero.If the value after decrementing would be zero, the blank code is loaded into SLOTO. When the flash timer is running, bit 5 of TIMERL is tested and either the contents of SLOTO or the blank code FF is loaded into MUX6 depending on the state of this bit 5.

Bit 5 is used since it changes at a suitable rate for flashing effect when SLOTO contains the coordinates of a LED.

In the main routine of the program, SLOT6 is used to store the coordinates of the LED to be energised in any scanning processes. SLOTO is used to store the coordinates of the LED of the panel selected by the user to enter a character into the computer 22 or carry out a function associated with that panel. Thus when the user is searching for the desired panel, LEDs will be illuminated steadily in accordance with transfer from SLOT6 to MUXO. When the user selects a panel, its LED will flash for a time determined by the value in TIMERL.

Since SLOT1 to SLOT6 can store and transfer to MUX 1 to 5 and MUXO up to six different LED coordinates, up to six different LEDs can be effectively illuminated together. The main routine stores the coordinates for CAPS SHIFT and SYMBOL SHIFT in SLOT1 and SLOT2 respectively, and for RECORD, PLAY and RESET in SLOT3, SLOT4 and SLOTS respectively.

The eight MOD subroutines are included respectively in eight successive runs of the interrupt routine by the use of the index register X of the Z80 processor 29, the sequence being MOD7 followed by MOXO to MOX6. Each MOD routine loads the index register X with the address for the next MOD routine.

The main program routine starts by establishing interrupt mode 1 and jumping past the interrupt routine to an initialization process in which the stack pointer register of the CPU 29 is initialized, the relays and the ceramic sounder 100 of the tape and audio tone output control circuitry 46 are turned off, a number of temporary storage regions in the RAM 37 are put into initial conditions, the address for MOD7 is loaded into index register X, and the address for another subroutine, labelled CMPOO, is loaded into index register Y of the Z80 processor 29. In this process, SLOT6 is loaded with the coordinates of the HOME SQUARE LED, and the blank code FF is loaded into SLOTO to SLOTS. Also, a starting value, designated TIM EL, is loaded into TIMERL, and a suitable value is loaded into each of INSTAT, IPSTAT, DESTAT and DESTAT+ 1.The subroutine labelled CMPOO is concerned with testing for selection of the tape control or reset panels of the display 1 9. The subroutines for tape control utilize three temporary storage regions of the RAM 37 designated VECT60, VECT70 and VECT80. In the initialization process, the addresses, labelled REW2, PLAY2 and REC2 for the rewind, play and record control subroutines are stored in VECT60, VECT70 and VECT80 respectively. Two further temporary storage regions designated STAT10 and ZXSTAT, are initialized, STAT10 storing the initial condition of the tape and audio tone output control circuitry 46, and ZXSTAT storing the status of shift data to be output of the computer 22 by the computer interface 44.A blank character code, 3F (hexadecimal), is output to the ZX Spectrum computer 22, and the initialization process ends by enabling interrupts and jumping to a monitoring subroutine labelled MONIT1.

In the monitoring subroutine, the scan mode selector switch 86 is read through the buffers 78 and one of five input mode subroutines labelled MODE1 to MODES is jumped to depending on the setting of the switch 86. The chosen input mode subroutine controls the LED matrix 60 in the case of MODE1 to MODE4. Each input mode subroutine ends either with a return to HOME SQUARE (or an equivalent starting condition in MODES) or selection of a special function or a character to be implemented or entered into the computer 22. After selection has occurred, the detection of any special function is carried out in the subroutine labelled CMPOO and if the selection is not a special function, the selected character is sent to the computer 22, or a shift code is stored temporarily in, or cleared from, ZXSTAT.

When a character is to be sent to the computer 22, the coordinates of the LED for that character on the display 19 are used to locate the ZX Spectrum key code in a look-up table stored in the ROM 34, this table being labelled TAB. Two further look-up tabies are stored in the ROM 34, one labelled TABLE2 and the other TABLE3.

TABLE2 is used in MODE4 to convert two successive selections of any one from the eight switches 20 into the coordinates of the LED of the corresponding character panel in the display 1 9.

TABLE3 is used in MODES to carry out a corresponding conversion for the data codes generated by closure of the switches 140 of the keyboard unit 129.

The main routine of the program also includes several processes for indicating, by the use of the sounder 100 and flashing of LEDs, that various user operations are errors. In general, whenever the sounder 100 is required to start producing a tone, the value TIME1 is loaded into TIMER1.

Similarly, whenever a LED is requested to start flashing, the starting value TIM EL is loaded into TIMERL, and the coordinates of the LED must either already be in SLOTO or be loaded in to start the flashing. The duration of a tone can be prolonged by restarting TIMER1 by loading TIME1 in again before the value in TIMER1 reaches zero.

To avoid interference with the bit in TIMER which determines the state of the flashing LED, restarting of TIMERL, when required, is effected by carrying out a logic OR operation on the contents of TIMERL with the value CO hexadecimal, thereby setting only the two most significant bits in TIMERL. In a particular example, the value of TI MEL is chosen to give three flashes over substantially 4 seconds. The time TIME1 may be 50 hexadecimal. The value OA hexadecimal in IPSTAT gives a debounce time of 1/30 seconds with an interrupt rate of 1200 hertz.

The program executed by the CPU 29 will now be described in more detail with reference to the flow charts shown in Fig. 18 onwards of the accompanying drawings. Individual steps in the operation of the CPU 29 will not be described where their nature will be apparent to those skilled in the art. The convention of indicating the contents of a memory region by bracketing its name is followed in the flow charts, and names may be used to represent the addresses of such regions.

Fig. 1 8 shows the initialization process which begins with switching on of the unit 10. Port 10 is the name allocated to the latch unit 89 of the tape recorder control circuitry and audio tone output control circuitry 46 of Fig. 9. STAT10 stores the status of the eight data bits latched into the latch unit 89 from the data bus lines DO to D7.

It will be seen that two subroutines, labelled OFFX and RSTVEC, are called towards the end of the initialization process. These subroutines are shown in Fig.19, OFFX effecting the outputting of a blank character code, 3F hexadecimal, to the computer 22, and RSTVEC establishing the initial conditions for routing the operation of CPU 29 when special functions involving tape control are selected. The index register Y of the CPU 29 is referred to as INDEX Y in the flow charts, and similarly the index register X is there INDEX X.

From Fig. 18 it will be seen that the initialization process ends with entry into the subroutine labelled MONIT1, which is illustrated in Fig. 20, together with the subroutine MODE 1.

In MONIT1, data received on the data bus lines D2 to D5 from the corresponding buffers 78 of the delays and scan mode selection circuitry 46 of Fig. 8 is compared with a set of mode codes in a predetermined order, and when one is found that matches the data from D2 to D7, the jump to the associated input mode subroutine is made. The mode codes are obtained from the ROM 34 as part of the program data. Filtering with 3C hexadecimal extracts the required mode switch data from the outputs of the eight buffers 78.

In MODE1, the contents of INSTAT are compared with FF hexadecimal and if found identical, a jump back to MONIT1 is made, since this indicates that the user has not closed any input switch. If the user closes any input switch of the input switch device, INSTAT is no longer blank, and a subroutine labelled ATRIG1 is carried out which causes the LEDs of the first column (lefthand side) of the matrix 60 to illuminate one after the other until the user releases the input switch, i.e. a vertical scan in the first column, starting from HOME SQUARE, is effected, at the rate determined by the scan delay, until release of the input switch.If the switch is held depressed, i.e. closed, for long enough, the CAPS SHIFT panel LED is illuminated, followed by the HOME SQUARE LED again and so on for as many vertical lines of scan along the first column as desired.

The sounder 100 is operated each time the position of the illuminated LED changes.

ATRIG1 is illustrated in Fig. 21 and includes another subroutine, labelled ASCAN, which is illustrated in Fig. 22. On entering ATRIGl,the CPU 29 triggers the scan delay monostable circuit 72 of Fig. 8, and then enters a loop formed by testing for the end of the scan delay, by inspection of bit 1 (data bus line Dl) from the buffers 78, and testing for complete release of the input switch or switches depressed by the user. The latter test is not specific to any particular switch, and is effected by comparing the contents of INSTAT with FF hexadecimal.It will be seen that if the switch or switches are completely released before the end of the scan delay, there is return from ATRIG. lf, however, the scan delay ends before the switch or switches are released, the subroutine ASCAN is called, and then ATRIG1 repeats.

As shown in Fig. 22, ASCAN alters the contents of SLOT6 and starts the audio tone timer, TIMER 1. The contents of SLOT6, which is an eight bit store, are treated as two equal fields, the X field and the Y field. The Y field defines the coordinate of an LED in the vertical dimension of the matrix 60, and the X field defines its coordinate in the horizontal dimension, the matrix 60 being treated as if arranged in a vertical plane with the LEDs of the top row of panels of the display 1 9 horizontal at the top of the matrix 60.

The Y field coordinate increases in the vertically downwards direction; the X field in the rightwards horizontal direction. Consequently to effect a vertical scan, only the Y field need be changed, each change, except when a return from the bottom row to the top row is required, involving simply increasing the Y field value by unity. To return from the bottom row to the top row, the bottom row value plus one is sensed and the resultant Y field value replaced by the Y field value for the top row, which in the present example is 0 hexadecimal. The bottom row Y field value is, of course, 5 hexadecimal.To effect a horizontal scan, the X field value is increased in steps of 10 hexadecimal until AO hexadecimal is reached, after which the X field value is changed to 00 hexadecimal to implement "wrap-around", i.e. return from the right hand edge column to the left hand edge column of the matrix 60. The bottom row Y field value 5 hexadecimal, and the right hand edge column X field value AO hexadecimal are referred to in the drawings as matrix edge values.

It will be seen from Fig. 22 that ASCAN effects a vertically downward change of one position by the illuminated LED during scanning, this LED being referred to hereinafter as the cursor, or wrap-around in the vertical direction.

Thus ATRIG1 effects vertical scanning until the input switch or switches are released, and also causes the sounder 100 to produce its audio output tone, referred to hereinafter as a beep, at each change in position of the cursor.

When the call to ATRIG 1 in MODE1 ends, BTRIG1 is called. BRIG1 is illustrated in Fig. 23 and differs from ATRIG 1 only in that it ends when any one or more input switches are closed, and that the scanning subroutine called in BSCAN, which is illustrated in Fig. 24.

BSCAN effects the change in the X field value of the cursor coordinates to implement horizontal scanning and, as will be seen from comparison with Fig. 22, is similar to ASCAN.

When the user closes any one or more input switches during BTRIG 1 in MODE 1, a subroutine labelled SELECT is entered.

MODE3 is similar to MODE1 and is illustrated in Fig. 25. The user must initially close any one or more of the input switches. The CPU 29 then executes a loop comparing the content of INSTAT with FF hexadecimal until the switch or switches are completely released whereupon a subroutine ATRIG2 is entered. Fig. 26 shows ATRIG2, which differs from ATRIG1 (Fig. 21) only in testing for closure of any one or more input switches to end ATRIG2. Thus vertical scanning is caused in MODE2 by the release of the input switch or switches initially closed, and is ended by closure of any one or more of the input switches. The CPU29 executes another loop testing INSTAT for release of the input switch or switches after vertical scanning.This loop is left on release and BTRIG 1 is called and effects horizontal scanning until any one or more of the input switches is closed, whereupon SELECT is entered. Input mode2 can therefore be used by persons able only to cause a switch to be momentarily closed, since vertical scanning will occur after a first momentary closure, horizontal scanning after a second momentary closure, and selection after a third momentary closure.

MODE2 is illustrated in Figs. 27 and 28, it being assumed, for simplicity, that a breath pressure actuated input switch device having the two switches 11 and 12 is used, the switch 11 being closed by a reduction in pressure, referred to hereinafter as 'suck', and the switch 12 being closed by an increase in pressure, referred to hereinafter as 'puff'. The presence and identities of suck and puff can be detected from the content of INSTAT, since bit 1 (i.e. the output to data line D1 from the respective buffer 53) is 0 when there is suck, and bit 0 (i.e. the output to data line DO from the respective buffer 53) is 0 when there is puff.

Initially, MODE2 continues only if INSTAT is not blank, i.e. one or more input switches are closed. In the particular example, one or other of the switches 11 and 12 must be closed before the initial triggering of the scan delay monostable circuit 72 is effected in MODE2. After this triggering of the monostable circuit 72, the CPU 29 tests bit 0 of INSTAT, and if it is zero, a jump is made to the beginning of MODE2B which is the end section of MODE2 and is illustrated in Fig. 28.

If bit 0 of INSTAT is not zero at this test, bit 1 is tested to discover whether INSTAT indicates suck. If this test shows bit 1 not zero, the CPU 29 executes a loop alternately testing for puff and suck. If suck is maintained or occurs during the alternate puff and suck testing loop, the CPU 29 tests for the end of the scan delay by testing bit 1 of the data from the buffers 78 of Fig. 8. While suck is maintained and the scan delay has not expired, the CPU 29 executes a loop passing through the three tests in Fig. 27 after the triggering of the scan delay monostable. If during execution of this loop the scan delay expires, the vertifical scanning step subroutine ASCAN is called, after which the scan delay monostable is triggered again as at entry into MODE2.To cause several vertical steps by the cursor, the user must suck at least intermittently to cause ASCAN to be called a sufficient number of times. Provided that the user does not puff, vertical scanning can be started, stopped and restarted as many times as desired. As soon as puff is detected, the CPU 29 jumps to MODE2B, from which it is not possible to return to the loops shown in Fig. 27.

As shown in Fig. 28, MODE2B begins with triggering of the scan delay monostable 72. A test for the end of the scan delay follows immediately and consequently the CPU 29 jumps to a test for puff as indicated at a decision box 1 46. If the puff which caused entry into MODE2B has by this time ended, a test for suck is carried out at a decision box 147. If a suck is detected, the CPU 29 jumps to the SELECT subroutine. If suck is not detected, the CPU 29 jumps back to the puff test of box 1 46. Consequently if there is no input action by the user after entry into MODE2B, the CPU 29 loops through the puff and suck tests of boxes 146 and 147. If a suck occurs during this looping, the jump to SELECT is made.

If the puff which caused entry into MODE2B is maintained, or a puff is commenced while the CPU 29 is looping through boxes 146 and 147, a jump from the puff test box 146 occurs to the test for the end of the scan delay in MODE2B. If the scan delay has not ended, the CPU 29 jumps back to the puff test of box 146. If the scan delay has ended, the scan delay monostable 72 is triggered again (box 148), BSCAN is called to effect one step horizontally, and a test for suck is carried out (box 149), which will give a negative answer when the input device is suitably operated, so that there is a jump to the puff test (box 146). Thus a maintained or repeat puff in MODE2B causes at least one step of horizontal scanning.

If the input device is not breath operated and is such that both switches 11 and 12 can be closed at the same time, MODE2B results in diagonal scanning since suck is found at box 149 so that ASCAN is called at a box 150 before a return is made to the puff test (box 146).

Thus in MODE2, the direction of scanning depends on which one and whether both of the two input switches 11 and 12 are closed, the switch 11 (suck switch) controlling vertical scanning, and the switch 12 (puff) controlling horizontal scanning, with the rule that if switch 11 alone is closed after switch 1 2 has been closed, the scanning ends and the SELECT subroutine follows. It will be noted that if both switches 11 and 12 are closed when the CPU 29 reaches the puff test (box 146), the jump to the test for the end of the scan delay is made.

MODE4 is illustrated in Figs. 29 and 30 and begins with testing for presence of any input switch 20 being closed, this input mode requiring the use of an input switch device having eight switches. If no switch is closed, the CPU 29 jumps back to MONIT1. If the content of INSTAT is not FF hexadecimal, the B and C registers of the CPU 29 are cleared and the contents of INSTAT are compared successively with the eight data input codes which can appear at the input buffers 53 (Fig. 6) depending on which one of the eight switches 20 is closed (Fig. 2). If none or more than one of the switches 20 are at this point found to be closed, the CPU 29 jumps to an error subroutine labelled ERROR. If one of the eight data input codes is matched, register B is incremented up to eight times depending on which code is matched, and then its contents are arithmetically shifted leftwards by four places to allow this first selection of an input code to be stored in the register B separately and with the required significance. Then audio tone timer, TIMER 1, is then started and two successive tests, decision boxes 151 and 152, of INSTAT, each forming a loop with itself as shown, are carried out to ensure that the first selection of an input code has ended before the next begins. The first test (box 151) of INSTAT waits for all input switches to be released, and the second test (box 152) waits for any input switch to be closed. At the end of the second test, the CPU 29 compares the contents of IPSTAT with the eight data input codes again.If there is no match, the ERROR subroutine is carried out. If there is a match, the register C is incremented up to eight times depending on which code is matched, and then its contents are combined with those of the register B so that the contents of register B constitute the more significant field and the contents of register C constitute the less significant field. A subroutine labelled LOOKUP is then called, after which an end section labelled VERIF2 is performed. The LOOKUP subroutine produces either the coordinates of an LED in the matrix 60 or an "illegal" code, which is preferably the blank code FF hexadecimal. In VERIF2, the result of LOOKUP is compared with the illegal code, and if it matches, the ERROR subroutine is carried out.

The reason for the existence of the illegal code is that the successive selection of one from eight gives sixty-four possible combinations, whereas the matrix 60 has only fifty positions. Hence fourteen of the possible combinations resulting from the use of an eight-switch input device are spare or redundant. To avoid having two possible combinations for fourteen of the LED positions, fourteen combinations are not associated with the matrix 60 and their selection leads to the ERROR subroutine.

If the result of the LOOKUP subroutine is not the illegal code, the result, which is the coordinates of a LED of the matrix 60, is loaded into SLOT6 and the SELECT subroutine is entered.

The LOOKUP subroutine is illustrated in Fig. 31 and begins with the loading of the starting address of TABLE2, which is the lookup table converting the sixty-four switch combinations into LED coordinates and the illegal code, and is stored in the ROM 34, into the register pair HL of the CPU 29. The combined contents of the B and C registers of the CPU 29 is held in its accumulator and the contents of the accumulator are added to the address in the register pair HL.

This process is carried out by adding the accumulator contents to those of register L above and incrementing register H if necessary. The resultant address in the pair HL points to the value in TABLE2, which is the LED coordinates or the illegal code corresponding to the particular switch combination chosen by the user, and this value is fetched before the CPU 29 returns to VERIF2 to discover whether the value is the illegal code or not.

The ERROR subroutine which occurs when no switch or two or more switches are closed at either user actuation of the eight-switch input switch device in MODE4 or when the illegal code results from the LOOKUP subroutine is illustrated in Fig. 32.

First in the ERROR subroutine the audio tone timer, TIMER1, is started, and then the starting address for the subroutine CMPOO is loaded into index register Y. The need for the latter step will become apparent hereinafter since the ERROR subroutine is also followed as a result of decisions taken in special function subroutines in which the content of the index register Y is changed. The flash timer TIMERL is then restarted or started by the setting of its two most significant bits, and the content of INSTAT is tested for the presence of the blank code FF hexadecimal to determine whether or not all the input switches have been released. If the switch or switches have not been released, the CPU 29 jumps back to the starting of TIMER1 as indicated.Thus for as long as the input switch or switches are kept closed while the ERROR subroutine is in progress, a loop is followed which maintains the output from the sounder 100 and keeps any LED which has been selected in the process which led to the ERROR subroutine flashing. When all the input switches are released, the CPU 29 loads the HOME SQUARE coordinates into SLOT6 and jumps to MONIT1.

The subroutine for input modeS, labelled MODES, is illustrated in Fig. 33. The input mode5 uses the diode matrix 144 and fifty switches 140 of Fig. 16 and, in the MODES subroutine described hereinafter, assumes the presence of the LED matrix 60 of the display 19. However, by appropriate modification of the interrupt routine it can be arranged that the contents of SLOTO, SLOT1, SLOT2, SLOTS and SLOT6 are used to control the indicator lamps 132 to 135 and 139 of the keyboard unit 129 of Fig. 17. The tape control indicator lamps 136 to 138 can be controlled by additional contacts of the tape control relays, relayl, relay2 and relay3.

Since there are fifty possible different input data codes, referred to hereinafter as mode 5 input bytes, each being an eight bit code appearing at the output terminals of the eight buffers 53 of Fig. 6, the conventional debounce effected through the use of DESTAT is employed in MODES. It will be seen from Fig. 33 that the contents of DESTAT are compared with the blank code, FF hexadecimal, and if there is a match, the CPU 29 jumps back to the MONIT1 subroutine. If DESTAT is not blank, the bits of the input byte are inverted to produce an ASCII code, since TABLE3 associates ASCII codes corresponding to the fifty possible inverted input bytes with the coordinates of the LEDs of the matrix 60 and other codes, such as those resulting from the simultaneous closure of two or more of the fifty switches 140, with the illegal code.Hence TABLE3 contains two hundred and fifty-six values, of which two hundred and six are the illegal code, the total possible number of different eight bit codes which can be sensed by the eight line data bus being two hundred and fifty six.

The CPU 29 next loads the starting address of TABLE3 into the HL register pair and, using the same procedure as in LOOKUP, adds the inverted input byte to this address to produce the address of the corresponding code in TABLE3. The CPU 29 then fetches the code at the computed address and carries out VERIF2, as described with reference to Fig. 30.

Fig. 34 illustrates the SELECT subroutine which occurs as a result of a selection by a user of a character to be entered into the computer 22 or of a special function to be executed. The first part of the SELECT subroutine tests to determine whether the selection is maintained long enough to indicate that the user intends the selection to be implemented. Hence the first step in SELECT is triggering of the actuate delay monostable 73 of Fig. 8 by the appropriate output signals on address line Al and line 125 from the input/output decoder 42. The contents of INSTAT are then compared with the blank code. If the blank code is found, the user has abandoned the selection by releasing the input switch or switches, and accordingly the CPU 29 jumps to a subroutine labelled ABORT2.If the user maintains the closure of the switch or switches, the CPU 29 tests for the end of the actuate delay having occurred by examining bit 0 of the data on the data bus lines (i.e. the signal on data line DO) from the buffers 78 of Fig. 8. Since the actuate delay monostable 73 has only just been triggered, the CPU 29 loops through the INSTAT test and the end of actuate delay test, as indicated in Fig. 34, until the actuate delay ends. The audio tone timer, TIMER1, is then started and the cursor coordinates are stored by loading the contents of SLOT6 in the register C of the CPU 29. Finally, the CPU 29 jumps to the address held in index register Y, this being the starting address of the special function comparison routine CMPOO or another address in the program, will be described hereinafter.

The subroutine CMPOO is illustrated in Fig. 35 and begins with a set of tests carried out on the cursor coordinates to determine whether a special function, i.e. a tape control function or the reset, has been selected, or a panel corresponding to a ZX Spectrum key. If the cursor coordinates match those of the REWIND LED, there is a jump to a subroutine labelled FUNC60, if they match those of the PLAY LED there is a jump to a subroutine FUNC70, for the RECORD LED a jump to FUNC80, and for the RESET LED a jump to FUNC9O. If there is no match, a character and shift subroutine labelled OUTX is called, then a subroutine labelled ABORT1 is called which leads to the subroutine labelled ABORT2 returning to MONlT1, as will now be described with reference to Figs. 35 to 39.

A first part of OUTX is illustrated in Fig. 35 from which it will be seen that the contents of all the registers of the CPU 29 are saved, and then the starting address of the lookup table TAB which relates LED coordinates to Spectrum key codes is obtained from the ROM 35 and the coordinates of the cursor added to this address to produce the address of the key code corresponding to the LED coordinates. In the lookup table TAB, the Spectrum key codes are arranged in groups of four, each corresponding to one column of four LEDs, in the matrix 60, used for indicating four Spectrum key characters or instructions, and being separated by groups of twelve blank character codes i.e. 3F hexadecimal, so that the simple addition of the LED coordinates to the starting address of TAB produces the current address.

The contents of the TAB location at the computed address are fetched and tested to determine whether the Spectrum key code is a shift code or not. Since only the CAPS SHIFT key code (40 hexadecimal) and the SYMBOL SHIFT key code (80 hexadecimal) are equal to or greater than 40 hexadecimal, this test is performed by determining whether the fetched code is less than 40 hexadecimal. If it is not, then the fetched key code represents a shift instruction and a subroutine labelled OUTXS is called. If the fetched key code is less than 40 hexadecimal, it is a character code.It is then necessary to determine whether a shift instruction must be combined with this character code, and therefore the shift data stored in ZXSTAT (filtered by ANDing (ZXSTAT) with CO hexadecimal) is added to the character code before the result is used to produce an input to the Spectrum computer 22 by transmission of the resultant eight bit data to the output part 47 in the computer interface 44 shown in Fig. 5. The shift data from ZXSTAT appears on the data bus lines D7 and D6 to control the switches 50 and 51, and the character code bits appear on the other data bus lines DO to D6 to control the switching units 48 and 49 of Fig. 5. The output data is latched into the port 48 and remains in control of the switching units 48 and 49 and the switches 50 and 51 for sufficient time to ensure that the computer 22 reads the result at the sense terminals ZXDO to ZXD4 (Fig.

5). The subroutine ABORT2 ensures the provision of sufficient time. After the data is sent to port 47, as indicated in Fig. 36, the stored shift data in ZXSTAT is cleared by the loading into ZXSTAT of 3F hexadecimal, the CPU registers are restored, and there is return.

If the Spectrum key code is found in the first test in OUTX to be not less than 40 hexadecimal, OUTXS follows the test. Fig. 36 shows that the first step in OUTXS is the combining, by addition of (ZXSTAT) with the fetched key code, of the stored shift data with the key code which should, on the basis of the first test, be either the CAPS SHIFT key code or the SYMBOL SHIFT key code.

If the user is entering the ZX Spectrum extended mode, the combination of the key code with the stored shift data will be a CAPS SHIFT pius SYMBOL SHIFT instruction, i.e. bits 6 and 7 of the combination will be both 1. To enter this instruction into the Spectrum computer 22, both of the switches 50 and 51 must be closed, and therefore, if when the combination of the key code and the stored shift data is compared with CO hexadecimal there is a match, the CPU 29 outputs FF hexadecimal to the computer interface 44 where the port 47 latches in this interface control data. The CPU 29 then jumps to the step of clearing the stored shift data from ZXSTAT, as shown in Fig. 36.

If there is no complementary shift data stored in ZXSTAT when OUTXS is entered, the comparison of the combination with CO hexadecimal is negative and a subroutine labelled OUTX6 is followed. As shown in Fig. 37, the subroutine OUTX6 compares the key code first with 40 hexadecimal, and then with 80 hexadecimal if there is no match at the first of these two tests, there being the key codes for the CAPS SHIFT and SYMBOL SHIFT instructions respectively. Both tests should not give negative answers, but if this occurs, the CPU 29 jumps back to the step of clearing the stored shift data in OUTX (Fig. 36). If one or the other test is positive, the status of the corresponding shift bit in ZXSTAT is inserted, i.e. the stored shift bit is toggled.The non-shift bits 0 to 5 of ZXSTAT are set to 1, and the new contents of ZXSTAT are output to the interface port 47. Since the shift bits stored in ZXSTAT at the beginning of OUTXS in this case were either both 0 or were in the same states as bit 6 and bit 7 of the key code, i.e. 1 and O for CAPS SHIFT and 0 and 1 for SYMBOL SHIFT, and a first shift instruction is to be cancelled by being followed immediately by the same shift instruction, toggling of the shift bit of ZXSTAT corresponding to selected key code has the required effect of either setting the corresponding shift bit of ZXSTAT to 1 or clearing it to 0. After outputting the new ZXSTAT contents to the. port 47, the CPU 29 jumps back to the final step of OUTX in Fig, 36, which is the restoring of the registers.

In the subroutine CMPOO (Fig. 35), after OUTX is called, ABORT1 is called. The subroutine ABORT1 is illustrated in Fig. 38 and begins with the starting of the flash timer, TIMERL. The cursor coordinates stored in register C are then loaded into SLOTO so that the LED at the final position of the illuminated LED in the input mode which led to SELECT is flashed, thereby indicating to the user that selection of this position has been effected. The initial time value, KTIME, for the keystroke timerTIMER2 is then loaded into TIMER2 and the contents of TIMER2 are repeatedly tested for the presence of the value 01 hexadecimal, which is the lowest value that is allowed for TIMER2.The repeated testing ensures that sufficient time is given for the ZX Spectrum computer 22 to read the input presented to it as a result of the operation of the computer interface 44. The flash timer is then restarted by the setting of the two most significant bits in TIMERL. The selected LED continues to flash until the input switch or switches are released, the flash timer being restarted repeatedly until INSTAT is blank.

When the input switch or switches are released, the CPU 29 enters ABORT2, which is illustrated in Fig. 39.

ABORT2 ensures that the matrix 60 will indicate any stored shift instructions, outputs a blank character, which is combined with the stored shift instructions, to the interface 44, loads the HOME SQUARE coordinates into the cursor memory SLOT6, and returns the CPU 29 to the MONIT1 subroutine. Stored shift instructions are indicated as a result of the loading of SLOT1 or SLOT2 with the CAPS SHIFT LED coordinates or the SYMBOL SHIFT LED coordinates respectively, bit 7 of the contents of ZXSTAT being tested to determine whether CAPS SHIFT is to be indicated, and bit 6 of the contents of ZXSTAT being tested to determine whether SYMBOL SHIFT is to be indicated. When bit 6 or bit 7 is 0, the blank code FF hexadecimal is loaded into SLOT1 or SLOT2.The CAPS SHIFT LED is in the first column and fifth row of the matrix 60, and accordingly the coordinates are 04 hexadecimal.

Similarly, SYMBOL SHIFT in the ninth column and fifth row has the coordinates 84 hexadecimal. The coordinates of the shift instructions LEDs are in this subroutine provided by the ROM 34. The HOME SQUARE coordinates, 00 hexadecimal, are similarly provided by the ROM 34. As described hereinbefore with reference to Fig.19, the subroutine OFFX combines the shift bits of ZXSTATwith the null character 3F hexadecimal and outputs the combination to the interface 44.

The process of combining the stored shift data with 3F hexadecimal is effected by an OR operation on the contents of ZXSTAT with 3F hexadecimal. As a result, the interface port 47 holds both switching units 48 and 49 in their nontransmitting states, so that there is no coupling of the ZX Spectrum strobe terminals ZXA8 to ZXA15 to the ZX Spectrum sense terminals ZXDO to ZXD4 by the switching units 48 and 49, but closes both shift control switches 50 and 51. This ensures that the interface 44 ends the inputting of any selected key character to the ZX Spectrum computer 22 but continues any shift instruction data, in case the sensing of the shift data is not co-terminus with the sensing of character data.

Figs. 40 to 43 illustrate respectively the subroutines FUNC6O, FUNC70, FUNC80 and FUNC90 which establish procedures for implementing the special functions tape rewind, play, record and computer reset respectively. Use is made of the index register Y in FUNC60, FUNC70 and FUNC80 and, as will be seen from the description hereinafter, this enables the response of the CPU 29 to selections made after a tape control special function subroutine has been entered to depend upon the particular subroutine and the particular subsequent selection. Thus, on entering the subroutines FUNC6O to FUNC80 for the first time after the starting address of the subroutine CMPOO has been loaded into the index register Y, the CPU 29 is routed respectively to the subroutine labelled REW2, PLAY2 or REC2.

The computer resetting function will now be described with reference to Figs. 43 to 46.

As Fig. 43 shows, FUNC9O begins with the loading of the cursor coordinates into SLOTS, which is reversed for storing the RESET LED coordinates. To ensure that the computer resetting function is implemented only if deliberately chosen, the FUNC9O subroutine establishes the subsequent selection of the "ENTER" character panel as the necessary condition for implementation by the loading of the starting address of a subroutine labelled RESET2 into the index register Y, the ABORT1 subroutine then following. It will be seen from Fig. 34 that the next selection by the user will lead to RESET2, which is illustrated by Fig. 44.In RESET2, the coordinates of the selected LED are compared with those of the ENTER LED, and if they match, which they will if the "RESET" selection was and still is intended, the CPU 29 jumps to a subroutine labelled RESET3 and illustrated by Figs. 45 and 46. If the user has made a mistake or has changed his mind after selecting "RESET", the cursor coordinates will not match those of the ENTER LED, the starting address of the CMPOO subroutine is loaded into the index register Y to restore the SELECT subroutine to its normal condition, SLOTS is loaded with the blank code to extinguish the RESET LED, and ABORT1 is carried out.

In RESET3, the initial contents of VECT60, VECT70, VECT80 and the index register Y are restored, all of the tape control relays are turned off and their status in STAT10 altered accordingly, and the blank code is loaded into SLOT2 to 4 to extinguish the symbol shift and tape functions LEDs. The resetting of the computer 22 is effected by closure of the FET71 of Fig. 7 which is controlled by the decoder 70. The FET71 is connected to the decoder 70 in such a way that its closure has no effect on the LED matrix 60. For example, the FET71 may be closed in response to the application of the code EE hexadecimal to the decoders 67 and 70 through the data bus 36.

Thus by loading of such a reset code into SLOT1, RESET3 ensures closure of the FET71 by the interrupt routine. Then the audio tone is produced (Fig. 46) by starting TIMER1, and the CPU 29 loops until the contents of TIMER1 reach 01 hexadecimal.

The blank code is then loaded into SLOT1, the contents of ZXSTAT cleared to 3F hexadecimal, the ENTER panel LED is flashed until the input switch or switches are released, the RESET panel LED blanked, and the HOME SQUARE coordinates loaded into SLOT6, the CPU 29 then jumping back to MONIT1.

If the rewind function is selected when the tape recorder 1 8 is neither playing nor recording, FUNC6O (Fig. 40) routes the CPU 29 to REW2 which is illustrated in Fig. 47 and begins by resetting bits 3, 2, 1 and 0 in STAT10 to 0, and then setting bit 1 to 1 and sending the result to port 10, i.e. the latch unit 89, of Fig. 9 to turn on relay 2 (winding 93, contacts 97) which controls the rewind function of the tape recorder 1 8. The REWIND LED is then flashed and the CPU 29 waits until the input switch or switches have been released and then closed again before resetting bits 3, 2, 1 and 0 in START10 again and turning off all the relays of Fig. 9. The starting address of CMPOO is then loaded into the index register Y and a subroutine ABORT4 carried out.

ABORT4 is illustrated in Fig. 48 and consists in a test loop waiting for the input switch or switching to be released, followed by return of the cursor to the HOME SQUARE and a jump to MONIT1.

When the PLAY panel LED is selected and the tape recorder 1 8 is not already operating in any mode, FUNC70 leads to PLAY2 which is illustrated in Fig. 49. SLOT4 is allocated to the storing of the PLAY LED coordinates and PLAY2 starts with the loading of these coordinates into SLOT4. STAT10 is then updated and relay3 (winding 94, contacts 98) turned on. It is arranged that to stop the play mode, the PLAY or RECORD LED must be selected. Selection of the REWIND LED is a mistake and leads to the ERROR subroutine (Fig. 32). Therefore PLAY2 uses the index register Y to load the starting address of ERROR into VECT60, and of a subroutine RECOFF into VECT70 and VECT80.Then CMPOO is reestablished, and a subroutine ABORT3 carried out which is shown in Fig. 50. ABORT3 flashes the PLAY LED and leads to ABORT4 (Fig. 48).

It will be seen from FUNC70 (Fig. 41), that selection of the PLAY LED when RECOFF is pointed to by VECT70 leads to RECOFF being executed. RECOFF is illustrated by Fig. 51 and consists in the blanking of the RECORD and PLAY LEDs, initializing of VECT60 to VECT80 and the index register Y, updating of STAT10, turning off of all relays, and execution of ABORT4.

Selection of the RECORD panel LED when no other tape operation is in progress leads through FUNC80 to REC2, shown in Fig. 52, in which the RECORD LED coordinates are loaded into the allocated store SLOT3, the start of REC3 loaded into the index register Y, and ABORT3 executed. It is now necessary to select the PLAY panel LED to complete selection of the record mode of the tape recorder 1 8. At the next selection by the user, SELECT leads to REC3, Fig. 53, which begins by testing the cursor coordinates for a match with those of the REWIND LED and, if there is a match at this point, the RECORD LED is blanked, the index register Y initialized, and the rewind subroutines executed. If the cursor coordinates are not those of the REWIND LED, PLYTST (Fig.

53) is executed, beginning with a test for matching of the PLAY LED coordinates. If there is no match at this point, RECTST (Fig. 54) is executed, which leads to ERROR if, for some reason the cursor coordinates are now found to be those of the REWIND LED, and to RECOFF (Fig.

51) otherwise. If in PLYTST (Fig. 53) the PLAY LED coordinates are found, the cursor coordinates are loaded into the allocated store SLOT4, STAT10 is updated and the record and play relays (1 and 3) are turned on. The starting address of RECTST is then loaded into all three VECT stores, and the index registerY initialized. This ensures that subsequent selection of PLAY or RECORD terminates the recording operation and that selection of REWIND is treated as an error.

It will also be seen from the PLAY2 (Fig. 49) and PLYTST (Fig. 53) subroutines and the SELECT subroutine that the user can enter characters and shift instructions into the computer 22 while the tape recorder 1 8 is in the play or record mode of operation.

A particular feature of the ZX Spectrum computer is that if a character code is presented to it continuously for longer than about 3 seconds, repeated entry of the character code begins and continues at a rapid rate until the character code ceases to be presented.

Consequently, as will be seen from Figs. 35 to 39, if the input switch or switches of the present apparatus are held closed for longer than the necessary time of about 3 seconds, the selected character code will be entered repeatedly, since the input to the computer 22 from the interface 44 is not cleared until OFFX is called in ABORT2, which does not occur until after INSTAT has been found to be blank in ABORT. If necessary, the user can adjust the repeat rate of the Spectrum computer by a Spectrum POKE operation.

Figs. 55 to 67 illustrate the subroutines of the interrupt.

Fig. 55 shows the stem portion of the interrupt routine in which the audio tone timer, TIMER1, is decremented if not zero, and the sounder inputs toggled, their states being stored as bits 6 and 7 of STAT10. The toggling is effected by an exclusive OR operation on the contents of STAT10 with CO hexadecimal. The stem ends with a jump to one of the eight branches, MODO to MOD7 of the interrupt routine, index register Y pointing the way.

Figs. 56 to 58 show MODO which outputs the contents of MUXO to the matrix 60 and effects the two forms of debounce described hereinbefore. It will be seen from Fig. 56 that the four allocated temporary storage regions INSTAT, IPSTAT, DESTAT+ 1 and DESTAT have their contents transferred to registers B, C, D and E respectively for the purposes of the various manipulations involved in effecting the debounce subroutine. The end of MODO is a return subroutine labelled RETO which is common to all the eight MOD branches of the interrupt.

The process of suppressing the loading of the same LED coordinates into more than one of MUXO to MUX6 is indicated in Figs. 65 to 67 which show MOD7. Beginning at Fig. 66, the suppression process involves replacing the contents of a respective register with the blank code FF hexadecimal whenever the contents of a SLOT under test are found to match those of a higher priority SLOT. Consequently in the step of Fig. 67 of loading the contents of the registers into MUXO to MUXS, only the blank code or an unduplicated set of LED coordinates is transferred to each MUX.

Claims (24)

Claims

1. Apparatus for entering characters into a data processing system, the apparatus comprising a first plurality of character indicators which can be selectively activated serially by a user, means for generating in response to activation of each indicator a respective first signal code, a memory storing a second plurality of mutually distinguishable second signal codes, means for retrieving from the memory a predetermined respective one of the mutually distinguishable second signal codes in response to generation of each of at least some of the first signal codes when generation of the respective first signal code is maintained for a predetermined time interval, and means for presenting an input determined at least partly by a retrieved second signal code to a data processing system.

2. Apparatus according to claim 2, wherein the means for presenting an input includes means for receiving interrogating signals from a data processing system and for responding thereto by outputting signals encoded in a manner determined at least partly by retrieved second signal codes.

3. Apparatus according to claim 1 or 2, wherein the apparatus includes at least one significance modifier which can be selectively activated serially amongst the said character indicators by a user, means for generating in response to activation of the significance modifier maintained for the said predetermined time interval a modification signal code and storing the modification signal code in a temporary storage region of the memory while any one of a group of the character indicators in which each has plural significance is activated and the second signal code corresponding thereto is retrieved, the said means for presenting an input being adapted to so combine with the said corresponding retrieved second signal code in response to storing of the modification signal code an indication of the activation of the significance modifier that the said input is determined by the combination of the said corresponding retrieved second signal code and the said indication.

4. Apparatus according to claim 2 or 3, wherein the means for receiving and responding to interrogating signals includes means for receiving a series of recurrent distinguishable interrogating signals and selecting any one from among the series of interrogating signals and responding to the selected interrogating signal.

5. Apparatus according to claim 4 when dependent upon claim 3, wherein the means for receiving and responding to interrogating signals includes further means for selectively responding to a particular predetermined recurrent one of the interrogating signals, the said further means being arranged to operate in dependence upon the presence of the modification signal code in the memory.

6. Apparatus according to claim 4 or 5, wherein the means for receiving and responding to interrogating signals includes a circuit for receiving a series of recurrent interrogating signals and so selecting one from the series in dependence upon a first portion of a retrieved second signal code as to produce a corresponding output signal at an output terminal thereof, and a circuit which is coupled to the said output terminal and is such as to so transmit the said corresponding output signal as to control the presence of parallel coded output signals in dependence upon a second portion of the retrieved second signal code.

7. Apparatus according to claim 6 when dependent upon claim 5, wherein the said further means includes a gating circuit arranged to receive as two input signals thereto at least the active portion of the said particular predetermined interrogating signal and a modifier signal indicating that the modification signal code is stored in the memory and to establish an output signal corresponding to the said particular predetermined interrogating signal only when the said two input signals are coincident.

8. Apparatus according to claim 7, wherein the modifier signal is provided by a circuit which also supplies control signals to the circuit for receiving the interrogating signals, the said control signals determining which interrogating signal is selected.

9. Apparatus according to claim 8, wherein the said circuit which supplies control signals and the said memory are coupled to a data bus which is coupled to a central processor which, in accordance with a program stored in the memory, is adapted to cause second signal codes and indications of activation of the significance modifier to be retrieved from the memory and transmitted to the said circuit which supplies control signals.

1 0. Apparatus according to claim 9, wherein means for indicating to a user that the modification signal code is stored in the memory are coupled to the central processor and the stored program is such as to cause the processor to convey absence and presence of the modification signal code in the memory to the said indicating means.

11. Apparatus according to any preceding claim, wherein the means for presenting an input to a data processing system is such that the inputs presented thereby in operation are timer multiplexed parallel binary coded signals.

12. Apparatus according to claim 3 or 4, wherein the memory has stored therein a second signal code which the retrieving means retrieves whenever the significance modifier is activated and generation of a first signal code generated in response to activation of the significance modifier is maintained for the said predetermined time interval, the said means for generating and storing a modification signal code including a central processor which, in accordance with a program stored in the memory, detects acceptance of the first signal code corresponding to the significance modifier and thereupon stores the modification signal code in the said temporary storage region of the memory.

1 3. Apparatus according to any preceding claim, wherein the mutually distinguishable second signal codes are stored in a look-up table in a read only region of the memory, and the said means for retrieving second signal code is such as to generate from each of a plurality of the first signal codes an address for a respective location in the look-up table.

14. Apparatus according to any preceding claim, wherein the means for presenting an input is adapted to replace a matrix-arranged keyboard circuit.

1 5. Apparatus according to claim 1, wherein the character indicators are regions of a visual display apparatus, and the means for generating a respective first signal code includes user operable switching means for selectively activating a user chosen character indicator region of the visual display apparatus.

1 6. Apparatus according to claim 15, wherein the means for generating a respective first signal code includes means for effecting a scanning mode of operation of the visual display apparatus under the control of the user operable switching means, and the means for generating a respective first signal code is adapted to establish a selected first signal code in response to selection of a user chosen region of the visual display apparatus by means of the user operable switching means.

1 7. Apparatus according to claim 1 or 15, wherein the means for generating a respective first signal code includes means for generating ASCII coded signals in response to activation of user operable switching means.

1 8. Apparatus according to any preceding claim, wherein the means for generating a respective first signal code is adapted to control means for effecting resetting of a data processing system, when coupled thereto, in response to activation of a reset indicator.

1 9. Apparatus according to any preceding claim, wherein means are provided for controlling a serial data store of a data processing system when coupled to the apparatus, the means for controlling the serial data store being adapted to be controlled by the means for generating a respective first signal code, and the said generating means being adapted to generate control signals therefor in response to serial activation of serial data store control function indicators.

20. Apparatus according to claim 19, wherein the said means for controlling a serial data store include a plurality of relays.

21. Apparatus according to any preceding claim, wherein the means for generating a respective first signal code and the said memory comprise means for debouncing signals from a user operable input switch device.

22. Apparatus according to claim 21, wherein the said memory includes a temporary storage region in which data representative of whether or not the said input switch device is actuated is stored, the said data being updated in response to a change by the said input switch device from unactuated to actuated or vice versa if there has been no such change for longer than a predetermined time, and being updated whenever there has been no such change for longer than the said predetermined time.

23. Apparatus according to claim 1 and substantially as described hereinbefore with reference to Figs. 1 to 14 and 18 to 67 of the accompanying drawings.

24. Apparatus according to claim 1 and substantially as described hereinbefore with reference to Figs. 4 to 67 of the accompanying drawings.