GB2124851A

GB2124851A - Facsimile system

Info

Publication number: GB2124851A
Application number: GB08309396A
Authority: GB
Inventors: Takehiro Yoshida; Sadasuke Kurahayashi
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1982-04-07
Filing date: 1983-04-07
Publication date: 1984-02-22
Also published as: GB2124851B; JPS58175358A; FR2525057A1; BR8301776A; GB8309396D0; FR2525057B1

Abstract

In a facsimile system, in order to check if a facsimile receiver can correctly receive an image transmitted from a facsimile transmitter, a check signal of a predetermined image pattern is transmitted and received prior to the transmission of the image, and if an error is detected, an image transmission method is changed from a first method to a second or third method so that degradation of quality of received image is substantially reduced even with a system having no automatic equalizer function. Depending on a size of an original and a size of a record paper, second or third image transmission method is selected so that an optimum one of the three image transmission system is selected and a quality of transmitted image is improved.

Description

SPECIFICATION Facsimile system The present invention relates to a facsimile system which is capable of selecting one of a plurality of different image transmission methods in accordance with the status of a transmission line involved.

Afacsimile system of GIll standards (digital type) in accordance with T.4 recommendation of CCITT is well known as a facsimile system which is capable of changing transmission speed or method in accordance with the status of a transmission line. In such a system, prior to high-speed image transmission, an automatic equalizer at a receiver is controlled by training signals and training check signals in accord ancewith transmission line characteristics. Control results are discriminated thereafter to determine the transmission speed and method. Ifthe automatic equalizer cannot be satisfactorily controlled, an error signal is generated to disconnect the transmission line or circuit. Such a facsimile system is costly and is therefore commercially available as a high-priced and high-class system.

In contrast to this, a Gll facsimile system (analog type) in accordance with T.3 recommendation is known as a low priced and intermediate-class system.

However, a Gll facsimile system requires about three times ofthe transmission time as that of a Gill facsimile system, and thus results in highertelephone charge. In view of this, analog-high-speed facsimile systems are widely adopted which have a transmission speed equivalentto that a high-speed system and are inexpensive. An example of a conventional analog high-speed facsimile system, and image degradation which may be caused by such a system by detective circuit characteristics of a transmission line will now be described below.

The first image transmission method will briefly be described in which the amount of image data to be transmitted is controlled in accordance with black and white data of an image to be transmitted. The transmitter divides, into M blocks, an L-bit picture signal array corresponding to one line ofthe image and received from a scanner. If the number of picture elements within one block is represented by N, L = M x N (where L, M and N are all integers). The picture signal within each block is checked. If one block entirely consists of a white signal, an n-bit skip signal is modulated and transmitted in place ofthe N-bit picture signal. If the block includes more than 1 bit of the blacksignal,the N-bit picture signal is modulated and is transmitted. Note the N > n and N = a x where a and bare integers. It is preferable that n > 1.This is because thatthe skip signal has a specific meaning in the method under discussion. IntheAM-PM-VSB or AM-DSB method as the analog transmission method, the error rate is significantly great. Therefore, if n = 1, a correct image may not be received in practical sense.

An I-bit synchronizing signal is added to the start of each line where lisa common multiple of n. Therefore, I > nA A skip signal in this case is an n-bit signal pattern in which a signal of an amplitide higher than the maximum amplitude ofthe picture signal (to be referred to as a high level signal hereinafter) continues for a certain duration and then a signal of zero amplitude ofthe picture signal is present. A synchro nizing signal is an I-bit signal in which a high level signal of a duration longerthan that of the skip signal is followed by a signal of zero amplitude ofthe picture signal.

The transmitter of the above configuration modulates and transmits an image data signal in which an l-bitsynchronizing signal is added at the start of each line and skip signals are included at blocks including all white signals.

The receiver demodulates the sequentially received signal into a base band signal. The receiver checks the amplitude ofthe base band signal to discriminate between the picture signal and the synchronizing and skip signals. The receiver then checks the duration (time interval priorto zero level signal) of the high level signal to discriminate between the synchronizing signal and the skip signal. The receiver discriminates between the skip signal and the picture signal at the timingofreceptionofthenth bitfromthetimingof detecting of the synchronizing signal. The transmitted signal in accordance with the first image transmission method will now be described in further details with reference to the accompanying drawings. Fig. 1 shows the format of a transmitted signal.Fig. 1 (a) shows a picture signal array for one line which is a binary signal having two levels of black and white.

Note that one line has 256 bits, and one block has 64 bits. Thus, one line is divided into 4 blocks. If it is assumed that only the third block includes a black signal, the transmitted signal has a format as shown in Fig. 1 (b).

Before transmitting data of one line, a synchronizing signal is transmitted. Sincethe first block is an all-white block, a skip signal is transmitted in correspondence with it. Since the second block is also an all-white block, another skip signal is transmitted. The third block includes a black signal and the picture signal is therefore is transmitted. Only if the immediately preceding block is a skip signal, a guard band signal is generated priorto transmission of the current picture signal. The guard band signal is generated so as to prevent adverse effects of ringing of the trailing edge of the immediately preceding skip signal having a double amplitude on the leading edge ofthe current picture signal. The 64-bit picture signal ofthethird block is transmitted afterthe guard band signal.Since the fourth block is also an all-white signal, a skip signal is transmitted, thus completing transmission of one line.

Fig. 2 showsthe formats of the synchronizing signal, the skip signal and the guard band signal.As shown in Fig. 2(a), the synchronizing signal is a 56-bit signal including a 46-bit high level duration, a 5-bit blacksignal level duration, anda5-bitwhitesignal level duration, in the order named. As shown in Fig.

2(b), the skip signal is an 8-bit signal including a 6-bit high level duration and a 2-bit black signal level duration. The guard band signal is, as shown in Fig.

8(c), is an 8-bit signal including a 3-bit black signal level duration and a 5-bit white signal level duration.

Sincethetransmission speed is 7,740 bps in this case, the duration ofthe high level signal of the synchronizing signal is 5,943 Cts, whilethat of the skip signal is 775 us Fig. 3 is a block diagram ofthe receiver. A block 10 includes an NCU and an equalizer. The equalizer is of the fixed type and serves to correct attenuation and delay distortion of a telephone line to a certain extent.

An outputfrom the NCU/equalizer 10 is supplied to a signal line 10a. Atelephone line 1 Ob is connected to the input end of the NCU/equalizer 10.

An automatic gain control circuit (to be referred to asanAGCcontrol circuit hereinafter) 12 is connected to the output end ofthe NCU/equalizer 10 through the signal line 1 Oa. Afacsimile signal from the transmitter is attenuated bythe telephone line l0aasatransmis- sion medium before it is received by the receiver. The amount of attenuation varies for each telephone line established. Once the telephone line is established, theamountofattenuation remainsthesame until transmission through such telephone line iscompleted. Therefore, every time facsimile transmission is to be performed, the received facsimile signal must be amplified to a certain level by the AGC circuit 12.A facsimile signal amplified to a certain level bytheAGC circuit 12 is produced onto a signal line 12a. The AGC circuit 12 receives an output from a demodulator 14 through a signal line 14a as a reference signal for performing AGC operation. The AGC circuit 12 also receives a timing signal to determine the timing of the AGC operation through a signal line 1 6e of a signal discriminator 16. The AGC circuit 12 used in this example performs the so-called keyed-AGC operation; it controls the gain such thatthe output peak value ofthe demodulator 14 is 5 V only while the input signal received through the signal line 1 6e is at logic level "1". While the input signal received through the signal line 1 6e is at logic level "0", the AGC circuit 12 maintains the immediately preceding gain.

The demodulator may be an AM-PM-VSB de modulator and may be of a known configuration.

The demodulator 14extractsthecarryfrom the facsimile signal received from the AGC circuit 12 through the signal line 12a, performs synchronous detection, performs full-wave rectification, and pro ducts the resultant received base band signal onto the signal line 14a.

The signal discriminator 16 is an important part of the entire circuitry. Although the function ofthis signal discriminator 16will be described in detail with reference to its block diagram, the signal discriminator 16 discriminates the synchronizing signal, the skip signal, the picture signal and the guard band signal; and transmits them onto signal lines 16a, 16b, 1 6e and 16d, respectively. Atthe same time, the signal discriminator 16 creates a binary image signal from the received base band signal and produces it onto a signal line 16f. When the signal discriminator 16 detects that the synchronizing signal is being re ceived, it produces a signal of logic level "1" on the signal line 16e for only the duration of the synchroniz ing signal being received.Forthis reason, the AGC circuit 12 performs AGC operation forthe time period during which the synchronizing signal is being received.

Upon detection of each of various signals, a control circuit 18 controls a double buffer memory 26 to be described laterthrough a signal line 1 8a such thatthe image data is stored in the double buffer memory 26.

In response to a signal on a signal line 20a, a printer 20 reads out the image data or picture signal data stored in the double buffer memory 26 through a data line 26a and prints the image accordingly.

Atiming clock generator 22 determinesthe timings at which the signal discriminator 16 and a byte buffer 24 are to be operated. Thetiming clock generator 22 generates onto a signal line 22a clocks same as those of bit timing clocks of the transmitter, that is, clocks having a frequency of 7,740 Hz; and also generates onto a signal line 22b clocksof a higher speed than the bittiming clocks ofthe transmitter, that is, clocks having a frequency of 62.5 kHi The byte buffer 24 comprises a serial infparallel out shift register. In response to the bit timing clock received through the signal line 22a, the byte buffer 24 fetches the received binary image data from the signaldiscriminatorl6throughthesignal Iinel6f.

The byte buffer 24 produces 8-bit image data onto a signal line 24a.

The double buffer memory 26 is capable of storing image data corresponding to 2 lines and may thus comprise two 256-bit buffers.

Fig.4 shows a block diagram of the signal discriminator 16. Comparators 30,32 and 34 respectively store reference voltages VH, VZ and Vp. These comparators 30,32 and 34 compare the received base band signal with the reference signals VH, Vz and Vp, respectively, and produce binary signals as the comparison results onto signal lines 30a, 32a and 34a, respectively. Note that VH > Vz > Vp. When the comparator 30 produces a signal of logic level "1" on the signal line 30a upon detection ofthe high level signal shown in Fig. 2, it means reception of the high level signal.On the other hand, when the comparator 30 produces a signal of logic level "0" on the signal line 30a, it meansthatthe input signal is not the high level signal. The comparator 32 serves to detect the black signal level as shown in Fig. 2(b). When the signal line 32a is at logic level "0", it means that black signal level or a black dot is detected at the end ofthe skip signal. The comparator 34servesto detectthe black and white signal levels. The comparator 34 produces onto the signal line 34a a signal of logic level "1" in correspondence with the white signal level or a signal of logic level "0" in correspondence with the blacksignal level.

While the signal on the signal line 30a is at logic level "1 ", a counter 36 counts the timing clocks received through the signal line 22b. Thus, the counter 36 counts the duration ofthe high level signal. In this example, when the high level signal continues for a duration of 384 us or longer, a signal line 36a rises or goes from logic level "0" to logic level "1 ". When the high level signal continues for a duration of 2,048 tis or longer, a signal line 36b goes from logic level "0"tothe logic level "1". Sincethe clocks receivedthroughthethesignal line 22b have a period of 16 loss, a duration of 384 us corresponds to 24 timing clocks received through the signal line 22b, while a duration of 2,048 us corresponds to 128 timing clocks received through the signal line 22b.As has been described with reference to the transmitted signal, the high level ofthe skip signal has a duration of 775 pus, while that ofthe synchronizing signal has a duration of 5,943 us. When the signal line 36a is at logic level "1 ", mea it meansthatthe skip signal or the synchronizing signal is being received. When the signal line 36b is at logic level "1", it means thatthe synchronizing signal is being received.

A multiplexer38 selects one ofthe signals on the output lines 32a and 34a, respectively, ofthe comparators 32 and 34, and produces the inverted signal of the selected signal onto a signal line 38a. Which one ofthe signals is to be selected by the multiplexer 38 is determined by the logic level ofthe signal line 1 6e of a flip-flop 40.

When the signal line 36b goes from logic level "0" to logic level "1", theflip-flop 40 is set and produces a signal of logic level "1" onto the signal line 16e.

When the signal line 36a goes from logic level "0" to logic level "1", a flip-flop 42 is set. Thus, the flip-flop 42 produces a signal of logic level "1" on a signal line 42a and a signal of logic level "0" on a signal line42b. Thus, when the signal line 1 6e ofthe flip-flop 40 is at logic level "1", it is confirmed thatthe snychronizing signal is being received. When the signal line 42e of the flip -flop 42 is at logic level "1 ", it is confirmed that the skip signal orthe synchronizing signal is being received. The signal lines 42a and 42b of the flip-flop 42 have the opposite states; the signal line 42a is at logic level "0" when the signal line 42b is at logic level "1" andviceversa.

A D flip-flop 44 is set or reset in accordance with the level of the input signal received through the signal line 42a when the input signal received through the signal line 38a goes from logic level "0" to logic level "1". When the input signal on the signal line 42a is at logic level "1", the Dflip-flop 44 produces a signal of logic level "1" on the signal line 16b. When the input signal on the signal line 42a is at logic level "0", the D flip-flop 44 produces a signal of logic level "0" on the signal line 16b.

A Dflip-flop 46 is set or reset in accodance with the level ofthe input signal received through the signal line 16ewhenthe input signal received through the signal line 38a goes from logic level "0" to logic level "1". The D flip-flop 46 produces an output onto the signal line 16a; the signal line 1 6a is at logic level "1" when the Dflip-flop 46 is set, and is at logic level "0" when the Dflip-flop 46 is reset.

Acounter48counts bittiming clocks received through the signal line 22a. An output from the counter 48 is cleared by a reset pulse received through a signal line 60a. Everytimethe counter 48 counts 8 bittiming clocks, it produces a signal of logic level "1" onto a signal line 48a. Thus, the byte timing clock which is the same as that in the transmitter is generated onto the signal line 48a.

The circuitfurther includes an OR gate 50, and AND gate 52, an OR gate 54, and a delay circuit 56 which consists of a plurality offlip4lops. The delay circuit 56 delays the input data received through the signal line 1 6b by one clock received through the signal line 1 6c and produces the delayed data onto the signal line 16d.

When the bit timing clock received through the signal line 22a goes from logic level "0" to logic level "1 ", a D flip-flop 58 latches the data received through a signal line 54a produces the latched data onto the signal line 16c.

A pulse generator 60 comprises a monomultivibrator orthe like. When the output from the D flip-flop 58 goes from logic level "0" to logic level "1", the pulse generator 60 generates pulses having a pulse width of several microseconds onto a signal line 60a.

The signal on the signal line 18b is produced from the control circuit 18 shown in Fig. 3.

When data for discriminating the synchronizing signal, the skip signal, the guard band signal and the picture signal is received through the signal lines 16a, 1 6b, 1 6c and 16d, respectively, ofthe signal discriminator 16, the control circuit 18 produces a clear pulse onto the signal line 18b. In response to this clear pulse,theflip-flops40,42,44,46, and 48 are simultaneously cleared.

The configuration ofthe signal discriminator has been described with reference to Fig. 4 but may be summarized as follows. By checking the base band signal received through the signal line 14a so as to detect the duration of the high level signal and detect the presence or absence of the black signal level, the signal discriminator 16 discriminates the synchronizing signal, the skip signal,the guard band signal and the picture signal. The signal discriminator 16 producesthe obtained results onto the signal lines 16a, 16b, l6cand 16d.

When one signal discrimination operation is completed, the signal line 16e goes from logic level "0" to logic level "1 ". At this time, the levels of the remaining signal lines 16b, and 16d are determined. Thefourtypes of signal thus obtained are discriminated in accordance with the algorithm to be shown in Table 1 below.

Table 1

16c 16a 16b 16d i Signal Name 1 1 1 x Synchronizing signal (SY) 1 0 1 x ;Skip signal (SKP) 1 o C - - 1 1, Guard band signal (GRD) 1 o I O ' O ' O ! Picture signal (PIX) where mark"x" representsthatthe level may be either"0"or"1".

The mode of operation of the receiver of the above configuration will now be described with reference to the timing chart shown in Fig. 5.

Fig. 5(a) shows the format of the received signal.

Fig. 5(b) shows a transmitted base band signal atthe side of the transmitter and also corresponds to the received base band signal at the side of the receiver.

When the synchronizing signal begins to be received, the signal line 30a ofthe comparator 30 rises to logic level "1" as shown in Fig. 5(d), indicating that the high level signal is being received. When the high level signal is kept received, the counter 36 i cou nts the du ration of the high level signal. When the counter 36 counts 24 clocks, that is, after about 384 us, the D flip-flop 42 is set as indicated at S1 of Fig.

5(b), and the signal line 42a rises to logic level "1".

When the counter 36 counts 128 clocks, the D flip-flop 40 is set, and the signal line 1 6e goes to logic level "1" as indicated at S2 in Fig. 5(g). Since the signal line 1 6e is kept at logic level "1" during such interval, theAGC circuit 12 controls the gain such that the maximum level ofthe received base band signal may not exceed 5V (Fig. 5(c)). Since an output 50a ofthe OR gate 50 shown in Fig. 4 is at logic level "0" during this interval, an output 52a from the AND gate 52 goes to logic level "0". Since the putputfrom the D flip-flop 46 is also at logic level "0", the D flip-flop 58 is kept reset.

Therefore,the signal line 1 6c of the D flip-flop 58 is kept at logic level "0". Since the signal line 1 6e is at logic level "1" during such interval,the multiplexer 38 selectsthe outputfrom the comparator34and produces an inverted signal ofthe selected signal.

When the signal line 34a ofthecomparator34 goes to logic level "0" as indicated by S3 in Fig. 5(f), a black dot is detected. Then, the signal line 38a goes from logic level "0" to logic level "1", and the D flip-flops 44 and 46 are set. As a result, the signal line 16a ofthe D flip-flop 46 goes to logic level "1", and the signal line 54a of the OR gate 54goes to logic level "1". When the next bit timing signal is generated on the signal line 22a, as indicated by S4 in Fig. 5(1), the D flip-flop 58 is set, and detection ofthe synchronizing signal is signalled to the control circuit 18. Atthistime, the signal lines 1 6a and 1 6b are at logic level "1".

Although not shown, since the signal line 16d ofthe delay circuit 56 is at logic level "0", the synchronizing signal is detected.

Although the synchronizing signal has 56 bits, it is detected atthetiming of the 48th bit. When the synchronizing signal is detected, the counter 36 and theflip-flops40,42,44,46 and 58 are reset bythe clear pulse from the control circuit 18through the signal line 18b. The signal lines 16a, 16b, 16cand 16efall or go to logic level "0", and theAGCcircuit 12 stops operating.Thereafter,theAGCcircuit 12 holds, for a time interval for receiving data of one line, the amplification factor which is determined immediately before the synchronizing signal is detected.

When the next 8-bit picture signal is received, the signal line 48a ofthe counter48 goes to logic leve as indicated by S5 in Fig. 5(k). Since the output 50a of the OR gate 50 is at logic level "1" atthistime, the signal line 16cofthe D flip-flop 58 goes to logic level "1" as indicated by S6 in Fig. (I) in synchronism with the next bittiming clock. Although the signal lines 1 6a and 1 6b are both at logic level "0" atthis time, the signal line 16d is at the level corresponding to that of the signal line 1 6b atthe timing indicated by S4 in Fig.

5 (I).Thus,the signal line 16d is atlogiclevel "1", indicating that the guard band signal is received. The control circuit 18 does not store any data in the double buffer memory 26. As has been mentioned earlier, the guard band signal is included so asto eliminate any adverse effect ofthe ringing of the trailing edge of a synchronizing signal on the subsequent picture signal. Since the synchronizing and the skip signals have high level, ringing also has a great amplitude. The effect of inclusion of a guard band signal is significant.

Reception ofthe next signal is initiated. As indi cated by S7 in Fig. 5(d), a high level signal is detected.

When the high level continues for a duration of 384 us, the D flip-flop 42 is set as indicated by S8 in Fig.

5(h). When the black signal level or black dot is subsequently detected as indicated by S9 in Fig. 5(e), the D flip-flop 44 is set, and the signal line 1 6b goes to logic level "1" as indicated by S10 in Fig. 10(j). Then, the output 50a ofthe OR gate 50 goes to logic level "1 ". When the signal line 48 goes to logic level "1" at the next byte timing, that is, as indicated by 511 in Fig.

5(k),thesignal line 54a connected to the input end of the Dflip-flop 58 goes to logic level "1" through the AND gate 52 and the OR gate 54. Therefore, the flip-flop 58 is set by the next bittiming clock supplied through the signal line 22a,andthe signal line 16c goes to logic level "1" as indicated by S12 in Fig. 5(1).

Since the signal lines 1 6a, 16b and 16d are respectively at logic levels "0", "1" and "0",the received signal is discriminated to be a skip signal In this case,the control circuit 18 serves to write one block of the white signal,that is,the 64-bitwhite signal data. Ion a similar manner, a skip signal corresponding to the second block and a guard band signal are detected at timings indicated by S13 and S14, respectively, in Fig.

5(I). A picture signal corresponding to the third block is then received. The first image transmission method hasthus been described. When the line status or circuit characteristics are bad during transmission in accordance with the first image transmission method as described above, the receiver is subject to various errors.Such errors include an error in which a skip signal from the transmitter is detected as a picture signal (to be referred to as a skip signal < picture signal error); an error in which a picture signal transmitted from the transmitter is detected as a skip signal (to be referred to as a picture signal < skip signal error); an error in which a skip signal from the transmitter cannot be received ata propertiming due to an incorrect timing of detection of the black signal level; a blackghosterrorwhich is caused by ringing when a skip signal is followed by a picture signal; a white balance error by ringing; and soon.The image disturbance due to such errors will be described with reference to attenuation distortion and group delay distortion which are two important factors accounting for line or circuit characteristics.

Attenuation distortion means thatthe amount of attenuation of a transmission line is not uniform within a voice range (300 Hzto 3.4kHz). The image disturbance by attenuation distortion will first be described. Fig. 6A shows a typical characteristic curveAofattenuation distortion, and Fig. 6(b) shows a characteristic curve B having the opposite characteristic. In Fig. 6, frequency is plotted along the axis of abscissa while attenuation amount is plotted along the axis of ordinate. In accordance with the character istic curve A shown in Fig. 6A, the attenuation decreases with an increase in thefrequency; this characteristic is called overequalization characteristic. In accordance with the characteristic curve B shown in Fig. 6, the attenuation increases with an increase in the frequency; this characteristic is called underequalization characteristic.

Figs. 7(a) and 8(a) show a signal block; Figs. 7(b) and 8(b) show a waveform without attenuation distortion; Figs. 7(c) and 8(c) show a waveform having the characteristic curve B or the undere qualization characteristic shown in Fig. 6(b); and Figs.

7(d) and 8(d) show a waveform having the characteristic curve A orthe overequalization characteristic shown in Fig. 6A.

Thus, Figs. 7(c), 7(d), 8(c) and 8(d) showthe received signal waveform (signal line 1 4a) when the line characteristic is subject to attenuation distortion.

Assume nowthatthefrequency ofthe main componentofthesynchronizing signal is lowerthan that of the skip signal.

In the case ofthe overequalization characteristic shown in Fig. 6A, the duration ofthe high level signal on the signal line 30a decreases as shown in Fig. 7(d).

Thus,the high signal doesnotcontinuefor384ps.

The signal line 42a does not, therefore, go to logic level "1" to cause the skip signal , picture signal error described above. When this error is caused, the image is shifted to the leftfrom the position in units of blocks (64 picture elements).

In contrast to this, in the case ofthe underequalization characteristic, when a picture signal (including a black signal within a block) is received after a skip signal and a guard band signal, a black ghost (62) appears in a black and white image due to ringing. If the line characteristic is subject to still intense underequalization, the duration ofthe high level signal on the signal line 30a increases so thatthe high level signal continues even for a duration longerthan 384 its after the transmittertransmits the picture signal. Then, the signal line 42a is kept at the high level, causing the pictu re sig nal-+ skip sig nal error. In particular, a picture signal having a signal array similarto that ofthe skip signal is likely to be mistaken as a skip signal.In this case, the image is shifted to the rightfrom the normal position in units of blocks (62 picture elements). When the transmittertransmits a skip signal, the receiver does not have any problem during the high level signal duration ofthe skip signal. However, when the peakvalue becomes very large, fall time increases so thatthe timing of detection ofthe black signal level is delayed. Thus, an error is caused wherein the skip signal cannot be detected at a correct position.

The image disturbance by group delay distortion will now be described. A group delay distortion is caused since signal propagation speed through a transmission line differs depending upon frequency.

This group delay distortion is attributed to the non-linear relationship between frequency and phase. Fig. shows a characteristic curve C corresponding to underequalization and Fig. 9B shows a characteristic curve D corresponding to overequalization. In Fig. 9, frequency is plotted along the axis of abscissa while delaytime (ms) is plotted along the axis of ordinate. The amount of group delay is represented as a difference with respect two 2,100 Hz.

In accordance with underequalization, group delay distortion increases in low- and high-frequency ranges. In accordance with overequalization, group delay distortion decreases in low- and high-frequency ranges.

Fig. shows a signal block; Fig. IO(b)shows a signal waveform without group delay distortion; Fig.

10(c) shows a waveform of the characteristic curve C shown in Fig. 9A and corresponding to underequalization; and Fig. 10(d) shows a waveform of the characteristic curve D and corresponding to overequalization.

Figs. 10(c) and 10(d) show received signal waveforms (signal line 1 4a) when the circuit characteristics are subjectto group delay distortion. When the circuit characteristics are subject two overequalization,timing of detection of black signal level (64) is delayed so thatthe skip signal cannot be detected at the correct timing. Two types of image disturbance are caused depending upon the error position within a signal array. Figs. 11 and 12 show timing charts for explaining the operation mode of the receiver in the case of such two types of image disturbance.

Fig. 11 shows a case wherein the skip signal cannot be received at a correct position within a continuous skip signal array. When the timing of detection of black signal level is delayed as indicated by S16 in Fig.

11(c), the signal lines 16b and 42b in Fig. 4 are at logic level "0", the output 50a ofthe OR gate 50 is at logic level "0", and the signal line 16a is at logic level "0".

Therefore,thesignal line 16cdoes not go to logic level "1" as indicated by S17 in Fig. (e). Intestate indicated by S18 in Fig. (e), the signal lines 1 6c and 16b are at logic level "1 ", while the signal lines 16a and 1 6d are at logic level "0". Therefore, the receiver recognizes the input signal as a skip signal. Thus, skip signals (g and (2) are recognized as one skip signal. In this case, the image is shifted to the left from the normal position in units of blocks (64 picture elements).

Fig. 12 shows a case wherein a picture signal is received after an error of failing to receive a skip signal at a correct position is caused. When the timing of detection of the black signal level is delayed as indicated by S19 in Fig. 12(c), the signal lines 1 6b and 42b in Fig. 4 are at logic level "0", the output 50a ofthe OR gate 50 is at logic level "0", and the signal line 16a is at logic level "0". Therefore, as indicated by S20 in Fig. 12(e), the signal line 1 6c does not go to logic level "1".At the timing indicated by S21 in Fig. 12(e), the signal lines 1 6c and 1 6b are at logic level "1", and the signal lines 1 6a and 1 6d are at logic level "0".

Therefore, the receiver recognizes the received signal as a skip signal. Atthetiming indicated by S22 in Fig.

12(e), the signal lines 1 6c and 1 6d are at logic level "1",whilethesignal lines 16a and 16b are at logic level "0". Therefore, the receiver recognizes the received signal as a guard band signal; the start byte ofthe picture signal is mistaken as a guard band signal. In this case, the image is shifted to the left from the normal position in units of bytes (8 picture elements).

In the case of overequalization, as indicated by 66 in Fig. 10(d), white imbalance is caused in the black image due to the ringing ofthe leading edge of the skip signal.

In the case of underequalization, as indicated by 68 in Fig. 10(c), white imbalance is caused in the black imagedueto ringingofthetrailingedgeoftheskip signal.

In the above description, attenuation distortion and group delay distortion are considered as factors for degrading circuit characteristics. However, in an actual circuit, otherfactors must also be considered such as attenuation hump, phase hit, phase jitter, frequency deviation, and instantaneous failure. In most cases, a combination ofsomeofthesefactors must be considered to accountfor image disturb ance.

In a conventional analog high-speed facsimile system, a fixed equalizer is used for the purpose of preventing degradation in image quality as described above. However, the telephone line characteristics vary everytime a line is established. The range of such variation may encompass the characteristic curve A two the characteristic curve B in Fig. 6. For this reason, degradation due to variation in the circuit characteristics cannot be completely prevented in a conventional analog high-speed facsimile system.

In a conventional analog high-speed facsimile system of the type described above, automatic equalization function is not incorporated in order to reduce the cost. If transmission is performed through a circuit of very bad characteristics, the image quality is significantly degraded by transmission errors.

In a conventional analog facsimile system of redundancy suppression type (first imagetransmission system), when a circuit is connected thereto, a circuit status check signal is not used which is used for checking if a redundancy suppression signal from a transmitter is correctly received by a receiver. For this reason, reception state of the redundancy suppression signal can only be confirmed by confirming image disturbance at the side of the receiver.

In oneaspectthe presentinventionaimsto prevent the degradation of quality of received image such as disturbance of image by changing an image transmission method depending on a characteristic of a line.

In anotheraspectthe present invention aims to allow prediction of disturbance of a received image priorto observing the received image.

In a further aspect the present invention aims to produce a high quality of received image by select ingoneofthree image transmission methods depending on a characteristic of a line and sizes of an original and a record paper.

Figs. (a) and 1(b) show the formats of transmit ted signal which is transmitted in accordance with the first image transmission method; Figs. 2(a) to 2(c) show the formats of a synchronizing signal, a skip signal, and a guard band signal; Fig.3 is a block diagram of a receiverwhich adopts the first image transmission method; Fig. 4 is a block diagram of a signal discriminator 16; Figs. 5(a) to 5(1) are timing chartsforexplaining the mode of operation of the receiver in accordance with the first image transmission method; Figs. 6A and 6B show characteristics of attenuation distortion;; Figs. 7(a) to 7(d) and 8(a)to 8(d) show waveforms of received signal when the circuit characteristics in volveattenuation distortion (by the first image transmission method); Figs. 9A and 9B showthe characteristics of group delay distortion; Figs. 10(a) to 10(d) show waveforms of received signal when the circuit characteristics involve group delay distortion (by the first image transmission method); Figs 11 (a)to 11(e) and 12(a)to 12(e) are timing charts for explaining the mode of operation of the receiver when the error is caused wherein a skip signal is not received at a correct position (bythefirst image transmission method); Figs. 13A(a) to 13B(f) showformats of check signals which are used in accordance with the present invention;; Fig. 14 is a block diagram of a transmitterfor transmitting the check signals which is used in accordance with the present invention; Figs 15(a) to 15(d) show a memory map of a pattern generator70; Fig. 16 is a flowchart of control sequence of a control circuit 72 shown in Fig. 14; Figs. 17(a)to 17(f) are timing charts of the check signal generator shown in Fig. 14; Fig. 18 is a block diagram of a circuit for receiving check signals which is used in accordance with the present invention; Fig. 19 is a memory map of a memoryA 116; Fig. 20 is a memory map of a memory B 118;; Figs. (a) and 21 (b) are flowcharts of control sequence of a control circuit 1 14 shown in Fig. 18; Figs.22ta)to 22(c) show waveforms of black ghost check signals; Fig. 23 shows a signal flow chartfor a Gll procedure; Fig. 24 shows image information immediately before transmission in the third image transmission method; and Fig. 25 shows waveforms transmitted by the first, second and third image transmission methods.

There isthefirst image transmission method or redundancy suppression method in which a picture signal array of one scanning line is divided into blocks each consisting of N picture signals, and image transmission is performed by controlling the amount of picture date to be transmitted in accordance with the black and white data of picture signals within each block. Although this method has an advantage of high transmission speed, it has a disadvantage of image disturbance if the circuit status is not good.

Next, a second image transmission method is known in which a picture signal array of one scanning line is not divided into blocks each consisting of N picture elements. Thus, the amount of picture data to be transmitted is not controlled in accordance with the black and white data within each block. Instead, an I-bit synchronizing signal is firsttransmitted, and then picture signals are transmitted after modulation. This second image transmission method has a disadvan tage of lowtransmission speed but has an advantage that image disturbance is caused infrequently even if the circuit characteristics are not good.

On the other hand, many ofthefacsimile machines having analog high speed feature have Gil facsimile functions prescribed in T-3 ofthe CCITT Recom mendation in orderto allow the communication with the facsimile machines of other manufacturers.

In such facsimile machines having the analog high speed feature and the Gll facsimile function, it is more advantageous to check the line condition and, if it is bad, to use the third imagetransmission method described in the present invention ratherthan the second image transmission method described above.

The third image transmission method provides a better result than the second image transmission method for a line having a very low S/N ratio or a line having a very large pulsive noise. In accordance with the present invention,forthefacsimile machine having the analog high speed feature and the GII function but no automatic equalizerfunction,the line characteristic is checked prior to the transmission of the image and the transmission method is changed depending on the check result.

In accordance with the present invention, if circuit characteristics are such that image disturbance may be caused by the first image transmission method, a circuit status check signal is transmittedlreceived to determine that the circuit characteristics are not good and image disturbance may be caused iftransmission is attempted in accordance with the first image transmission method. In this case, transmission is performed in accordance with the second image transmission method.

In this manner, the disturbance ofthe received image dueto the poor line characteristic can be substantially reduced and the line disconnection can be prevented.

In an oversea line (long distance communication line), a line condition (particularly, pulsive noise condition) maychangewith time after it has been connected. Accordingly, when a plurality of original sheets are to be transmitted, the check signal is transmitted and received priorto the transmission of each ofthe original sheets to checkthe line condition and an optimum transmission method is selected depending on the check result.

The present invention is now explained in detail in conjunction with preferred embodiments thereof.

Fig. l3showsaformatofachecksignal which checks a line condition to determined whether an original isto betransmitted bythefirst image transmission method which uses a skip signal to instruct skip of white information groups, or by the second image transmission method in which all picture cell signals are modulated and transmitted without skipping or by the third image transmission method.

Fig. 13A(a) shows the overall format ofthe check signals. Referring to Fig. 13A(a), Eisa signal having a frequency of 2,100he and for controlling a PLL circuit and an AGC circuit. Sixteen synchronizing signals include 16 signals each having a 46-bit high level signal duration and a 5-bit black signal level duration, and then include a 5-bitwhitesignal level duration.

The same applies to 6 synchronizing signals and 10 synchronizing signals in Fig. 1 3A(a). A skip check signal in Fig. 13A(a) is shown in Fig. 13A(c),whilea black ghost check signal in Fig. 13A(a) is shown in Fig.

13B(e). Four hundred ninety six skip signals in Fig.

13A(c) include 496 signals each having a 6-bit high level signal duration and a 2-bit black signal level duration. In accordance with an example ofthe black ghost check signal shown in Fig. 1 3B(e), as shown in Fig. 1 3B(f), 8 signals are generated in each of which a skip signal (having a 6-bit high level signal duration and a 2-bit black signal level duration) is followed by a guard band signal (having a 3-bit black signal level duration and a 5-bit white signal level duration), a 32-bit white signal level duration and a 32-bit black signal level.

Fig. shows a block diagram for transmitting circuit status check signals which are used in accordance with the facsimile system ofthe present invention. Referring to Fig. 14,ascannerunit67 converts optical image data read outfrom an original (not shown) into electrical image signals. An image processor 68 receives image signals from the scanner unit 67 and generates transmission signalsforthe first image transmission method orforthe second image transmission method.

A multiplexer 69 selects the signals from the image processor 68 or from a pattern generator70 to be described later and supplies the selected signals to a byte buffer 76 which will also be described later. The scanner unit 67 and the image processor68 are mainly concerned with processing of the image signals which are read outfrom the original. The circuit for generating the circuitstatus check signals in accordance with the present invention will now be described.

Referring to 14,the byte buffer 76 serves to latch an 8-bit parallel signal received through a signal line 70d in response to a clock pulse (byte timing clock) received through a signal line 84a, and sequentially produces the latched signal in units of bits in response to a bit timing clock received through a signal line 74a. The byte buffer76 comprises a parallel in/serial outshiftregisterorthelikeand seriallytransmits the 8-bit signal from its LSB toward the more significant bits.

The gain of a variable gain amplifier78 is changed in accordance with the logic level of a signal line 82a.

If the signal line 82a is at logic level "1 ",the gain is 2. If the signal line 82a is at logic level "0", the gain is 1.

The amplified signal from the variable gain amplifier 78 is produced onto a signal line 78a.

An AM - PM - VSB modulator 80 is of the known configuration and will now be described in detail. In the modulator 80, the signal received through the signal line 78a is band-limited by a suitable low-pass filter (LPF) sothat undesirablefoldover noise may be eliminated. Then,the signal is AM - PM -VSB modulated, and is transmitted through an NCU (network control unit; not shown).

Atiming pulse generating circuit 74 generates two types oftiming pulses which are used in the transmitter. A bittiming clock having a frequency of, for example,7,740 appears on the signal line 74a and is applied tothe byte buffer76 and a delay element 82. Since transmission data is transmitted in response to this bit timing data,thetransmission speed is 7,740 bps. Abytetiming clockwhich is obtained byfrequency-dividing the bit timing clock by 8 appears on the signal line 74b and is applied to the pattern generator70, a control circuit 72 and a delay element 84. The byte timing clock has a frequency of 7740/8=967.5 Hz.

The delay element 82 comprises a flip-flop orthe like. The delay element 82 delays the signal received through a signal line 70b by a delaytime corresponding to one period ofthe bit timing clock received through the signal line 74a. The delayed signal is produced onto a signal line 82a.

The delay element 84 serves to produce onto a signal line 84a a byte timing clockwhich is obtained bydelayingthebytetiming clockfromthetiming pulse generating circuit 74 received through the signal line 74b buy a predetermined period of time (corresponding to halfthe period of the bittiming clock from the timing pulse generating circuit 74). The delayed clock serves as a pulse for latching the 8-bit parallel signal in the byte buffer76.

The pattern generator 70 comprises an ROM (Read-Only Memory) of 10x124 bits and an address pointer. Fig. 15 shows a memory map of the pattern generator. Ten-bit data is produced in corresponding with each of O to 123 addresses. The 10-bit data is produced ontothesignal line70c,the ninth bit data from the LSB is produced onto the signal line 70b, and the LSB to the 8th bit data is produced onto a signal line 70a.

The gain ofthe 8-bit data which is latched in the byte buffer 76th rough the signal lines 70a and 70d and is sequentially produced in response to the bit timing clocks is determined in accordance with the signal on the signal line70b. The signal on the signal line 70b is supplied to thevariable gain amplifier78 through the delay element 82. The circuit status check signals are transmitted by setting the address pointer to 0, and by producing onto the signal lines 70a, 70b and 70cthe current address data ofthe address pointer each time it receives the byte timing clock through the signal line 74b. The address pointer is increased upon reception of the pulse from the control circuit 72.

When one pulse is generated on a signal line 72a, the address pointer is incremented by 1. The address pointer is set to O in the initial state.

As has been described earlier, the control circuit 72 controls the address pointer ofthe pattern generator 70. An example will be described in which sequence control is performed utilizing a microprocessor. In the initial state, the address pointer ofthe pattern generator70 is setto 0, andthe content ofthe B register is set to 1. In accordancewith the main control operation of the control circuit 72, when a byte timing clock is generated on the signal line 74b, the signal on the signal line 70c is received so asto enterthe data of the current address pointed by the address pointer. Note that the data entered through the signal line 70c is such that a 10-bit output may be produced from the ROM described above.Utilising the data received through the signal line 70c,the control circuit 72 performs control ofthe holding period ofthe address pointer according to which the same data is produced onto the signal lines 70a and 70b of the pattern generator 70 in response to reception of further byte timing clocks.

The control sequence of the control circuit72 is shown in Fig. 16. In step 85 in Fig. 16, initialization is performed; 1 is entered in the B register. In step 86, it is discriminated if a pulse is generated on the signal line 74b, that is, if a byte timing clock is generated. If YES in step 86, the content ofthe B register is decremented by 1 in step 88. It is then discriminated in step 90 ifthe content ofthe B register O. If NO in step 90, it is then discriminated in step 91 if the content ofthe B register is 1. If YES instep 91, a pulse is generated on the signal line 72a to advancethe address pointer by 1 in step 92.If YES in step 90, the signal is entered on the signal line 70c in step 94; the address data currently pointed by the address pointer is entered. In step 96, it is discriminated ifthe input data on the signal I I ine 70e is 1 FFH. If YES in step 96,5 is entered in the B register in step 106. On the other hand, if NO in step 96, it is discriminated in step 98 if the input data on the signal line 7Oc is FFH. If YES in step 98,4 is entered in the B register in step 112. If NO in step 98, and if YES in step 102 or 104,1 is entered in the B register step 110. In step 11 1,a pulse is generated in the signal line 72a so as to advance the address pointer by 1.If NO in all of steps 96to 104,4 is entered in step 112.

Acasewill be described in which the address pointer is setto 0 and a synchronizing signal is transmitted. The discrimination of step 86 is repeated until a pulse is generated on the signal line 74b. When the pulse is finally generated on the signal line 74 and YES is obtained in step 86, the content of the B register is decremented by 1 to O in step 88. Thus YES is obtained in step 90. When the data is entered on the signal line 70coin step 94, the data is 1 FFH. Atthistime, a signal of logic level "1" is produced onto the signal line 70b and "FFH" (8-bit high level signal) is produced on the signal line 70a bythe pattern generator70. Since the data on the signal line 1 FFH, YES is obtained in step 96, and 5 is entered in the B register in step 106.When the second byte timing clock is generated, the content of the B register is changed to 4. Thereafter, the content of the B register is decremented to 3 upon generation of the third byte timing clock, is decrementedto 2 upon generation of thefourth byte timing clock, and is decremented to 1 upon generation ofthe fifth byte timing clock ("1 " is produced on the signal line 70b and "FFH" is produced on the signal line 70a when the second to fifth byte timing clocks are generated). At this time, YES is obtained in step 91, and the addresss pointer is advanced to 1 in step 92. When another byte timing clock is generated, the content ofthe B register its0, and YES is obtained in step 90.When the data is entered on the signal line 70c in step 94, the data on the signal line 70e is 1 3FH. At this time, "1" is produced on the signal line 70b and "3FH" is produced on the signal line 70a bythe pattern generator 70. Since the data on the signal line70c is 13FH, YES is obtained in step 102, and 1 is entered in the B register in step 110. The address pointer is advanced by 1 to 2 in step 111.Asignal which is transmitted when the addresss pointer changes from Oto 1 is considered; data 1 FFH is transmitted five times and 13FH is su bsequentlytransmitted once.

Since the ninth bit from the LSB is "1" in each case, a high level signal is transmitted. Sincethe8-bitdata is sequentially transmitted from the LSB by the byte buffer76,46 bits ofthe high level signal and 2 bits of the black signal signal are sequentiallytransmitted.

This corresponds to one synchronizing signal as shown in Fig. 13A(b). Thereafter, all the check signals are transmitted onto the circuit in a similar mannerto that described above.

Fig. 17 shows timing charts ofthe signals gener ated by the check signal generating circuit; two synchronizing signals are transmitted. The signal appearing on the signal line 78a ofthevariable gain amplifier 78 is a transmitted base band signal having the waveform shown in Fig. 17(a). In the initial state, the address pointer is setto (Fig. 17(f)). In response to a byte timing clock K1 on the signal line 74b shown in Fig. 17(c), "FFH" is produced on the signal line 70a and "1" is produced on the signal line 70b. Thus, the content ofthe byte buffer 76 is FFH as shown in Fig.

17(d),whilethe gain control signal hasalogiclevel "1" as shown in Fig. 17(e). Thus, an 8-bit signal of logic level "1" is produced as a transmission binary signal (signal line 76a) as shown in Fig. 17(b), and an 8-bit signal of high level is produced as an amplifier output (signal line 78a) as shown in Fig. 17(a). The same operation as that upon reception ofthe byte timing clock K1 is performed for each of byte timing clocks K2, K3, K4 and K5. When the byte timing clock K5 is generated on the signal line 74b, the address pointer changes from 0 to 1.When the next byte timing clock K6 is generated, 3FH is produced on the signal line 70a, while 1 is produced on the signal line 70b. As shown in Fig. 17(b), the content ofthe byte buffer76 becomes 3FH, while the gain control signal goes to logic level "0" as shown in Fig. 17(e). Thus, as a transmission binary signal (signal line 76a) is generated as in Fig. 17(b) a 6-bit signal of logic level "1" and a 2-bit signal of logic level of "O". As shown in Fig. 17(a), as an amplifier output (signal line 78a) is generated a 6-bit high level signal and a 2-bit black level signal.When the byte timing clock K6 is generated on the signal line 74b, the address pointer changes from 1 to 2. The same operation as that performed upon reception of the byte timing clocks K1, K2, K3, K4and K5 is performed upon reception of byte timing clocks K7, K8, K9, K1 0 and Ki 1. When the byte timing clock K11 is generated on the signal line 74b,the address pointer changes from 2to 3. When the byte timing clock K12 is generated on the signal line 74b,the same operation asthat performed upon reception ofthe byte timing clock K6 is performed.

Further, check signals are produced on the circuit in a similar manner.

The mode of operation for generating the circuit status check signals used in the present invention will now be described in more detail.

Fig.18showsa blockdiagram of a circuitfor generating circuitstatus check signals which is substantially the same as that shown in Fig. 3. Thus, the circuit shown in Fig. 18 differs from that shown in Fig. 3 in that the printer20 and the buffer memory 26 are omitted, and a control circuit 114, a memory A 116, and a memory B 118 are added in the circuit shown in Fig. 18. The memory A 116 comprises an 8 x 7-bit RAM (Random Access Memory).

Fig. 19 shows a memory map of the memory A 116.

Referring to Fig. 19, the memoryA 116 has 1-byte memory areas for CNTSY1 (count sync), CNTPIX (count pix), CNTGRD (count guard), CNTSY2 (count sync), and CHKPTR (check pointer); and a 2-byte memory area forCNTSKP (count skip). These memory areas respectively count synchronizing signals (sync), picture signals (pix), guard band signals (guard), and skip signals (skip).

The memory B 118 comprises an 8x 100-bit RAM or the like. Fig. 20 shows the memory map ofthe memory B 118. As shown in Fig. 20, the memory B 118 has memory addresses (a to 99.

The control circuit 114 receives the check signals generated by the transmitter, and stores the reception results of the skip check signal in the memory A and the reception result of the black ghost check signal in the memory B.

As in the case of the control circuit 18 shown in Fig.

3, the control circuit 114 produces a clear pulse onto a signal line 114e upon reception ofthe data for discriminating the synchronizing signal, the skip signal,the guard band signal and the picture signal from the signal discriminator 16through the input signals 16a, 16b, 16cand 16d. In response to this clear pulse, the counter36 and the flip-flops 40, 42, 44, 46 and 58 are cleared. The control circuit 114 performs control ofthe memories A 116 and B 118.In the initial state, the control circuit 114 sets the contents ofthe memory areas CNTSY1, CNTPIX, CNTGRD, CNTSKP, CNTSY2, and CHKPTR ofthe memory All 6to -28,0, -4, -1984, -7, and 0; and also sets the contents of 8 x 100 bits ofthe memory B 1 18to FFH (8-bit signal of high level). The control circuit 114 recognizes recep tionofoneofthesynchronizing signal,theskip signal,the guard band signal, and the picture signal when the signal line 1 6c rises from logic level "0" to logic leve "1".When the signal line 1 6c goes to logic level "1", the control circuit 114fetchesthe levels of the signal lines 16a, and 16d to discriminate among the cases 1) reception of a synchronizing signal (signal line 1 6a goes to logic level "1" in this case), 2) reception of a skip signal (the signal line 1 6a is at logic level "0" and the signal line 1 6b is at logic level 16b),3) reception of a guard band signal (the signal lines 1 6a and 1 6b are at logic level "0", and the signal line 1 6d is at logic level "1"), and 4) reception of a picture signal (the signal lines 16a, 16b and 1 6d are at logic level "0"). Ifthe synchronizing signal is received, the content of the memory area CNTSY1 is incremented by 1. If skip signal is received, the content ofthe memory area CNTSKP is incremented by 1. If guard band signal is received, the content of the memory area CNTGRD is incremented by 1. If the picture signal is received, the content ofthe memory area CNTPIX is incremented by 1. The contents ofthe memory areas CNTSY1, CNTSKP, CNTGRD and CNTPIX may be respectively in cremented by 1 by fetching the current contents through a signal line 1 16a and producing in cremented results through the signal line 11 4a. This operation is performed while the content ofthe memory area CNTSY1 is negative. When the content of the memory area CNTSY1 is no longer negative, the following control sequence is performed.

When the signal line 16c goes to logic level "1",the signal on the signal line 1 6a is fetched to determine if a synchronizing signal or a skip signal is received. If a synchronizing signal is received, the content ofthe memory area CNTSY2 is incremented by 1. If a signal otherthan the synchronizing signal is received, the data produced on the signal line 24a is stored in the memory B. The memory B 116 is addressed bythe content of the memory area CHKPTR is this case.

When the synchronizing signal is received, after the data is stored in the memory B 118, the content ofthe memory area CHKPTR is incremented by 1. The above operation is performed if the content of the memory area CNTSY2 is negative. Reception ofthe check signals is completed when the content ofthe memory area CNTSY2 is no longer negative.

Fig. 21 shows the control flow ofthe control circuit 114 described above. In step 120, it is discriminated if the signal line 16e is at logic level "1", that is, if one signal discrimination operation is completed. If YES in step 120, it is then discriminated in step 122 if the signal line 16a is at logic level "1", that is, if a synchronizing signal is received. If YES in step 122, the content ofthe memory area CNTSY1 is incremented by 1 in step 124. It is then discriminated in step 126 ifthe content of the memory area CNTSY1 is negative, that is, if reception ofthe skip signal is completed. If NO in step 126, the flow jumps to the top of Fig.21(b) in step 128to perform reception of a black ghost check signal.If YES in step 126, the flow returns to step 120. If in step 122 the signal line 1 6a is at logic level "0", that is, the synchronizing signal is not received, it is then discriminated in step 130 if the signal line 1 6b is at logic level "1", that is, if a skip signal is received. If YES in step 130, the content ofthe memory area CNTSKP is incremented by 1 in step 132 and thereafter the flow returns to step 120. However, if NO in step 130, that is, if the skip signal is not received, it is discriminated in step 134 if the signal line 1 6d is at logic level "1", that is, if a guard band signal is received. If YES in step 134, the content ofthe memory area CNTGRD is incremented by 1 in step 136 and the flow returns to step 120.If NO in step 134, that is, if the picture signal is received, the content of the memory area CNTPIX is incremented by 1 in step 138 and the flowthen returns to step 120. The above operation is repeated until the content of the memory area CNTSY1 is no longer negative. The content ofthe memoryareaCNTSY1 is no longernegative,thatis, it is zero after 28 synchronizing signals are recieved.

The check signals have the formats as shown in Fig.

13. After a signal having a frequency of 2,100Hz is received, 16 synchronizing signals are received.

During subsequent reception ofthe skip signal, 9 synchronizing signals are received. Six synchronizing signals are received between the skip check signal and the black ghost check signal. When 3 synchronizing signals are received between the skip check signal and the black ghost signal, the content of the memory area CNTSY1 becomes zero. When the content of the memory area CNTSY1 becomes zero, the control flow goes to the top in Fig. (b). Thus, the skip check signal is received underthe control the flow of which is shown in Fig. 21(a). The reception result is stored in the memory A 116. The black ghost check signal is received underthe control the flow of which is shown in Fig. (b), and the reception result is stored in the memory B 118.If the check signals are correctly received, the contents of all the memory areas CNTSY1, CNTSKP, CNTGRD and CNTPIX are zero.

This means that 1984 skip signals, 4 guard band signals and no picture signal are received when 28 synchronizing signals are received.

The flowchart shown in Fig. (b) will now be described. In step 140 in Fig. 21(b), it is discriminated if the signal line 16c is at logic level "1", that is, if one signal discrimination operation is completed. If YES in step 140, it isthen discriminated in step 142 if the signal line 16a isatlogiclevel "1 ",that is, a synchronizing signal is received. If YES in step 142, the content ofthe memory area CNTSY2 is incremented by 1 in step 144.It is discriminated in step 146 if the content of the memory area CNTSY2is negative, that is, if the reception ofthe checksignals is completed. lithe reception ofthe check signals is not completed yet or YES in step 146, the flow returns to step 140. If NO in step 146, discrimination of end of reception ofthe black ghost check signal is performed in step 148.This is performed bycountingthe number of black dots in the 3-byte black and white data after the guard band signal. Ifthe reception is being performed normally, no black dot is detected. If the signal line 16a is at logic !evel "O" or NO in step 142, that is, the synchronizing signal is not received, the data produced on the signal line 24a is stored in the memory B.The memory B is addressed by the content ofthe memory area CHKPTR. In step 152, the contentofthe memory area CHKPTR is incremented byl.

In this manner, reception ofthechecksignals transmitted by the transmitter is completed.

The second image transmission method is now briefly explained. The following change is made to the first image transmission method. In the facsimile transmitter, one scan line of picture cell signal sequence is not divided into blocks each consisting of the predetermined number (N) of picture cell signals, that is,the quantity of image transmission is not controlled in accordance with the white and black information but all ofthe picture cell signals are modulated and transmitted. Since they are not divided into blocks, no skip signal is sent.In the facsimile receiver, the control circuit 18 of Fig. 3 does not receive the signal 16b from the signal discriminating circuit 16 but discriminatesthe synchronizing signal, the guard signal orthe image signal as shown in Table 2 in thefirstsignal discrimination. The delay circuit 56 of Fig. 4 receives the signal 1 6a instead of the signal 16b. Sincethefacsimiletransmitterdoes not send the skip signal, the skip signal is not discriminated.

Table 2

s 16c 16a 16d Signal 1 1 x Sync. Signal 1 0 1 Guard Signal 1 0 O Image Signal One of causes of an error in which the receiver regardsthe skip signal sentfromthetransmitteras the image signal is that a high level duration is short, that is, 384 Ii seconds. It may be possible thatthe format of the skip signal may be slightly modified (for example, high level duration is doubled) and transmitted instead of switching the image transmission method from the first method to the second method when itis not possibletotransmitthe original bythe first method.

The third image transmission method is now explained. The third image transmission method usestheimagetransmission method in the Gll facsimile machine defined by CCITTT3 Recommendation. A difference resides in the phase matching and the determination of the sub-scan line density.

The phase matching is first explained. Fig. 23 shows a procedure in the Gll facsimile machine defined by the CCITTT3 Recommendation. In Fig. 23, numeral 154 denotes a called equipment identification signal CED which indicates thatthe called equipment is a non-audio terminal. Numeral 156 denotes a Gll identification signal G12 which indicates that the equipment is ready to receive original information and can receive at least one sheet of original of size A4 ofJlS by the communication system recommended to the facsimile Gll machine.

Numeral 158 denotes a Gll command signal GC2 which indicates that the transmitter is the communication system recommended to the Gll machine. Numeral 160 denotes a transmission line control signal LCS which has a function to allow the receivertoequalizethetransmission line. This signal is optional. Numeral 162 denotes a phase signal PHS for matching phases ofthetransmitterand the receiver. Numeral 164 denotes a ready for reception signal CFR 2which indicates that the receiver has completed the phase matching and is ready to receive the original image. Numeral 166 denotes image information ofthe original.

As shown in Fig. 23, the Gll facsimile machine defined by the CCITTT3 Recommendation matches the phases ofthe transmitter and the receiver by the phase signal PHS sent from the transmitter.

Inthethird imagetransmittermethod,the phase matching is not carried out in the procedure but effected immediately before the transmission ofthe image information. If the transmission of the original by the third image transmission method is decided in the pre-procedure including the line condition check, it is not necessaryto send the signal PHS for six seconds for phase synchronization, because the recent facsimile machine matches the phases not mechanically but electrically.

Fig. 24 shows a signal immediately before the image information is transmitted inthethird image transmission method. In Fig. 24, numeral 168 denotes a 2100 Hz signal sentto adjust an automatic gain control circuit (AGC) and a phase locked loop circuit (PLL)of the receiver. Numeral 170 denotes a phase signal PHASING for matching the phases of the transmitter and the receiver. Numeral 172 denotes a 2100 he signal sent to give a timing forthe receiverto shift from the phase signal reception modetothe image information reception mode. Numeral 174 denotes original image signal.

As shown in Fig. 24, in the third image transmission method, the phases of the transmitter and the receiver are matched bythe phase signal PHASING transmitted immediately before the transmission of the image information.

The determination of the sub-scan line density is next explained. In the Gll facsimile machine defined bytheCClTTT3 Recommendation, the sub-scan line density is 3.85 lines/mm. In the third image transmission method, if the mode on the panel isthestandard mode, the sub-scan line density is set to 3.85 lines/mm,and if the modeonthe panel isthefine mode, the sub-scan line density is setto 7.7 lines/mm.

The sub-scan line density of 7.7 lines/mm can be readily attained by reducing the paperfeed speeds of a stepping motor of a read unit and a stepping motor of a record unit to one halves of those for the sub-scan line densityof 3.85 lines/mm. Thethird image transmission method is advantageous because the phase matching is faster than by the Gll machine and the fine mode can be used.

The method for receiving the check signal sent from thetransmitter, the second image transmission method and the third image transmission method have been described. Based on the result of the reception of the check signal sent by the transmitter, it is determined whether the original image isto be transmitted in the first image transmission method, the second image transmission method or the third image transmission method. Whether the original imageisto betransmitted inthesecond image transmission method orthethird image transmission method is determined by the size ofthe original sheet loaded in the transmitter and the size of the record paper loaded in the receiver.

Thefirst image transmission method, the second image transmission method orthethird image transmission method is determined by the result of the reception of the check signal in accordance with a Table 3.

Table 3

Skip check signal Tr Black ghost check Si nal 1st image transmission o o method 2nd image o x transmission method or x o 3rd image transmission x x method Forthe skip check signal and the black ghost check signal, the states of o(good) and x(non-good) are determined.

As shown in table 3, if the results of the determination forthe skip check signal and the black ghost check signal are o, the original image is transmitted by the first image transmission method, and if at least one ofthe check resultsforthe skip check signal and the black ghost signal is x, the original image is transmitted in the second imagetransmission method orthethird image transmission method.

A skip check signal is a signal for mainly detecting the skip signal e picture signal error and an error wherein a skip signal is not received at a correct position due to delayed timing ofthe black dot, when the original image is transmitted in accordance with the first image transmission method. Atwo-alterna tive discrimination of o orx is performed for the skip check signal. The discrimination algorithm will now be described. o indicates reproduction of 496 x 4 skip signals; the content of the memory area CNTSKP of the memoryA 116 iszero.x indicates non-reproduction of 496 x 4skip signals; the content of the memory area CNTSKP ofthe memory A 116 is not zero.

A black ghost check signal is a signal for mainly detecting black ghost generation in a white image by ringing when the original image is transmitted in accordance with the first image transmission method. lf the circuit has the characteristic curve B, that is, underequalization, a picture signal < skip signal error may also be caused. This error is always accompanied with the black ghost in a white image by ringing. Atwo-alternative discrimination of o and xis performed for a black ghost check signal, as has been described above. Fig. 22 shows a part of a black ghost check signal. A black ghost check signal includes 8 signals as shown in Fig. 22. Fig. 22(a) shows a transmitted base band signal, while Figs. 22(b) and 22(c) show received base band signals.As indicated by P1 in Fig. 22(b) and by P2 in Fig. 22(c), it is checked how many black dots are generated in a 3-byte white signal level duration. Fig. 22(b) shows a case wherein no black dot is generated in a 3-byte white signal level duration, and Fig. 22(c) shows a case wherein a black dot is generated in a3-bytewhitesignal level duration as indicated by P3. Since the signal as shown in Fig.

22 is generated 8 times as a black ghost check signal, it isthus checked how many black dots are generated within 3 x 8 = 24 byte of white signal level duration.

If at least one of the check results forthe skip check signal orthe black ghost check signal is x as a result of the transmission and the reception ofthe line check signal,the original image is transmitted either in the second image transmission method or in the third image transmission method, as determined in the following manner.

The original image is transmitted in the second image transmission method only when the size of the original in the transmitter is B4 and the size of the record paper in the receiver is B4.

When the size of the original in the transmitter is A4 and the size ofthe record paper in the receiver is A4, when the size of the original in the transmitter is A4 and the size ofthe record paper in the receiver is 84, and when the size ofthe original in the transmitter is B4 and the size ofthe original in the receiver is A4, the original imageistransmitted inthethird image transmission method.

Thus, the receiver receives the check signal sent from thetransmitter and can identify whether it is to transmit the original image in the first image trans mission method or it isto transmitthe original image inthesecondorthirdimagetransmission method.

The selection of one ofthethree imagetransmission methods must be done beforethetransmission ofthe original image, that is, in the pre-procedure.The pre-procedure is done by using a tonal signal not defined in the CClTTT30.

If line condition is bad as a result of the line condition check, the second image transmission method is selected when the size ofthe original in the transmitter is B4 and the size ofthe record paper in the receiver is 84. In the present embodiment, the third image transmission method uses the image transmission method in the Gll facsimile machine defined by the CCITTT3 Recommendation. When the size ofthe original in the transmitter is B4 and the size of the record paper in the receiver is 84, the following mode can betaken by modifying the transmitting and receiving clocksforthe image information. Namely, if the line condition is bad,thethird image transmission method is selected.

Fig. 25 shows waveforms when the image signal is transmitted in the first, second and third image transmission methods. Fig. 25(a) shows an image signal to be transmitted, Fig. 25(b) shows a waveform when the image signal is transmitted in the first image transmission method, Fig. 25(c) shows a waveform when the image signal is transmitted in the second image transmission method, and Fig. 25(d) shows a waveform when the image signal is transmitted in the third image transmission method. To compare Fig. 25(c) with Fig. 25(d), the image signal level in Fig. 25(d) is two times as high as that of Fig.

25(c). Thus, forthe line having a very low S/N ratio, the third image transmission method is more advantageous than the second image transmission method. Since the second image transmission method is oftransmission synchronization type, it is more affected by a pulsive noise between synchronizing signals than the third image transmission method with is of independent synchronization type.

As described above, the third image transmission method utilizes the Gll function. It istherefore effective to only the size A4 recording. It is possible to modifythe hardware to enable the B4equi-scale transmisson inthethird imagetransmission method but it is not effective because of increase of cost.

Accordingly, the B4equi-scaletransmission is done in the second image transmission method.

The present invention is thus proposed to the case where the analog high speed transmission is selected in the facsimile machine having the analog high speed feature and the Gll function. Even if the automaticequalizerfunction is not equipped, the line characteristic is checked priorto the image transmission and the transmission method is selected depending on the check result so thatthe degradation of the quality of the received image due to the bad line characteristic can be substantially reduced over the prior art analog high speed machine.

As described hereinabove, according to the present invention,there is provided an analog high speed fascimile machine in which the line condition is checked priortothe image transmission and an optimum image transmission method is selected depending on the check result and which is easy to usefor a user.More particularly, one ofthefollowing imagetransmission methods is selected to transmit the original image: (1) The first image transmission method in which one scan line of picture cell signal sequence is divided into blocks each consisting of N picture all signals and the quantity of image transmission is controlled in accordance with the white and black information of the picture cell signals in each block more specifically, the l-bitsynchronizing signal is sent priorto the transmission of each scan line of image and if the block includes black information (first block), N image signals are modulated and sent out, and ifthe block includes all-white information (second block), the n-bit skip signal (n < N) is modulated and sent out, and if the block immediately before the first block to be transmitted was the second block, them-bit guard signal is modulated and sent out.

(2) The second image transmission method in which one scan line of picture cell signal sequence is not divided into blocks each consisting of N picture cell signals, that is, the quantity of image transmission isnotcontrolled bythewhiteand black information butthe I-bit synchronizing signal is sent out priorto the transmission of each scan line of image cell signals and then all ofthe image cell signals are modulated and sent out.

(3) The third image transmission method which utilizes the image transmission method in the Gll facsimile machine defined in the CCITTT3 Recommendation (although the phasing and the determination of the sub-scan line density are different).

The line condition is checked bythe transmission and the reception ofthe check signal and if it is determined that the distortion of image will result in thefirstimagetransmission method,the second or third image transmission method is selected depend ing on the size of the original in the transmitter and the size of the record paper in the receiver. By the present image transmission system, the distortion of image is prevented. In summary', the adaptability of the analog high speed facsmile machine to the bad line condition is substantially improved. In the oversea line (long distance line), the line condition (particularly pulsive noise) changes with time after the line has been connected. Accordingly, when a plurality of original sheets are to betransmitted,the check signal is transmitted and received priortothe transmission of each original to checkthe line condition so thatthe optimum transmission method is selected each time depending on the check result.

Claims

1. Afacsimile machine comprising: meansfortransmitting and receiving a check signal of a predetermined image pattern prior to transmission ofimage information read from an original; and control means for selecting, after checking of a line condition by said check signal, one of a first image transmission method in which a skip signal for instructing skip is transmitted and received in accord ancewith white information read from said original, a second image transmission method in which said skip signal is nottransmitted and a third image transmission method in which phasing is effected immediately before the transmission of the image information.

2. Afacsimile machine according to Claim 1 wherein said first image transmission method divides one scan line of picture cell signal sequence read from said original into blocks each consisting of N picture cell signals and controls the quantity of information transmission in accordance with white or black information contained in the picture cell signals in each block, said second and third image transmission methods do not divide one scan line of picture cell signal sequence read from said original into blocks each consisting of N picture cell signals and do not control the quantity of information transmission but modulate and transmit all ofthe white and black picture cell signals in the scan line, and said control means selects said second image transmission method in which a level ofthe white picture cell signal is lowerthan a high level of a synchronizing signal when both of a size ofsaid original in a transmitter and a size of a record paper in a receiver are first size, and selects said third image transmission method in which the level of the white picture cell signal is substantially equal to the high level ofthe synchronizing signal when both ofthe size of said original in the transmitter and the size ofthe record paper in the receiver are second size.

3. Afacsimile machine according to Claim f or2 wherein said check signal comprises a synchronizing signal, a skip check signal having a predetermined number of repetition of alternative combination of a skip signal and the synchronizing signal and a black ghost signal having a predetermined number of repetition of signal block consistng ofthe skip signal, a white information signal and a black information signal.

4. Afacsimile machine comprising: control means for receiving a check signal including a synchronizing signal, a skip signal and a black ghost signal priorto reception of an image signal read from an original and selecting, in accordance with a reception condition of said check signal, a reception mode of said image signal to either a first image transmission method or second or third image transmission method, and selecting, in accordance with a size of said original and a size of a record paper, the reception mode of said image signal to either said second image transmission method or said third image transmission method; first memory means for receiving said skip check signal from said control means and storing therein and then outputting the stored skip check signal to said control means; and second memory means for receiving said black ghostchecksignalfrom said control means and storing therein and then outputting the stored signal to said control means.

5. Afacsimile machine according to Claim 4 wherein said control means selects said first image transmission method when a predetermined number of said skip check signals are reproduced and a predetermined information is not included in said black ghost signal, and selects said second orthird image transmission method when the predetermined numberofsaid skip check signals are not reproduced and/orlessthan a predetermined numberofthe predetermined information are included in said black ghost check signal, and said control means selects said second image transmission method in which a level of a white picture cell signal is lowerthan a high level ofthe synchronizing signal when both of the size of said original and the size of said record paper are first size, and selects said third image transmission method in which the level of the white picture cell signal is substantially equal to the high level of the synchronizing signal and the phasing is effected immediately before thetransmission of the image information when both the size of said original and the size of said record paper are second size.

6. Afacsimile machine according to Claim 5 wherein said predetermined information in said black ghostchecksignal is black information.

7. Afacsimile machine according to Claim 5 wherein said first image transmission method divides one scan line of picture cell signal sequence read from said original into blocks each consisting of N picture cell signals and controls the quantity of information transmission in accordance with white or black information contained in the picture cell signals in each block, and said second and third image transmission methods do not divide one scan line of picture cell signal sequence read from said original into blocks each consisting of N picture cell signals and do not control the quantity of information transmission but modulate and transmit all of the white and black picture cell signals in the scan line.

8. Afacsimile machine according to ClaimS or 7 wherein said check signal comprises a synchronizing signal, a skip check signal having a predetermined number of repetition of alternative combination of a skip signal and the synchronizing signal and a black ghost signal having a predetermined number of repetition of signal block consisting of the skip signal, a white information signal and a black information signal.

9. A data transmission system in which data can be transmitted in any of at least three different modes and in which the state of the transmission line is checked prior to data transmission, and a selection of the optimum transmission mode to be used is effected using the result ofthe line state check.

10. An image data transmission system according to claim 9 wherein the mode selection can also involve a selection criterion concerning the size of an image-bearing documentfortransmission.

11. An image data transmission system according to claim 10 wherein the arrangement is such that the result ofthe line state check determines whether or not data transmission will be effected by a first of said modes, and if not, the said size will determine which ofthesecond and third modeswill be used.

12. Afacsimile system substantially as hereinbefore described with reference to the accompanying drawings.