GB2123242A - Modifying television signals - Google Patents

Abstract

A circuit arrangement for performing a gamma correction or an inverse gamma correction on digital input signal Vi applied to an input terminal (1) comprises a first read only memory (12) which stores the function P = loga ({logAVi) where A and B are arbitrary constants, a second read only memory (6) which stores the function Q = logBG where G is the correction factor, an adder (4) which adds the outputs of the read only memories (6,12) and a further read only memory (13) which stores the function A exp Ä{B exp ({R)Ü where R= P+Q. This enables the usual multipliers to be replaced by an adder which is easier to produce in digital form. In a modification for performing the inverse gamma correction operation the adder (4) is replaced by a subtractor. When operating on analogue signals, the log, log(log) and double exponential functions are performed by non linear amplifiers. <IMAGE>

Description

SPECIFICATION Modifying television signals The invention relates to a circuit arrangement for modifying a television signal. Such modification is required for gamma correction or for the inverse function of deriving an uncorrected signal from a previously gamma corrected signal as may be required, for example in television cameras.

Display tubes for television introduce a distortion of the picture information due to a non-linear relationship between the applied signal voltage and the resulting screen brightness. This relationship may be approximated by the expression Lo - KV,Y where Lo = Light output K = constant Vs = applied signal voltage y = constant, known as gamma.

Typically w has a value of 2.5 whereas ideally it would be 1.0.

To prevent this distortion become apparent to the viewer the video signal is transmitted in a modified form by passing the signal through a gamma correction circuit which introduces a complementary distortion.

The modification carried out by a gamma corrector may be described by the expression V = Vi' Y = V1G where Vs = output signal for transmission Vj = input signal requiring modification y = constant, as before.

In practice the value of dy employed in the gamma correction circuit may not be exactly 2.5 but chosen to give the best subjectively pleasing result.

Gamma correction is normally achieved by first converting the input signal into its logarithm, then multiplying this signal by the desired correction factor G, and finally applying the resultant signal to an exponential oranti-logarithm converter.

If the signals are expressed in digital form, as is increasingly common, the same approach can be followed except that logarithmic and exponential conversion may then be achieved by means of 'look-up' tables stored in programmable read only memories (PROMs). Some difficulty is encountered, however, with the multiplication process which must be performed on each digital sample within the sample period, typically 75ns. The digital signal, after conversion into its logarithm, may be 12 bits wide and the correction coefficient, G, 6 or more bits wide. The multiplication of a 12 bit number by a 6 bit number within 75ns entails either complex circuitry to form and add partial products, or the use of integrated circuit multipliers which consume considerable power and are relatively expensive.

It is an object of the invention to produce a circuit arrangement for generating a gamma corrected or an inverse gamma corrected television signal which does not require the use of a multiplier circuit.

The invention provides a circuit arrangement for gamma correcting an input video signal Vj comprising first means for producing a first signal P equal to logs (-logV1), second means for producing a second signal Q equal to log8G where G is the correction factor, means for adding the first and second signals to produce a third signal R equal to P+Q, and third means for producing a fourth signal equal to A exp [-B exp (-R)], the fourth signal being the gamma corrected video signal.

The invention further provides a circuit arrangement for performing an inverse gamma correction on an input video signal Vj comprising first means for producing a first signal P equal to logs (logVi), second means for producing a second signal Q equal to logsG where G is the correction factor, means for subtracting the second from the first signal to produce a third signal R equal to P-Q, and third means for producing a fourth signal equal to A exp [-B exp (-R)], the fourth signal being the corrected video signal.

These arrangements enable the multiplier of prior art arrangements to be replaced by an adder or a subtractor as appropriate. Where digital signals are employed adders and subtractors can be fabricated more cheaply than multipliers and can operate more quickly. The sampling rate agreed by the European Broadcasting Union for digital television standards is 13.5 MHz which means that the time available for processing each sample is less than 75nSecs.

It may be noted that in a gamma correction circuit which comprises a read only memory code converter is disclosed in a paper entitled "Digital Processing Amplifier and Colour Encoder" by Yoshizumi Eto, Kazuyuki Matsui, Shizuka Ishibashi, and Hiroyuki Terui which was published in SMPTE Journal, Volume 87, January 1978, pages 15 to 19. However the arrangement described therein will only produce a fixed gamma correction it not being possible to alter the correction factor.

When the input video signal Vj is in digital form the first, second and third means may comprise programmed digital memory devices which digital memory devices may comprise programmable read only memories.

This enables a relatively simple construction from readily available standard integrated circuits.

When choosing the bases for the logarithms it is convenient to make A equal to 2" where n is the number of bits in each sample of the input signal. B may be conveniently chosen to be equal to 10X where x = [- log10 (IogAi)].

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 illustrates in block schematic form the principle of gamma correction according to the invention, Figure 2 shows in block schematic form a first embodiment of a circuit arrangement for gamma correcting an input video signal according to the invention, Figure 3 shows in block schematic form a second embodiment of a circuit arrangement for gamma correcting an input video signal according to the invention, and Figure 4 is a graph of the function y = [-log8 (-logA (x))].

Figure 1 illustrates an arrangement for producing a modified signal which does not involve the use of multipliers and comprises an input 1 for a video signal Vj which input is connected to a log conversion unit 2 for producing a first output equal to logn V1. The output of unit 2 is connected to a log conversion unit 3 for producing a second output signal equal to logs (logA Vi). The second output signal is applied to a first input of an adder 4. A correction factor G is connected via a second input 5 of the arrangement to a unit 6 which produces a third output signal equal to log. The third output signal being connected to a second input of the adder 4.The adder 4 produces a fourth output signal equal to logs (logA Vi) + logsG which is fed to an antilog conversion unit 7 which produces a fifth output signal equal to G logAVj. The fifth output signal is fed to an antilog conversion unit 8 which produces a sixth output signal equal to VjG which sixth output signal is applied to an output terminal 9 of the arrangement.

Since in a television signal the black level and peak white level must remain at defined amplitudes it is necessary that the input signal Vj is defined as being in the range 0V11. However, since the logarithm of a number having a value between 0 and 1 is always negative it is not possible to find the second logarithm [logs (logs V1)] since, mathematically, there is no logarithm of a negative number.

However, in this case, for the purpose of achieving the multiplication function the sign of the multiplicand may be ignored and the multiplicand treated as a positive number even though it is in fact negative. This applied in this case since the multiplicand is always negative and the multiplier G is always positive; consequently the product is always negative.

This procedure is shown functionally in Figure 2 in which those items having the same functions as corresponding items in Figure 1 have been given the same reference numerals. In the arrangement shown in Figure 2 a unit 10 is added which multiplies the output of unit 2 by -1 to give an output signal equal to -IO9A lO Vj which means in turn that the first input of the adder 4 receives a signal equal to logs (-logA V1). As a result the output of the adder is equal to logs (- logA V1) + logsG and the output of unit 7 is equal to -G logV1. This signal is then multiplied by -1 in a unit 11 to give an output G logVi which is then applied to the unit 8.

If the input signal Vj is in analogue form the log and antilog conversion units may be realised as amplifiers having logarithmic and exponential characteristics respectively, the units 10 and 11 by inverting amplifiers, and the adder 4 as a summing amplifier.

If the input signal Vj is in digital form then the log and antilog conversion units may be formed as programmable read only memories (PROMS) and the units 10 and 11 may be incorporated in the respective PROM since their only effect is to change the sign of the output. In practice, with a digital input signal a further simplification can be made as illustrated in Figure 3. In the arrangement shown in Figure 3 a PROM 12 replaces units 2,3 and 10 and a PROM 13 replaces units 4, 5 and 11. The arrangement then simplifies to three PROMS 6,12 and 13 and an adder 4.With this arrangement the PROM 12 is programmed to give an output equal to [-logB (-logV1)] in response to an input signal Vj, the PROM 6 is programmed to give an output equal to logsG in response to an input signal G, and the PROM 13 is programmed to give an output A exp [-B exp (-R)] where R = P+Q P = logB (-logVi), and 0 = logBG.

The embodiments described may be modified to perform the inverse function, that is to convert a previously gamma corrected signal into an uncorrected signal or is = V1llG. The only modification required is to replace the adder 4 by a subtractor so that at the output of the subtractor the function Iog8(logV1)-log8G is formed. Such an inverse operation may be useful within television camera circuits or in special effects generators.

The choice of logarithm bases A and B is arbitrary but there are certain values which ease implementation.

If base A is related to the resolution of the input variable, Vj, the dependent variable P can be made positive for all non-zero values of Vj. Vj may, for example, be a ten bit binary number representing values in the range 0 1023 1024 V' 1024 If base A is chosen as 1024, then the intermediate variable, I = [-109,024 (V1)] varies between 0.00014095 and 1.0 as Vj varies between 1023 1024 and 1024 The zero value, V1 = 0 1024, is a special case, discussed hereinafter.

The second logarithm base, B, acts as a scaling constant and is conveniently chosen such that 0 # P # 1 for 0 # Vi # 1023 0 # P # 1 for 1024 Vi 1024 This is achieved by making B = 10X 1023 where x = [-log10 (-log1024 (1023))] rounded up.

For the values given B = 7095.

The general form of the function y = [-log8 (-log (x))] is as shown in Figure 4.

By differential calculus it can be shown that the minimum gradient if the function y = [-logB (-logA (x))] occurs for a value of x = lie. At this point the gradient of the function is gradientmjn loge B = .3066 (B = 7096) For each input code to translate to a unique output code the output code must have four times the resolution of the input code. Consequently if the input is defined by ten bits, the output should have twelve bits. If the value of [logBG] is subtracted instead of added then inverse operation is achieved, i.e. the output signal becomes Vs = V Y) In practice certain circumstances require special attention when the input value Vj = 0 the output Vs must also be zero. This can be done by detecting the zero value of the input code either by a multiple input 'NOR' gate having one input for each input bit or by using an extra output from PROM 12. When the zero input code is detected the output code, Vs, can be artificially forced to zero.

For large values of Vj the adder may overflow. This is readily detected by sensing the 'carry-out' output of the adder. In the event of overflow the output, Vs, must be artificially forced to unity. Conversely if inverse operation is being done then the state of 'underflow' of the subtractor must be sensed and the output, V forced artificially to zero.

Claims (8)

1. A circuit arrangement for gamma correcting an input video signal Vj comprising first means for producing a first signal P equal to logs (-logAVi), second means for producing a second signal Q equal to logBG where G is the correction factor, means for adding the first and second signals to produce a third signal R equal to P+Q, and third means for producing a fourth signal equal to A exp [-B exp (-R)], the fourth signal being the gamma corrected video signal.

2. A circuit arrangement for performing an inverse gamma correction on an input video signal Vi comprising first means for producing a first signal P equal to logs (-logAVi), second means for producing a second signal Q equal to logsG where G is the correction factor, means for subtracting the second from the first signal to produce a third signal R equal to P-Q, and third means for producing a fourth signal equal to A exp [-B exp (-R)], the fourth signal being the corrected video signal.

3. A circuit arrangement as claimed in Claim 1 or Claim 2, in which the input video signal Vj is in digital form wherein the first, second and third means comprise programmed digital memory devices.

4. A circuit arrangement as claimed in Claim 3, in which the digital memory devices comprise programmable read only memories.

5. A circuit arrangement as claimed in any of Claims 1 to 4, in which A = 1024.

6. A circuit arrangement as claimed in any preceding claim, in which B=1 0x where x = [ -logs0 (-logA (A-1)].

A

7. A circuit arrangement as claimed in any preceding claim, in which the resolution of the gamma corrected signal is four times that of the input video signal.

8. A circuit arrangement for performing a gamma correction or an inverse gamma correction on an input video signal substantially as described herein with reference to Figures 1 and 2 or to Figures 1 and 3 of the accompanying drawings.