GB2123241A - Improvements in or relating to colour television colour decoders - Google Patents

Abstract

A circuit arrangement is provided for permitting a colour decoder for decoding signals of one type, such as PAL signals, to decode signals of another type, such as NTSC. The circuit arrangement comprises a conventional decoder 1 arranged to receive one of the colour difference signals directly or via a linear multiplier 9 provided with a circuit arrangement 11a 11b 12, 14 for alternately reversing the phase of the colour difference signals. Another circuit arrangement 15, 16, 17 18 causes the colour burst signal of the incoming chrominance signal to swing in phase in synchronism with the reversing of the colour difference signal phase for each alternate line. Thus, in the case of a PAL decoder 1, the colour burst signals and one of the colour difference signals of a NTSC chrominance signal are modified to give the appearance of a PAL chrominance signal. <IMAGE>

Description

SPECIFICATION Improvements in or relating to colour television colour decoders The present invention relates to colour television colour decoders. Such a decoder may be used for decoding NTSC or PAL colour television signals.

Nearly all conventional colour television receivers are equipped with circuitry which permits correct operation with only one of the three standard colour signal coding systems i.e. NTSC, PAL, or SECAM.

Each of these standard coding systems transmits the luminance signal in essentially the same way, but with differences in the number of lines per frame and with different frame or field frequencies. However, the chrominance signals are treated differently and in such a way that the systems are incompatible with each other.

The NTSC and PAL systems use a modulated subcarrier system for coding the chrominance signal, whereas the SECAM uses a different modulation technique and is thus wholly incompatible with the other two systems.

There are two main differences between the NTSC and PAL systems which lead to the incompatibility, the first of which concerns differences in the number of lines per frame and field frequency and the second of which concerns the phase of one of the colour difference signals modulated on the subcarrier. The NTSC system provides 525 lines per frame and transmits 60 fields per second interlaced in pairs to provide 30 frames per second. Also, the two colour difference signals are modulated in quadrature onto the subcarrier without any variation in their phase. The PAL system provides 625 lines per frame and transmits 50 fields per second inerlaced in pairs to provide 25 frames per second.The two colour difference signals are also modulated in quadrature on the sub-carrier but, whereas the phase of one difference signal is not varied, the phase of the other difference signal is reversed on alternate lines. Further, there are variations of both NTSC and PAL sub-carrier frequencies.

The line frequency for the NTSCsystem is thus 15, 750, Hz whereas that for the PAL system is 15, 625.

However, the line timebase and synchronising circuits in most colour television circuits are such that they will lock onto either of these frequencies without modification. The frame timebase and synchronising circuits in some colour television circuits are capable of locking at either 50 Hz or 60 HZ, but other circuits require relatively minor modifications to enable locking onto either frequency. It is generally necessary also to adjust the "picture height" control separately for each frequency because of the way in which the frame timebase generates the vertical scanning ramp voltage. However, because of the alternate line phase inversion of the PAL system, the colour decoders of the NTSC and PAL systems are incapable of operating with PAL- and NTSCcoded signals, respectively.

With the coming into operation of satellite broadcasting, there is the increasing possibility of television sets in one area or country being able to receive signals from another area or country. However, where the two areas or countries adopt different colour standards, the incompatibility problems described above limit the utility of the television receivers. This problem is even more acute where television sets are installed in ships or other vehicles which may travel to parts of the world adopting different colour standards.

The problem also occurs with video cassette recorders when an attempt is made to reproduce a cassette recorded according to one standard by means of a machine designed to work on another standard. For instance, some PAL video cassette recorders are capable of replaying cassettes recorded according to the NTSC system without substantially degrading the chrominance signal.

However, a PAL decoder in a conventional television receiver cannot make use of the colour information.

According to a first aspect of the invention, there is provided a circuit arrangement for permitting a colour decoder for decoding colour signals of a first type to decode colour signals of a second type, comprising means for selectively inverting one of the colour difference signals of the decoder and means for causing the inverting means to invert the one colour difference signal during alternate lines of the television picture.

It is thus possible to provide a circuit arrangement which permits, for instance, a PAL decoder to decode satisfactorily colour signals of the NTSC system without the need to provide two fully independent colour decoders.

The inverting means may invert the "V" colour difference signal prior to demodulation by the decoder. Alternatively, the "R-Y" colour difference signal resulting from demodulation, but prior to matrixing to form the colour signals R, G, and B, may be inverted.

According to a second aspect of the invention, there is provided a circuit arangement for synchronizing a frame time base, comprising a phase sensitive detector arranged to receive field syne pulses and field blanking pulses, and to supply a frequency control to the frame time base.

Such a circuit arrangement may be applied to a frame time base of the type employing a ramp generator whose frequency may be voltage controlled. Thus, the frame time base will synchronize to either 50 Hz, for the PAL system, or to 60 Hz, for the NTSC system, and will provide a scanning ramp voltage of constant amplitude irrespective of the synchronized frequency of operation. This avoids the disadvantages inherent in conventionally synchronized time bases in which synchronization is achieved by resetting the ramp wave-form so that the height of this wave-form is dependent on the frequency of operation. Thus, in the case of a television receiver capable of receiving signals of both the PAL and NTSC system, it is unnecessary to provide separate switching or adjustment of the frame time base amplitude or picture height.Further, because the frame time base effectively forms the voltage controlled oscillator in a phase locked loop, the control voltage supplied from the phase sensitive detector to the frame time base provides a measure of the frequency of operation of the time base and may thus be used to control automatic switching of a circuit arrangement according to the first aspect of the present invention according to which type of colour signals are being received.

According to a third aspect of the invention there is provided a circuit arrangement for selecting the subcarrier frequency of a colour television colour decoder, comprising switch means for selectively connecting one of a plurality of filters to the colour decoder, and sequencing means for causing the switch means to connect the filters one after another to the decoder and arranged to be inhibited by correct colour decoding by the decoder.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block circuit diagram of a PAL colour decoder incorporating a circuit arrangement constituting a preferred embodiment of the invention; Figure 2 is a block circuit diagram of a frame synchronizing and NTSC/PAL signal detecting circuit arrangement forming another part of the preferred embodiment of the invention, and Figure 3 is a block circuit diagram of a circuit arrangement for selecting the decoder sub-carrier frequency.

The circuit arrangement of Figure 1 includes a conventional PAL decoder 1 of a colour television receiver for processing an input chrominance signal so as to provide red, green, and blue signals R, G and B for driving a colour television tube via appropriate video amplifiers and the like.

The decoder 1 is of the type which provides an automatic gain controlled chrominance signal at terminal 2 (better known as A.C.C. controlled) for driving a PAL delay line, and having inputterminals 3 and 4 for receiving the U and V colour difference signals from the delay line 5. The decoder 1 also receives the luminance signal at 6 and control signals at 7, so that the circuit arrangement constituting the preferred embodiment of the invention does not affect the operation of controls of the television receiver.

The output signals from the terminal 2 of the decoder 1 are also supplied to a level-equalizing attenuator 8, whose output is connected to the input of a linear multiplier 9, for instance formed by a 4-quadrant integrated circuit multiplier. A set of changeover switches 10a, 10b and 10c are controlled by an NTSC/PAL control signal supplied from the circuit arrangement shown in Figure 2, which will be further described hereinafter.

In Figure 1, the switches are shown in their NTSC selecting position in which the switches 10a and 10b connect the U and V inputs 3 and 4 of the decoder 1 to the outputs of the attenuator 8 and the multiplier 9 respectively. However, when a PAL signal is detected, the electronic switches 1 0a and lOb switch to their other positions in which they connect the inputs 3 and 4 to the U and V outputs of the PAL delay line 5, which functions as the conventional comb separator.

The linear multiplier 9 has a second input which is connected to one of a pair of further electronic changeover switches 1 la and 1 it. The switches 11a and 11 1b are controlled by a burst keybulse provided buy a sandcastleseparator 12 from signals received from the television receiver at a terminal 13. The burst keybulse is also supplied to a divide-by-two circuit 14, whose output is connected to a first fixed "contact" of each of the switches 11 a and 11 b. The other fixed contact of the switch 11 a is shown connected to ground whereas the other contact of the switch 1 1b is shown as having no connection.

The moving "contact" of the switch 1 1b is connected, via the switch 1 Oc when in its NTSC position, to one input of another linear multiplier 15, whose other input is connected via a level-adjusting cntrol 16 to receive the incoming chrominance signal. The output of the linear multiplier 15 is connected to the input of a 90 phase shigting circuit 17, whose output is connected to one input of an adder or mixing circuit 18. The other input of the adder 18 receives the chrominance signal. The output of the adder 18 is connected to the chrominance signal input of the decoder 1.

When a PAL colour signal is received by the television receiver, which supplies the PAL chrominance signal via the terminal 19to the circuit arrangement of Figure 1, the signal supplied to the terminal 20 has a level which causes the switches 10a and 10b to connect the U and V outputs of the delay line 5 to the corresponding inputs 3 and 4 of the decoder 1, and the switch 10cto disconnect the switch 11 b from the multiplier 15. Thus, the outputs of the attenuator 8 and the multiplier 9 are disconnected from the decoder 1, which decodes the PAL chrominance signal in the usual way.Although the portion of the circuit including the multiplier 15 and the adder 18 continue to function, there is no output from the multiplier 15 so that nothing is added by the adder 18 to the PAL chrominance signal and operation of the decoder 1 is not affected.

When a NTSC signal is received by the television receiver, the signal at the terminal 20 has a level such that the switches 10a lOb and 10c move to the positions shown in Figure 1, so that the demodulated colour difference signals from the decoder 1 are supplied to the attenuator 8, which serves to equalize the levels of the signals supplied to the inputs 3 nd 4 of the decoder 1 at the values corresponding to the values normally provided by the delay line 5 when a PAL chrominance signal is being decoded. The U input 3 receives its signal directly from the attenuator 8 whereas the V input 4 receives its input signal from the output of the linear multiplier 9. Also, the switch 1 Oc connects the switch 1 lib to the multiplier 15.

The separator 12 and divide-by-two circuit 14 supply signals which correspond to multiplication x 1 and multiplication x - 1 for alternate lines of the transmited picture signal. Thus when the burst key pulse, and hence the colour burst signal, are not being received, the switch 11 a supplies a voltage corresponding to multiplication by + or -1 to the linear multiplier 9, which thus inverts the phase of the signal supplied to the V input 4 of the decoder 1 for each alternate line. During the burst key pulse, the switch 1 la connects the input of the multiplier 9 to a voltage corresponding to multiplication x -1 so as to maintain correct operation of the decoder 1 while the colour burst signal is being received.

Accordingly, the phase of the NTSC colour difference signal simulating the V signal to the decoder 1 is reversed for each alternate line in accordance with the PAL system V colour difference signal.

The switch 1 lib supplies a voltage to the linear multiplier corresponding to multiply by zero except during the burst key pulse, so that the multiplier 15 supplies no output signal and the chrominance signal is supplied from the terminal 19 via the adder 18 to the decoder 1 without modification. The burst key pulse causes the switch 11 b to be connected to the output of the dive-by-two circuit 14, which thus supplies a signal to the multiplier 15 causing multiplication by +1 or -1 according to whether the phase of the signal V supplied to the decoder 1 is to be inverted during the subsequent line. The multiplier 15 thus isolages the colour burst signal and inverts it on alternate lines, and the alternately inverted colour burst signal is phase shifted by 90 in the phase shifter 17.The phase shifted colour burst signal is then added to the ordinary chrominance signal in the adder 18, and has a phase such that it causes the phase of the colour burst signal supplied from the adder 18 to the decoder 1 to oscillate symmetrically between + and - approximately 45 so as to permit the ident circuit in the decpder 1 to operate correctly and to prevent the colour killer circuit from being actuated. Adjustment of the actual + and - phase shift allows the maximum colour saturation in the NTSC mode to be set so as to correspond to that in the PAL mode.

The circuit arrangement shown in Figure 1 thus permits an essentially conventional PAL decoder 1 to operate from NTSC system colour signals modifying the colour burst signals in the chrominance signal supplied to the decoder so as to resemble the colour burst signal of a PAL chrominance signal, and by alternately inverting the V colour difference signal supplied to the demodulator in the decoder 1.

This provides satisfactory reproduction of the NTSC colour signal (without, of course, the advantages inherent in the PAL system) while permitting the standard controls of the decoder 1 to remain functional.

Although the circuit arrangement shown in Figure 1 is provided for enabling a PAL decoder to operate from a NTSC chrominance signal, the circuit arrangement could readily be modified by a man skilled in the art to permit a NTSC decoder to operate satisfactorily on PAL chrominance signals.

Figure 2 shows a circuit arrangement for providing the NTSC/PAL detection signals to the circuit arrangement of Figure 1, and for synchronizing the frame time base of a television receiver. The circuit arrangement comprises a phase sensitive detector in the form of a digital edge counting phase compara tor 21 which receives on its inputs 22 and 23 the field sync pulses from the sync separator of the television receiver and the field blanking pulses from the frame time base. The output of the phase comparator 21 is supplied to a loop filter in the form of an integrator 24 and thence via a potential divider comprising resistors 25 and 26 to the base of an output transistor 27. The open-circuit collector of the transistor 27 is conneced to an output terminal 28 for connection to a frequency control input of the frame timebase.

Thus, the parts of the circuit arrangement of Figure 2 which have been described operate, together with the frame timebase of the television receiver, as a phase locked loop with the frequency of the frame timebase being locked to that of the field sync pulses. Where the circuit arrangement of Figure 2 is provided in a conventional television receiver, some modification of the frame timebase is required. For instance, triggered reset of the timing ramp by the field synchronizing pulses has to be disabled and the terminal 28 must be connected to the timebase in such a way that the frequency of oscillation is controlled by the output of the filter 24.

The emitter of the transistor 27 is provided with a load resistor 29 to provide a voltage proportional to, or at least corresponding to, the frequency of operation of the frame timebase. This signal is supplied to a first input of a comparator 30, whose second input is connected to a potential divider 31 which provides a reference voltage. The output of the comparator 30 supplies the NTSC/PAL detection signal to the terminal 20 of the circuit arrangement of Figure 1.

The use, the phase comparator 21 compares the timing and frequency of the field blanking pulses from the frame timebase, which constitutes the voltage controlled oscillator of the phase locked loop, with the field synchronising pulses, and controls the time base via the integrator so that the timebase locks to the synchronising pulses. The integrator provides the loop filtering or damping of the phase locked loop and permits a fast lock-up without affecting the pull-in range of the loop because of the use of the digital edge counting phase comparator. In particular, this type of phase locked loop does not average the synchronising timing but responds to each sync pulse and is therefore not immune from noise. However, its behaviour to noise pulses when locked is similar to that of the contentional trigger synchronised time base.

This arrangement thus permits the frame time base to be synchronised to either 50 Hz, in the case of PAL signals, orto 60 Hz in the case of NTSC signals. The control voltage provided by the loop filter is supplied to the first input of the comparator 30 and has a value determined by the frequency to which the timebase has been synchronised, and the reference voltage supplied by the divider 31 is set to a value between the two values corresponding to the two frequencies of synchronisation. Thus, the output signal of the comparator 30 indicates which type of signal is being received and thus provides automatic control of the operation of the decoder circuit arrangement of Figure 1.

An advantage of the synchronising circuit arrangement shown in Figure 2 is that the amplitude of the voltage ramp produced by the frame timebase is not effected by the frequency of operation thereof, as opposed to the conventional trigger-synchronised timebase in which the amplitude of the ramp falls with increasing frequency of operation. Thus, no adjustment of the amplitude of the ramp or of the picture height is necessary when changing from NTSC system to PAL system signals, and vice versa.

Figure 3 shows a circuit arrangement for selecting the colour subcarrier frequency of the decoder 1, which corresponds to the decoder 1 shown in Figure 1. The circuit arrangement shown in Figure 1 is indicated in Figure 3 at 40.

The decoder 1 has an output 41 connected to an electronic switch 42. The switch 42 is connected to a plurality of quartz crystal filters 43a, 43b, 43c connected in series with respective trimming capacitors 44a, 44b, and 44c, respectively. Any number of crystal filters may be provided so as to ensure that all subcarrier frequencies presently in use are catered for by the circuit arrangement. A low input impedance amplifier 45 has an input connected to the trimmer capacitors and an output connected to a crystal input terminal 46 of the decoder 1.

The control inputs of the selector switch 42 are connected to the outputs of a counter 47, whose clock input is connected to the output of a low frequency clock generator 48. The clock generator 48 has an inhibit and reset clock input 49 connected to a terminal 50 of the decoder which supplies the colour killer signal in the form of a first voltage level, which inhibits and resets the clock generator 48, when a colour signal is being correctly decoded by the decoder 1, and a second level, which allows the clock generator 48 to supply clock pulses to the counter 47, when the colour killer within the decoder 1 is active indicating absence of a suitable colour signal fordecoding.

The terminal 19, to which the chrominance signal is supplied, is connected to the circuit arrangement 40 and thence to the decoder 1, and also to a first input of a PAL recognition circuit 51. A second input of the PAL recognition circuit is connected to the output of the low input impedance amplifier 45. The output of the circuit 51 supplies a NTSC/PAL selection signal to the circuit arrangement 40 i.e. to the terminal 20 in Figure 1, and may be used in place of the comparator 30 shown in Figure 2 for controlling operation of the decoder 1. This is particularly useful where the value of the synchronised frame time base frequency does not give an unambiguous indication of whether NTSC or PAL colour signals are being received, for instance in the case of a PAL system operating with a frame time base frequency of 60 HZ.

The circuit 51 has a further input 52 to which the burst key pulse is supplied so that the circuit is only active when the colour burst signal is being received.

During the colour burst signal, the circuit 51 compares the colour burst signal being received with the subcarrier generated in the decoder 1. For instance, the circuit 51 may operate in essentially the same way as the ident circuit in the decoder 1 so as to detect the swinging phase colour burst signal which characterises the PAL system. When the swinging phase burst signal is detected, the circuit 51 supplies a signal to the terminal 20 of the circuit arrangement 40 so as to change the switches 10a, lOb and lOcto the PAL position.

When a chrominance signal is supplied to the decoder 1,assuming that the crystal selected by the switch 42 is incorrect, the colour killer within the decoder 1 supplies an output voltage on the line 50 which enables the clock generator 48 to supply pulses to the clock input of the counter 47. The counter 47 causes the selector 42 to connect each of the crystals 43a, 43b 43coo the decoder 1 in turn and the frequency of the clock generator 48 is arranged so that each crystal is connected to the decoder 1 for a period which is longer than the recognition and settling period of the decoder 1.

Assuming that a chrominance signal is being supplied to the terminal 19, when the crystal whose frequency is equal to the subcarrier frequency of the chrominance signal is selected, the colour killer in the decoder 1 is deactivated and the voltage supplied to the terminal 49 of the clock generator 48 changes so as to inhibit the generator and reset it.

The counter 47 thus retains its current state and causes the selector switch 42 to maintain the connection of the crystal filter of correct frequency to the decoder 1. At the same time, the PAL recognition circuit 51 detects whether the incoming chrominance signal is of NTSC or PAL type, and supplies the selection signal to the terminal 20 of the circuit arrangement 40.

The circuit arrangement of Figure 3 thus provides automatic selection of the correct subcarrier frequency for the decoder 1 in such a way as not to impair the automatic phase control loop which frequency-and-phase locks the subcarrier to the colour burst portion of the chrominance signal.

In order to prevent colour "flashing" during the selection process, caused by the sequential selection of the crystal filters, the circuit arrangement of Figure 3 may include circuitry for preventing colour signals from being supplied until a colour signal is being received and the correct subcarrier frequency is being generated by the decoder 1. For instance, the signal supplied to the output terminal 50 of the decoder 1 may be used to alter the saturation control signal, normally supplied from a manually operable control on a PAL decoder, so as to inhibit any attempt by the decoder 1 to provide colour information.

A further detector switch (not shown) may be provided and operated in synchronism with the switch 42 so as to select the correct subcarrier wave trap in the video amplifier of a television. Preferably, such a further selector switch is only enabled to connect the selected wave trap when a colour signal is being detected, for instance by means of the signal supplied to the output 50 of the decoder, so as to prevent unnecessary filtering and interference with the picture, for instance when a monochrome picture is being received.

Claims (38)

1. A circuit arrangement for permitting a colour decoder for decoding colour signals of a first type to decode colour signals of a second type, comprising means for means for selectively inverting one of the colour difference signals of the decoder and control means for causing the inverting means to invert the one colour difference signal during alternate lines of the television picture.

2. A circuit arrangement as claimed in claim 1, in which the inverting means comprises a linear multiplier having a first input for receiving the one colour difference signal and a second input connected to the output of the control means, which is arranged to produce an output signal corresponding to +1 and -1 during alternate lines.

3. A circuit arrangement as claimed in claim 1 or 2, in which the control means comprises a pulse supplying circuit arranged to supply a burst key pulse corresponding to the presence of a colour burst signal in the signal of the second type, a control signal producing circuit arranged to produce at its output an inversion-causing signal in response to alternate burst key pulses and a non-inversioncausing signal in response to the remainder of the burst key pulses, and changeover switch means arranged to connect the inverting means to the ouput of the control signal producing circuit in the absence of the burst key pulses and to an inversioncausing signal source in the presence of the burst key pulses.

4. A circuit arrangement as claimed in claim 3, in which the control signal producing circuit comprises a bistable multivibrator.

5. A circuit arrangement as claimed in any one of the preceding claims, in which there is provided means for altering the phase, during alternate lines of the television picture, of a colour burst signal of the signal of the second type.

6. A circuit arrangement as claimed in claim 5, in which the phase altering means comprises a phase varying circuit for varying the phase of the colour burst signals, and an adder for adding the phase shifted colour burst signals to the signal of the second type supplied to the decoder.

7. A circuit arrangement as claimed in claim 6, in which the phase varying circuit comprises a further linear multiplier having a first input for receiving the colour burst signals and a second input for receiving a signal which corresponds to O in the absence of the colour burst signals and to +1 and -1 in the presence of alternate colour burst signals, and a phase shifting circuit for shifting the phase of the output signal of the further multiplier by 90 degrees.

8. A circuit arrangement as claimed in claim 7 when dependent on claim 3, including further changeover switch means arranged to connect the second input of the further linear multiplexer to the output of the control signal producing means in the presence of the burst key pulses and to a zero signal source in the absence of the burst key pulses.

9. A circuit arrangement as claimed in any one of the preceding claims, including means for detecting whether signals of the first or the second type are supplied to the decoder and for activating and deactivating the circuit arrangement when signals of the second and first types, respectively, are detected.

10. A circuit arrangement as claimed in claim 9, in which the detecting means is arranged to provide a detection signal corresponding to the synchronised frequency of the frame timebase of a television receiver to indicate detection of signals of the first or second type.

11. A circuit arrangement as claimed in claim 10, in which the detecting means comprises a phase sensitive detector arranged to receive field sync pulses and field blanking pulses from the television receiver and to supply a control voltage to the frame timebase, and a comparator arranged to compare the control voltage with a reference voltage to provide the detection signal.

12. A circuit arrangement as claimed in claim 11, in which the phase sensitive detector is a digital edge counting phase comparator.

13. A circuit arrangement as claimed in claim 11 or 12, in which the output of the phase sensitive detector is connected to an integrator for providing the control voltage.

14. A circuit arrangement as claimed in any one of claims 11 to 14, in which a transistor is arranged to supply the control signal at an open-circuit collector thereof for connection to a control input of the frame timebase.

15. A circuit arrangement as claimed in claim 14, in which the comparator is arranged to receive the control voltage from across an emitter resistor of the transistor.

16. A circuit arrangement as claimed in any one of claims 9 to 15, including switch means arranged to supply the one colour difference signal from the output of the linear multiplier to the decoder when a signal of the second type is detected by the detection means.

17. A circuit arrangement for permitting a colour decoder for decoding colour signals of a first type to decode colour signals of a second type, substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

18. A colour decoder including a circuit arrangement as claimed in any one of the preceding claims.

19. A colour decoder as claimed in claim 18, in which the signals of the first and second types are PAL and NTSC signals, respectively.

20. A colour decoder as claimed in claim 19 when dependent on claim 16, including a comb separator and a level attenuator arranged to receive the automatic gain controlled chrominance signal, the switch means being arranged to supply the V signal from the comb separator to the decoder when a signal of the first type is detected by the detecting means, there being provided further switch means arranged to supply the U signal or the attenuator output signal to the decoder upon detection of signals of the first or second type, respectively, by the detection means, the output of the attenuator being connected to the input of the inverting means.

21. Atelevision receiver including a colour decoder as claimed in any one of claims 18 to 20.

22. A circuit arrangement for synchronising a frame timebase, comprising a phase sensitive detector arranged to receive field sync pulses and field blanking pulses and to supply a frequency control to the frame timebase.

23. A circuit arrangement as claimed in claim 22, in which the phase sensitive detector comprises a digital edge counting phase comparator.

24. A circuit arrangement as claimed in claim 22 or 23, including an integrator connected to the output of the phase sensitive detector for providing the control voltage.

25. A circuit arrangement as claimed in any one of claims 22 to 24, including a transistor for supplying the control current and having an open-circuit collector for connection to the frame timebase.

26. A frame timebase including a circuit arrangement as claimed in any one of claims 22 to 25.

27. Atelevision receiver including aframetimebase as claimed in claim 26.

28. A circuit arrangement for selecting the subcarrier frequency of a colour television colour decoder, comprising switch means for selectively connecting one of a plurality of filters to the colour decoder, and sequencing means for causing the switch means to connect the filters one after another to the decoder and arranged to be inhibited by correct colour decoding by the decoder.

29. A circuit arrangement as claimed in claim 28, in which the switch means comprises an electronic switch.

30. A circuit arrangement as claimed in claim 28 or 29, in which the sequencing means comprises a clock generator connected to a counter whose outputs control the switching means.

31. A combination of a colourtelevision colour decoder and a circuit arrangement as claimed in any one of claims 28 to 30, in which a colour killer output of the decoder is connected to an inhibit input of the sequencing means.

32. A combination as claimed in claim 31, in which means are provided for preventing the decod erfrom supplying colour information until a chrominance signal is received and the filter whose frequency corresponds to the subcarrierfrequency of the chrominance signal has been selected.

33. A combination as claimed in claim 32, in which the preventing means is arranged to control a saturation control input of the decoder in accordance with a colour killer output thereof.

34. Atelevision receiver including a combination as claimed in any one of claims 31 to 33, including further switch means arranged to be switched in synchronism with the switch means and to select a subcarrierwavetrap in a video circuit of the receiver corresponding to the filter selected by the switch means.

35. A receiver as claimed in claim 34, in which the further switch means is arranged to be enabled by the decoder upon correct colour decoding thereby.

36. A receiver as claimed in claim 35, in which the further switch means has an enable input connected to the colour killer output of the decoder.

37. A combination of a circuit arrangement as claimed in claim 9 and a circuit arrangement as claimed in any one of claims 28 to 30, in which the detecting means is arranged to provide a detection signal corresponding to detection of a PAL swinging colour burst signal upon correct colour decoding by the decoder.

38. A combination as claimed in claim 37, in which the detecting means is arranged to be enabled by a burst key signal to compare the phase of a colour burst signal of a received chrominance signal with the subcarriergenerated by the decoder.