GB2122437A - FSK receiver with twin stable state PLL - Google Patents
FSK receiver with twin stable state PLL Download PDFInfo
- Publication number
- GB2122437A GB2122437A GB08215413A GB8215413A GB2122437A GB 2122437 A GB2122437 A GB 2122437A GB 08215413 A GB08215413 A GB 08215413A GB 8215413 A GB8215413 A GB 8215413A GB 2122437 A GB2122437 A GB 2122437A
- Authority
- GB
- United Kingdom
- Prior art keywords
- output
- input
- signal
- responsive
- comparison means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/16—Frequency regulation arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
- H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
- H04L27/152—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A heterodyne radio receiver is provided that is particularly suited to demodulating a binary FSK signal. A voltage controlled oscillator (VCO 20) generates a reference signal at the nominal center frequency of the input signal, and the signals are mixed in mixer (8) to produce an intermediate frequency (I.F.) signal. The I.F. is limited (14) and then compared with the output of a reference oscillator (22) using a phase detector (16) with a triangular transfer characteristic, the output of which is fed back to the VCO via a loop filter (18). Three ways of deriving a demodulated output are disclosed: using an analogue recovery circuit (44); or digitally using an auxiliary phase detector (30) responsive to the reference signal phase shifted 90 degrees and to the limited I.F.; or digitally using a D-type latch (54), Fig. 5 (not shown) receiving the limited I.F. and clocked by the reference signal. <IMAGE>
Description
SPECIFICATION
FSK receiver with twin stable state PLL
This invention is related to the inventions entitled "Twin Stable State PLL" and "Synchronizer For Use
With dual State PLL Receiver", of Graham Edgar
Beesley, filed on even date herewith, and assigned to the same assignee as the present invention.
This invention relates generally to the field of electronic circuits, and, in particular, to a heterodyne radio receiver.
The present invention concerns an improvement heterodyne radio receiver. To reduce the manufacturing costs and the packaging size of radio receivers, it is desirable to provide as much ofthe receiver circuitry as possible in integrated form.
By providing a receiver circuit utilizing a digital phase locked loop (PLL) and a low (i.e. in the audio range) intermediate frequency, the present invention facilitates an integrable receiver. In the prior art, the use ofhighfrequency l.F.'s particularlywhen high gain is required, requires a degree of physical isolation oaf circuit elements which does not easily tend itself to integration.
The present invention can be implemented entirely on a digital integrated circuit, thus considerably reducingthe cost of manufacturing the circuitand enabling the greater commercialization of products incorporating such circuits.
Accordingly, itis an object of the present invention to provide an improved radio receiver.
In accordance with the present invention there is provided radio receiver responsive to an input signal, the receiver comprising firstfrequencycom- parison means having a first input responsive to the input signal, a second input, and generating an output; signal limiting means having a input responsive to the output ofthe first frequency comparison means and generating an output; meansforgenerating a reference signal; secondfrequencycomparison means having a first input responsive to the output of the signal limiting means, a second input responsive to the reference signal, and an output; a controlled oscillator coupled to the output of the second frequency comparison means and providing an output to the second input ofthe first frequency comparison means; and analog data recovery means having an input coupled to the output ofthe second frequency comparison means and generating a demodulated output signal.
The invention is pointed out with particularity in the appended claims. However, otherfeatures ofthe invention will become more apparent and the invention will be best understood by referring to the following detailed description in conjunction with the accompanying drawings in which:
Fig. 1 shows a block diagram illustrating several embodiments, including a preferred embodiment, of an FSK Receiver With Twin Stable State PLL of the present invention.
Fig. 2 shows several waveforms useful in under
standing the operation if a preferred embodiment of the present invention.
Fig. 3 shows a transfer characteristic of phase detector 16 of the present invention.
Fig. 4 shows several waveforms useful in understanding an alternative embodiment of the present invention.
Fig. 5 shows another embodiment of a radio
receiver with digital data recovery.
Referring nowto Fig. 1, a block diagram of the FSK
Receiver With Twin Stable State PLL of the present invention shown.
According to one embodiment of the present invention -- i.e. that indicated by reference numeral 2 in Fig. 1-an improved phase locked loop (PLL) is provided which is simple to implement.
According to another embodiment ofthe present invention -- i.e. that indicated by reference numeral 2 taken in combination with reference numeral 44, an improved radio receiver is provided which utilizes the above-mentioned improved PLL as well as analog data recovery circuit 44.
The preferred embodiment provides a radio receiverincorporating the above-mentioned PLL and addi tionally comprising a coherent detector which func tionsasadigital data recovery circuit and which can be implemented using solely digital technology.
Both the embodiment incorporating analog data recovery and the preferred embodiment are particularlysuited to demodulating frequency shift keyed (FSK) inputsignals. In an FSKtransmission binary O's may be represented, for example, by the presence of an uppersideband (USB) to the input signal center frequency, and binary l's represented, for example, bythe presence ofthe lower sideband (LSB)The improved PLL embodiment of the present invention is shown within the dashed outline indicated by reference numeral 2. It comprises a mixer 8 having one input responsive to the incoming signal received by antenna 5, a second input responsive to the output of voltage controlled oscillator (VC0)20, and an output to band pass filter 10.
The output of the band pass filter 10is amplified by amplifier 12, whose output is fed into limiter 14.
Limiter 14generatesa rectangular-shaped waveform in which the transitions correspond to the zerocrossing points of the signal inputthereto. The signal at point 15 thus represents a filtered, amplified, and limited intermediate frequency (I.F.).
Theoutputoflimiter 14- i.e. the limited l.F.- is input into phase detector 16, which may be implemented, in example, in digital technology as an
Exclusive NOR gate. The other input to phase detector 16 is provided bytheoutputoflocal oscillator22, which may generate, for example, a reference signal of approximately4.5 KHz.
The output of phase detector 16 is coupled via lead 17 to loop filter 18, whose output is in turn coupled to the input voltage controlled oscillator (VCO) 20. The output of VCO 20 is provided to one input of mixer8, as mentioned above. The loop filter 18 can be implemented using either analog or digital techniques.
OPERATION OF PLL
EMBODIMENT
The operation ofthe improved PLLembodimentwill
now be explained with reference to Fig. 1 and Fig. 3.
The VCO 20 output signal mixes with the incoming signal centerfrequencyto produce a 4.5 KHz l.F.
signal. This is compared in phase detector 16 with the 4.5 KHz reference signal generated by oscillator 22.
The transfer characteristic of phase detector 16 is shown in Fig. 3. The stable states ofthe loop operation are on slopes 50 and 51, one slope corresponding to reception ofthe upper side band (USB) and the other to reception ofthe lower side band (LSB) of the incoming signal.
With reference to Fig. 2, waveform 60 depicts the output ofoscillator22. When the USB is present atthe incoming signal, the stable relationship between the l.F. 61 derived from the USB and the reference signal 60 is as shown in Fig. 2. Any movements in the VCO to a higherfrequency gives rise to a decreasing l.F., which when compared in phase comparator 16with the reference frequency causes a decrease in the voltage applied to VCO 20, thereby serving to keep its output locked to the USB frequency.
Conversely, when the LSB is present at the incoming signal, the stable relationship between the l.F. 63 derived from the LSB and the reference signal 60 is as shown in Fig. 2. Any movement in the VCO 20 to a lower frequency causes an increasing l.F., which when compared in phase comparator 16 with the reference causes an increase in the voltage applied to VCO 20, keeping its output locked to the LSB frequency.
Thus there is a stablestateforthe PLLforeithera LSB or an USB. The two states of balance are on either of the slopes of the transfer characteristic shown in
Fig. 3. They provide a voltage increase both fora
phase increase at -90 degrees and for a phase
decrease at +90 degrees.
OPERATION OF RECEIVER
WITH ANALOG DATA
RECOVERY EMBODIMENT
The PLLshown in dashed outline 2 in Fig. 1 can be employed as a radio receiver with the addition of a suitable analog data recovery circuit 44, whose input is coupled to the output of loop filter 18.
It is necessary to select the reference frequency such thatthe VCO doesn't operate only at the center frequency, since there must be a change in the VCO input to enable data detection.
OPERATION OF RECEIVER WITH
DIGITAL RECOVERY EMBODIMENT
(PREFERRED EMBODIMENT)
The PLL described above can also be used as a radio receiver with the addition of the coherent detector comprising phase shifter 24 and phase detector 30.
The operation of such a receiver will be explained with referenceto Figs. 1 and 4.
Waveform 70 in Fig. 4illustratesthe reference signal generated by oscillator 22. Phase shifter 24 shifts this signal by approximately 90 degrees, as represented by waveform 71.
Phase comparator 30 compares waveform 71 with the l.F. taken from point 15 of Fig. 1. Phase comparator 30 may be implemented as an Exclusive NOR gate.
Inthecaseofan l.F. derived from the USB, which
looks like waveform 72, the output of phase comparatorwill be all 1's. When the l.F. is derived from the LSB, the output of phase comparatorwill be all 0's. These outputs may be used withoutfurtherfiltering. Howev er,filtering may be performed if desired in order to reduce the presence of transients in the outputs.
As an alternative implementation ofthe preferred embodiment, as shown in Fig. 5, the phase shifter 24 may be eliminated and a D-type latch 54 substituted for the phase comparator 30. The D input (if such latch is coupled to the l.F. and its clock input is coupled to the reference frequency.
Itwill be apparentto those skilled in the artthatthe disclosed FSK Receiver With Twin Stable State PLL may be modified in numerous ways and may assume many embodiments otherthan the preferred form specifically set out and described above.
Accordingly, it is intended bythe appended claims to cover all modifications of the invention which fall within the true spirit and scope ofthe invention.
What is claimed is:
Claims (9)
1. A radio receiver responsive to an input signal, said receiver comprising: firstfrequencycomparison means (8) having afirst input responsive to said input signal, a second input, and generating an output;
signal limiting means (14) having an input responsive to the output of said firstfrequency comparison means and generating an output;
means (22) forgenerating a reference signal;
secondfrequencycomparison means (16) having a first input responsive to the output of said signal limiting means, a second input responsive to said reference signal, and an output;;
a controlled oscillator (20) coupled to the output of said second frequency comparison means and providing an outputtothe second input of said first frequency comparison means; and
analog data recovery means (44) having an input coupled to the output of said second frequency comparison means and generating a demodulated output signal.
2. The radio receiver recited in claim 1 and further comprising
band pass filtering means (10) having an input responsive to the output of said first frequency comparison means and providing a filter output;
amplifying means (12) having an input responsive to said filtered output and providing an amplified outputtothe input of said signal limiting means; and
additional filtering means (18) responsive to the output of said second frequency comparison means and providing an inputto said voltage controlled oscillator and to said analog data recovery means.
3. The radio receiver recited in claim 1 wherein said controlled oscillator is a voltage controlled oscillator.
4. Adigital radio receiver responsive to an input signal, said receiver comprising:
first frequency comparison means (8) having a first input responsive to said input signal, a second input, generating an output;
signal limiting means (14) having an input responsive to the output of said firstfrequency comparison means and generating an output;
means (22) for generating a reference signal;
second frequency comparison means (16) having a first input responsive to the output of said signal limiting means, a second input responsive to said reference signal, and an output;
a controlled oscillator (20) coupled to the output of said second frequency comparison means and providing an output to the second input of said first frequency comparison means;; means (24)forshifting the phase of said reference signal to produce a phase-shifted reference signal;
phase comparison means (30) having a first input responsiveto the output of said signal limiting means, a second input responsive to said phase-shifted reference signal, and generating a demodulated output signal.
5. The radio receiver recited in claim 4 and further comprising:
band pass filtering means (10) having an input responsive to the output of said first frequency comparison means and providing a filtered output;
amplifying means (12) having an input responsive to said filtered output and providing an amplified output to the input of said signal limiting means;
additional filtering means (18) responsive to the output of said second frequency comparison means and providing an inputto said voltage controlled oscillator; and
outputfiltering means (32) responsive to said demodulated output signal for providing a filtered output signal.
6. The digital receiver as recited in claim 4 wherein said phase-shifting means shifts said reference signal approximately ninety degrees.
7. The digital radio receiver as recited in claim 4 wherein said controlled oscillator is a voltage controlled oscillator.
8. A digital radio receiver responsive to an input signal, said receiver comprising:
first frequency comparison means (8) having a first input responsive to said input signal, a second input, and generating an output;
signal limiting means (14) having an input responsive to the output of said firstfrequency comparison means and generating an output; means (22) for generating a reference signal;
second frequency comparison means (16) having a first input responsive to the output of said signal limiting means, a second input responsive to said reference signal, and an output;
a controlled oscillator (20) coupled to the output of said second frequency comparison means and providing an outputto the second input of said first frequency comparison means; and
a D-type latch having its D input responsive to the output of said signal limiting means, its clock input responsive to said reference signal, and generating a demodulated output signal.
9. A radio receiver substantially as herein de scribed with reference to and as illustrated in figs 1 or 5 ofthe drawings.
9. The digital radio receiver as recited in claim 8 wherein said controlled oscillator is a voltage controlled oscillator.
New claims filed on 29June 1983 superseded claims 1 to 9.
New claims:
1. A radio receiver for receiving a F.S.K. input signal, having upper and lower sidebands, said receiver comprising a twin stable state phase locked loop circuit including first frequency comparison means (8) having a first input responsive to said input signal, a second input, and an output;
signal limiting means (14) having an input coupled to the output of said firstfrequency comparison means, and an output;
means (22) for generating a reference signal;
second frequency comparison means (16) having a first input coupled to the output of said signal limiting means, a second input responsive to said reference signal, and an output.
a controlled oscillator (20) coupled to the output of said second frequency comparison means and providing an output signal to the second input of said first frequency comparison means; and wherein the phase locked loop circuit is arranged to lock in one stable state in response to reception ofthe upper sideband and to lock in the other stable state in responseto reception ofthe lower sideband.
2. A radio receiver as claimed in claim 1 and further comprising
band passfiltering means (10) having an input fed from the output of said first frequency comparison means and providing a filtered output signal;
amplifying means (12) having an input responsive to said filtered output signal and providing an amplified output signal to the input of said signal limiting means; and
additional filtering means (18) fed from the output of said second frequency comparison means and providing an inputto said voltage controlled oscillator.
3. A radio receiver as claimed in claim 1 wherein said controlled oscillator is a voltage controlled oscillator.
4. A radio receiver as claimed in any preceeding claim and including analogue data recovery means having an input coupled to the output of said second frequency comparison means for providing a demodulated output signal.
5. A radio receiver as claimed in any one of claims 1 to 3 and further comprising means (24) for shifting the phase of said reference signal to produce a phase-shifted reference signal;
phase comparison means (30) having a first input fed from the output of said signal limiting means, a second input responsive to said phase-shifted reference signal, and an output for providing a demodulated output signal.
6. A radio receiver as claimed in claim 5 and having outputfiltering means (32) responsive to the demodulated output signal fed from the phase comparison means for providing a filtered output signal.
7. A radio receiver as claimed in claim 5 wherein the meansforshifting the phase of the reference signal shifts said reference signal approximately ninety degrees.
8. A radio receiver as claimed in any one of claims
1 to 3 and further comprising a D-type latch having its
D input coupled to the output of said signal limiting means, its clock input responsive to said reference signal, and operative to provide a demodulated output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08215413A GB2122437B (en) | 1982-05-26 | 1982-05-26 | Fsk receiver with twin stable state pll |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08215413A GB2122437B (en) | 1982-05-26 | 1982-05-26 | Fsk receiver with twin stable state pll |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2122437A true GB2122437A (en) | 1984-01-11 |
| GB2122437B GB2122437B (en) | 1986-03-19 |
Family
ID=10530650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08215413A Expired GB2122437B (en) | 1982-05-26 | 1982-05-26 | Fsk receiver with twin stable state pll |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2122437B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2137836A (en) * | 1983-04-06 | 1984-10-10 | Multitone Electronics Plc | FM Demodulators |
| EP0153835A2 (en) * | 1984-03-01 | 1985-09-04 | Stc Plc | Radio receiver |
| EP0160339A2 (en) * | 1984-04-30 | 1985-11-06 | Philips Electronics Uk Limited | Improvements in or relating to direct modulation FM data receivers |
| US4580101A (en) * | 1983-04-06 | 1986-04-01 | Multitone Electronics Plc | FM demodulators with local oscillator frequency control circuits |
| FR2674388A1 (en) * | 1991-03-21 | 1992-09-25 | Samsung Electronics Co Ltd | Bias stabilisation circuit for a personnel paging receiver |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1394967A (en) * | 1972-09-25 | 1975-05-21 | Westinghouse Electric Corp | Modulation and noise analyzer |
| GB1553852A (en) * | 1975-03-14 | 1979-10-10 | Siemens Ag | Superheterodyne receivers |
-
1982
- 1982-05-26 GB GB08215413A patent/GB2122437B/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1394967A (en) * | 1972-09-25 | 1975-05-21 | Westinghouse Electric Corp | Modulation and noise analyzer |
| GB1553852A (en) * | 1975-03-14 | 1979-10-10 | Siemens Ag | Superheterodyne receivers |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2137836A (en) * | 1983-04-06 | 1984-10-10 | Multitone Electronics Plc | FM Demodulators |
| US4580101A (en) * | 1983-04-06 | 1986-04-01 | Multitone Electronics Plc | FM demodulators with local oscillator frequency control circuits |
| EP0153835A2 (en) * | 1984-03-01 | 1985-09-04 | Stc Plc | Radio receiver |
| EP0153835A3 (en) * | 1984-03-01 | 1986-05-14 | Stc Plc | Radio receiver |
| EP0160339A2 (en) * | 1984-04-30 | 1985-11-06 | Philips Electronics Uk Limited | Improvements in or relating to direct modulation FM data receivers |
| EP0160339A3 (en) * | 1984-04-30 | 1988-01-07 | Philips Electronic And Associated Industries Limited | Improvements in or relating to direct modulation fm data receivers |
| FR2674388A1 (en) * | 1991-03-21 | 1992-09-25 | Samsung Electronics Co Ltd | Bias stabilisation circuit for a personnel paging receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2122437B (en) | 1986-03-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5003621A (en) | Direct conversion FM receiver | |
| US4528522A (en) | FM Transceiver frequency synthesizer | |
| US5771442A (en) | Dual mode transmitter | |
| CA1151735A (en) | Broadcast signal receiving system for directly recovering the modulating signal from a received modulated high frequency signal | |
| US6385442B1 (en) | Multiphase receiver and oscillator | |
| US5260671A (en) | Receiving circuit for demodulating an angle modulated signal | |
| US5079526A (en) | Frequency modulated synthesizer using low frequency offset mixed VCO | |
| JPS6313370B2 (en) | ||
| US7577215B2 (en) | Angle demodulation apparatus, local oscillation apparatus, angle demodulation method, local oscillation signal generating method, recording medium and computer data signal | |
| EP2315350B1 (en) | Digital phase locked loop | |
| US7233631B2 (en) | DC-offset correction circuit having a DC control loop and a DC blocking circuit | |
| EP0568939B1 (en) | FSK receiver | |
| GB2122437A (en) | FSK receiver with twin stable state PLL | |
| EP0363226A2 (en) | Coherent demodulating arrangement for use in digital radio communications system | |
| US5586147A (en) | Demodulation method using quadrature modulation | |
| US6622009B1 (en) | Radiotelephone transmitter/receiver | |
| US6782249B1 (en) | Quadrature signal generation in an integrated direct conversion radio receiver | |
| US6617932B2 (en) | System and method for wide dynamic range clock recovery | |
| US6137852A (en) | Phase detector circuit and method of phase detecting | |
| US4578706A (en) | Television synchronous receiver | |
| US5745004A (en) | FPLL with third multiplier in an AC path in the FPLL | |
| US6999529B1 (en) | Digital AM demodulator | |
| KR950010625A (en) | HDTV receiver | |
| US6023614A (en) | Method for decoding a suppressed-carrier modulated signal in the presence of a pilot tone, particularly for FM signals | |
| EP0222863B1 (en) | Fm feedback demodulator using injection-locked oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |