GB2121221A - Table-driven apparatus for data display and modification - Google Patents

Abstract

Data modification and display apparatus for use as an editing device has memory 103 containing a buffer 113 for storing data codes representing data to be modified, control data 115 including a state value 121 for controlling modification and display of data, and an editing table 111 containing editing instruction sequences for modifying the contents of the buffer, for modifying the control data, and for producing display codes; a terminal with a keyboard 109 for providing input codes and a screen display 107 for displaying visual representations in response to display codes; and a processor 105. For each input code received from the keyboard 109 the location of a corresponding editing instruction sequence in the editing table is determined. Editing instruction sequences are divided into sections corresponding to certain state values, and editing instructions including instructions to which the processor responds to altering the state value. The processor responds to the editing instructions by modifying the data codes in the buffer 113, or by modifying display codes applied to the display 107. The sections may also include a section containing instructions to be executed at the beginning of operation of the apparatus, and a section to be executed on termination of operation of the apparatus. More than one editing table 111 may be provided, and programs using data modification and display apparatus may select an editing table. <IMAGE>

Description

SPECIFICATION Table-driven apparatus for data display and modification Background of the invention 1. Field of the invention The present invention relates generally to data modification apparatus in a digital data processing system, and more specifically to apparatus in an input-output system including a terminal keyboard and a terminal display for displaying data to be modified by a user of the system, permitting a user to modify data by means of keystrokes from a terminal, and displaying the results of the modifications on a terminal display.

2. Description of prior art In the prior art, users of computer systems have modified data from a terminal by means of general-purpose editing programs and singlepurpose editing functions for specific applications.

General-purpose editing programs provide a broad array of functions for modifying data. Such programs work by receiving editing commands from a terminal. In response to an editing command, the editing program displays data, modifies data, and displays modified data. Many general-purpose editing programs have a macro capability, i.e., they allow users to make and execute macros, that is, programs consisting of sequences of editing functions. Such a macro capability thus provides a user with a way of making new editing functions out of combinations of editing instructions. Some general-purpose editing programs also provide ways of associating a macro with a key of a terminal, so that a user can execute the macro by means of a single keystroke. Using this capability, a user may make a general-purpose editing program serve a variety of special purposes.

However, the power of a general-purpose editing program is not without cost. A generalpurpose editing program requires a considerable amount of memory for its code, and commencing and terminating operation of a general-purpose editing program require a considerable amount of time. The size of a general-purpose editing program limits its usefulness in applications where memory is at a premium, for example in "smart" terminals, i.e., terminals having local memory and processing capabilities. The time required to commence and terminate operation of a general-purpose editing program is excessive in programs which do not have editing as their main purpose, but instead perform a few editing operations in the course of other operations.

Programs which perform a few editing operations are particularly common in interactive applications, that is, where a program responds to commands or data from a terminal. In order for the program to be useful, a user must be able to see what he has input into the terminal and must be able to modify his input if it is in error. Since time and space requirements of a generalpurpose editing program are excessive for such applications, the prior art has incorporated simple editing capabilities into many special-purpose programs. By so doing, the prior art has avoided overhead involved in using the general purpose editor, but has increased the complexity of special-purpose programs and has thereby made them more difficult to write and maintain.To some extent, too, including simple editing capabilities in special-purpose programs wastes memory space: each special-purpose program may require essentially the same editing functions, but because there are minor differences, the editing functions cannot be combined into a single program used by all.

The trend towards digital data processing systems whose components are connected into networks has increased the need for data display and modification apparatus which have the generality and availability of the general-purpose editors but do not have their overhead. In network systems, each transmission of data over the network involves considerable overhead, and consequently, efficiency requires as few transmissions as possible to accomplish a given task. One way to reduce the number of transmissions is to distribute processing capability throughout a system, for example, by providing terminals in a system with local microprocessors and memory. In such a system, modifications on data stored in a terminal's memory may be performed using the terminal's microprocessor.Consequently, modification of data such as a line of ASCII characters may require only two transmissions: one to transmit data to be modified to a terminal, and a second to transmit modified data from the terminal to other parts of the system.

Neither approach used by the prior art to data display and modification is advantageous is a network system. Both general-purpose editing programs and special-purpose programs containing data display and modification components are generally too large to fit into the limited memory available in an individual terminal, and individual editing commands must therefore be sent in separate transmissions from a terminal to the processor upon which the generalpurpose editing program or the special purpose program is executing. The separate transmissions contain far less data than the maximum amount which could be included in such a transmission, resulting in an inefficient use of the network.

In order to make more efficient use of a network, the art has provided limited data display and modification capabilities for individual terminals. In a terminal with such a capability, data display and modification is carried out by sending all of the data to be displayed and modified in a single transmission from a central processor to the terminal memory, performing modifications, and then returning modified data in a single transmission to the central processing unit. However, the price for efficient use of the network has been restricting all programs which use the terminal to a single set of data display and modification operations provided by the terminal.

The present invention provides improved data display and modification apparatus with features which solve the abovementioned problems of the prior art.

Summary of the invention The invention in its various aspects is defined in the appended claims.

A preferred data display and modification apparatus, termed herein an Editing Device (ED), embodying the invention, which requires only a limited amount of memory, provides powerful general-purpose cabilities, can be programmed to provide different users with different data display and modification capabilities, and is uniquely suited for use in networks.

An ED consists of the following elements: * a Display, such as a terminal screen, for displaying data; * Input Apparatus, such as a terminal keyboard, for inputting input codes describing data modifications and data to be used in modifications; * Memory at least for a Working Buffer for storing data codes representing the data to be modified and for Control Data used to control modification and display of data, * A Processor for modifying data in response to input codes and controlling display of data on the Display; and * an Editing Table containing table entries corresponding to one or more data codes or input codes.

Each table entry in an Editing Table consists of a sequence of editing instructions which control the manner in which the ED responds to a set of input or data codes. As prescribed by editing instructions, the ED may modify the contents of the Working Buffer, modify the display of data on the Display, or modify Control Data. Some embodiments of the ED may use a number of Editing Tables, and programs employing these embodiments may specify which Editing Table an ED is to obtain editing instructions from. In EDs in "smart" terminals, an Editing Table may be provided to the terminal along with the data the ED is to modify.

While an ED using a specific Editing Table is not as powerful as a general-purpose editor, the fact that an ED can use a variety of Editing tables gives it the generality of a general-purpose editor without the memory space requirements and time penalties inherent in general-purpose editors. The size of an ED makes it particularly adapted to use in a "smart" terminal, and the capability of receiving an Editing Table along with data gives "smart" terminals employing an ED more flexible editing capabilities than would otherwise be possible.

The preferred ED to be described in more detail below has the advantages of being more flexible and efficient than the known devices, and determines the manner in which the data display and modification apparatus responds to input codes and displays the data with the use of one or a plurality of Editing Tables. The apparatus is particularly suited to use in network systems.

Other advantages and features of the apparatus will be understood by those of ordinary skill in the art after referring to the following detailed description of the preferred embodiment and drawings.

Brief description of the drawings The preferred embodiment will now be described in more detail as an example of the invention, with reference to the drawings, in which: Fig. 1 is a block diagram of a digital computer system embodying the present invention; Fig. 2 is a diagram of an Editing Table and an Editing Instruction Sequence of the present invention; Fig. 3 is a block diagram of a first embodiment of the present invention in a digital data processing system with a single CPU; Fig. 4 is a block diagram of second embodiment of the present invention in a digital data processing system with a CPU and an Input Output Processor; Fig. 5 is a block diagram of a third embodiment of the present invention in a digital data processing system with a "Smart" Terminal;; Fig. 6 is a block diagram of a fourth embodiment of the present invention in a multiprogramming digital data processing system; Fig. 7 is a functional block diagram of the procedure EDITREAD-SYS-CALL in an embodiment of the present invention.

Fig. 8 is a hexadecimal representation of a specific Editing Table in an embodiment of the present invention.

Description of the preferred embodiments The following description of the preferred embodiments first presents an overview of the Editing Device (ED), then discusses various ways in which the ED may be incorporated into data processing systems, and finally discusses one embodiment of the ED in detail. In these discussions, parts of instruction sequences are often described as performing actions. In fact, of course, the actions are performed by the processor which executes the instructions. The usage which attributes the actions to the instruction sequences is common among those skilled in the art and is employed here for the sake of clarity of presentation.

1. Overview of the Invention-Figure 1 Figure 1 is a conceptual block diagram which provides an overview of the ED. Therein is shown ED 101, which receives data from Data Processing System (DP) 127, modifies the data, and returns it to DP 127. ED 101 is further connected to Input 109 and to Display 107. As indicated by arrows joining Interpreter 101 and Input 109 and Interpreter 101 and Display 107, Interpreter 101 receives input codes from Input 109 and outputs display codes to Display 107.

Input codes received from Input 109 direct the manner in which data received from DP 127 is to be modified and provide additional data to be used in modifying data received from DP 127, while Display 107 responds to display codes by displaying visual representations of that data as received from DP 127 and as modified in response to input codes from Input 109.

In most embodiments, both Input 109 and Display 107 are part of a terminal, Input 109 being the terminal's keyboard and Display 107 the terminal's CRT, or in the case of hard copy terminals, the paper upon which the terminal types its output. In a present embodiment, input codes are 1-byte (eight-bit) ASCII codes which the terminal produces in response to key strokes.

In other embodiments, input codes may be EBCDIC codes or special input codes, and input codes may be longer or shorter than 8 bits.

Similarly, in a present embodiment, display codes are ASCII codes, augmented by special display control codes, but other display codes, such as EBCDIC codes or special display codes, are possible.

2. Components of ED101 ED 101 has two main components: Memory 103 and Processor 105. Processor 105 provides addresses to Memory 103 and either fetches data from Memory 103 at a location specified by an address or stores data in Memory 103 at a location specified by an address. These addressing, fetching, and storing operations are indicated in Figure 1 by < and > symbols showing addresses being transmitted from Processor 105 to Memory 103 and data being transmitted in both directions. In addition, Processor 105 performs operations on data fetched from Memory 103, receives input codes from Input 109, and provides display codes for Display 107.

2.1 Memory 103 Memory 103 contains data codes to be modified by ED 101 in response to input codes received from Input 109, one or more Editing Tables containing instructions directing modification and display of visual representations of data codes before and after modification on Display 107, and control data used to control ED 101. In Figure 1, various kinds of information contained in Memory 103 are indicated by dashed boxes. Flow of information between DP 127, Memory 103, and Processor 105 is indicated by arrows between DP 127, Processor 105 and the boxes representing the information.

Turning first to Working Buffer 1 13. Working Buffer 11 3 contains data codes received for display and/or modification from DP 127. As indicated by arrows between Working Buffer 11 3 and DP 127 and between Working Buffer 113 and Processor 105, Working Buffer 113 receives data codes from DP 127 at the beginning of the operation of ED 101 and returns data codes to DP 127 on termination of operation of ED 101.

During ED 101's operation, Processor 105 both reads data codes from and writes data codes to Working Buffer 113.

Control Data 11 5 contains data used to control Processor 105 as Processor 105 causes Display 107 to display the contents of Working Buffer 113 and modifies the contents in response to input codes from Input 109. Data in Control Data 115 may be provided from two main sources: Data in External Control Data (ECD) 117 may be provided by DP 127 at the beginning of operation of ED 101 and may be returned to DP 127 at the end of ED 101 's operation; Data in Internal Control Data (ICD) 119 is produced during the operation of ED 101.As the an arrow in Figure 1 indicates, Processor 105 may both read data from and write data to Control Data 11 5. Data contained in Control Data 115 includes State 121, a value which determines the location in Editing Table 111 from which ED 101 obtains editing instructions corresponding to a specific input code from Input 109, BI 123, a value which specifies a position in Working Buffer 11 3, and CP 126, a value which specifies a position of a cursor in Display 107. The cursor position so specified corresponds to the location specified by BI 123 in Working Buffer 11 3, and consequently, CP 126 is dependent on BI 123; whenever ED 101 changes the value of BI 123, it changes the value of CP 126.In embodiments of the present invention having more than one Editing Table 111 in Memory 103, ETID 125, finally, is a value specifying which Editing Table 111 ED 101 is currently using.

Editing Table 111 contains sequences of Editing Instructions which determine how Processor 105 modifies the contents of Working Buffer 113 and/or values in Control Data 115 in response to input codes from Input 109 and how Processor 105 causes Display 107 to respond to these modifications. Processor 105 may read Editing Instructions from Editing Table 111, but may not modify Editing Table 111. As specified by arrows in Figure 1, in some embodiments of the present invention, DP 127 may provide an Editing Table 111 to ED 101 at the beginning of operation of ED 101; in other embodiments, ED 101, Editing Tables 111 may be contained in read only memory belonging to ED 101.

2.2 Overview of Contents of Editing Table 111~Figure 2 Turning next to the overview of the contents of Editing Table 111 contained in Figure 2, it may be seen that Editing Table 111 in a present embodiment may have following parts: * Locator Information 201, containing information used by Processor 105 to locate Editing Instruction Sequences in Editing Table 111; * Dispatch Table 203, containing information used by Processor 105 to locate a set of Editing Instruction Sequences corresponding to a given value of State 121; * Initial Sequence 205, containing an Editing Instruction Sequence which is executed when ED 101 begins operation; * Final Sequence 207, containing an Editing Instruction Sequence which is executed when ED 101 finishes operation;; * Display Sequences 209, containing Editing Instruction Sequences corresponding to data codes contained in Working Buffer 113; * Buffer Editing Sequences 211, containing sets of Editing Instruction Sequences corresponding to values of input codes from * Input 109 and to values of State 121. As may be seen from Figure 2, all Editing * Instruction Sequences corresponding to a given value of State 121 are grouped together in a single Buffer Editing Sequences 213 for that value of State 121.

Editing Instruction Sequences contained in Buffer Editing Sequences 211 and Display Sequences 209 are represented by Editing Instruction Sequence 215 in Figure 2. In a present embodiment, Editing Instruction Sequence 215 is a sequence of bytes. The first two bytes, LV 219 and UV 221, define a range of 8-bit codes for which Editing Instruction Sequence 215 is valid; the third byte, Size 223, specifies the number of bytes in Editing Instruction Sequence 215 excluding LV 219, UV 221, and Size 223; the remaining bytes are Editing Instruction Bytes 225.

Editing Instruction Bytes 225 control response of Processor 105 to an input code input from Input 109 or a data code input from Working Buffer 113. Editing Instruction Bytes 225 may specify operation codes and operands. Operands may be variables, stored in Control Data 11 5, or they may be literal values.

Editing Instruction Sequences in Initial Sequence 205 and Final Sequence 207 resemble those of Display Sequences 209 and Buffer Editing Sequences 211, but have neither LV Byte 219, UV Byte 221, nor Size Byte 223.

3. Overview of the Operation of ED 101 Operation of ED 101 is initiated when DP 127 executes a program which performs operations requiring the use of ED 101. Under control of the program, DP 127 provides data codes for Working Buffer 113 and values for ECD 117 including at least a value for BI 123 specifying a location in Working Buffer 11 3. In embodiments having more than one Editing Table 111, ECD 117 may also include a value for ET-ID 125 specifying one of Editing Tables 111 available to ED 101.

When ED 101 begins operation, it first initializes State 121 to an initial value, 0, and then locates Initial Sequence 205 in Editing Table 111 and executes all Editing Instructions contained in Initial Sequence 205. Next, ED 101 displays the contents of Working Buffer 113 on Display 107. It does so by retrieving data codes placed in Working Buffer 11 3 one at time and for each data code, locating Editing Instruction Sequence 225 in Display Sequences 209 corresponding to that data code. It then executes that sequence in Display Sequences 209 and responds thereto by producing one or more display codes corresponding to that data code. Display 107 then produces a visual representation in response to the display codes.For example, if a data code is one representing a printable ASCII character, Editing Instruction Sequence 225 for those characters produces a display code for that character. Other cases are more complicated; for example, Editing Instruction Sequence 225 corresponding to the ASCII tab character causes ED 101 to produce the number of blank display codes required to reach a position in Display 107 corresponding to the next tab stop. When ED 101 is finished, Display 107 shows a representation of the contents of Working Buffer 11 3, including a cursor at the position on Display 107 corresponding to the location specified by BI 123 in Working Buffer 113.

ED 101 is now ready to begin receiving input codes from Input 109, modifying the contents of Working Buffer 109 and values in Control Data 11 5 in accordance with these codes, and displaying the results of these modifications on Display 107.

In the following, three operations of varying degrees of complexity are described. The first of these operations, Move, changes the values of BI 123 and CP 126 and moves a cursor in Display 107 to a position corresponding to BI 123 and CP 126. The second, Search, locates a data code in Working Buffer 113, changes the values of BI 123 and CP 126 to specify the location of the data code, and moves a cursor in Display 107 to the position of the data code. The third, Insert, inserts data codes in Working Buffer 11 3 at the position specified by the cursor and displays the modified contents of Working Buffer 11 3 on Display 107.

3.1 A Move Operation To perform a Move operation, for example, one which moves the cursor one position to the right on Display 107 and changes the values BI 123 and CP 126 to correspond to the new cursor position, a user of a keyboard version of Input 109 strikes a move cursor key. In striking that key, the user sends an input code corresponding to the key to ED 101. Processor 105 receives the input code, and using that input code and the current value of State 121, namely 0, it locates an Editing Instruction Sequence 21 5 for that input code in Buffer Editing Sequences for State=0 213.

Editing Instruction Sequence 215 thus located contains instructions which cause ED 101 to modify the value of BI 123 to indicate a position one data code to the right in Working Buffer 113.

Next, ED 101 updates Display 107 to reflect the change in the value of Bl 123 by displaying a display code corresponding to the data code at the previous position of BI 123, display codes corresponding to all data codes between the previous and new position of BI 123, and a display code corresponding to a data code at the new position of BI 123. The display codes are produced by taking each data code from Working Buffer 11 3 and for each data code, executing an Editing Instruction Sequence 215 corresponding to that data code in Display Sequences 209.Each time an Editing Instruction Sequence 215 for a printable display code is executed, ED 101 changes the value of CP 126, so that at the end of a display operation, CP 126 indicates the location of the visual representation on Display 107 corresponding to a data code in Working Buffer 113 specified by BI 123. At the end of a display operation, a visual representation of a cursor is output to Display 107 at the location specified by the value of CP 126. Thus, at the end of a Move operation, a cursor is at the desired location in Display 107 and the values of BI 123 and DP 126 correspond to that location.

3.2 A Search Forward Operation The search operation discussed herein is a Search Forward operation. This operation searches Working Buffer 113 forward from a current cursor position until it finds a data code corresponding to an input code provided in the Search Forward operation. To perform a Search Forward operation, the user makes two keystrokes: one, of a search key specifying the operation, and another of a key specifying the input code corresponding to the data code to be searched for.

Editing Instruction Sequence 215 corresponding to the input code produced by the search key is also in the portion of Buffer Editing Sequences 211 for State=0. In response to this Editing Instruction Sequence 215, ED 101 sets State 121 to a predetermined value. ED 101 then fetches the next input code, that specifying a data code to be searched for. However, since the value of State 121 has been changed, ED 101 locates Editing Instruction Sequence 215 corresponding to the input code not in Buffer Editing Sequences 213 for State=O, but instead in Buffer Editing Sequences 213 for the current value of State 121.Editing Instruction Sequence 215 at that location contains instructions to which ED 101 responds by starting at the current cursor position and working forward, comparing data codes from Working Buffer 11 3 with a data code corresponding to the input code which specified the data code to be searched for. If ED 101 finds a matching data code in Working Buffer 113, it resets BI 123 to the location of that data code in Working Buffer 113 and then displays visual representations of the data codes in the searched area of Working Buffer 113 in the manner described for a Move operation on Display 107, and finally resets State 11 5 to 0. Thus, at the end of a Search Forward operation, BI 123, CP 126, and a cursor on Display 107 all specify the location of the character being searched for.

An Insert Operation In an Insert operation, finally, a sequence of data codes specified by input codes is inserted in Working Buffer 11 3 at the position specified by the cursor. A user of Input 109 may perform the operation by striking an insert key to begin the operation, then striking keys for the input codes corresponding to the data codes being inserted, and finally striking the insert key again to end the operation.

ED 101 may respond to the keystrokes as follows: First, an editing instruction sequence corresponding to the input code provided by the insert key sets a variable in Control Data 11 5 to indicate that an insert operation is going on and then redisplays the contents of Working Buffer 113 on Display 107. As part of the display operation, ED 101 may check the value of the variable indicating an insert operation, and if the variable indicates that one is going on, ED 101 may modify the display on Display 107 to indicate that an insert operation is in progress. For example, in some implementations, a display may have a "hole" at the cursor for the insertion of new characters, and in others, a display may dim the character at the point of insertion.

A user next hits keys on Input 107 corresponding to the characters he wishes to insert. Since Editing Instructions 225 for the insert input code do not reset State 121, Editing Instruction Sequence 215 which performs the actual insert operation is in Buffer Editing Sequences 213 for State=0. ED 101 responds to that Editing Instruction Sequence 215 by inserting a data code corresponding to the input code at a location specified by BI 123 in Working Buffer 113, updating BI 123 to specify the position following the inserted character, and redisplaying any affected portion of Working Buffer 11 3 on Display 107 as previously described. When the user has finished inserting characters, he again strikes the insert key. This time, the operation performed is the reverse of the one previously described.Since the variable in Control Data 11 5 indicates that an insert operation is going on, ED 101 sets it to indicate that it is not. Then ED 101 redisplays the contents of Working Buffer 113 on Display 107. Since no insert operation is going on, the display on Display 107 no longer shows a "hole" or a dimmed character at the cursor.

A user of Input 109 indicates that he has finished using ED 101 by striking a key of Input 109 which produces a delimiter input code. A delimiter input code is one which is defined in Editing Table 111 as one which marks the end of a use of ED 101. Typical delimiter input codes might be the ASCII new line or carriage return codes. In response to Editing Instruction Sequence 215 for a delimiter input code, contained in Buffer Editing Sequences 213 for State=O, ED 101 ceases fetching input codes from Input 109, executes Editing Instruction Bytes 225 in Final Sequence 207, and indicates to DP 127 that it is finished modifying Working Buffer 113.

4. Alternative Embodiments of ED 101 ED 101's two main components are Processor 105 and Memory 103. In actual digital data processing systems, Processor Means 105 and Memory 103 may be implemented on a variety of components of the data processing system. Some of the implementations are the following: ED 101 in a System with a Single CPU and a Single Memory In digital data processing systems with a single CPU and a single memory accessible from the CPU, the single CPU serves as Processor 105 and that CPU's memory as Memory 103. This embodiment is presented in Figure 3.

ED 101 in a System with CPU, IOP, and Shared Memory In digital data processing systems with two processors sharing a single memory, one a general-purpose CPU and the other an Input/Output Processor (IOP), a special-purpose processor dedicated to handling input/output, the IOP serves as Processor 105 and the shared memory serves as Memory 103. Such an embodiment is illustrated in Figure 4.

ED 101 in "Smart" Terminals In digital data processing systems, finally, with "smart" terminals, each terminal contains its own processor and memory. The terminal processor then functions as Processor 105 and the terminal memory as Memory 103. An example of such an embodiment is shown in Figure 5.

In the following, each of the above embodiments is described in detail. Embodiments of ED 101 in digital data processing systems other than those described above will be obvious to those skilled in the art.

4.1 ED 101 in a System having a Single CPU and a Single Memory-Figure 3 Figure 3 shows an embodiment of ED 101 in a digital data processing system having a single CPU 303. CPU 303 executes instructions stored in Memory 313. In response to these instructions, CPU 303 produces addresses of data and instructions in Memory 313, fetches data and instructions to CPU 303, and writes data to Memory 313. CPU 303 further generates control signals for Terminal 305, which responds to the control signals in two ways: Terminal 305 displays visual representations corresponding to the display codes in Display Buffer 309 in Memory 313, and it writes data input to Terminal 305 to Input Code Buffer 311.Taken together therefore, Display Buffer 309 and Terminal 305 are equivalent to Display 107, while Input Code Buffer 311 and Terminal 305 are equivalent to Input 109. Memory 313 further contains at least one Editing Table 111, Working Buffer 113 and Control Data 11 5. In addition, it contains ED Instruction Sequence 307. ED Instruction Sequence 307 is a sequence of instructions to which CPU 303 responds. When executing these instructions, CPU 303 responds to keystrokes from Terminal 305 in the manner described for Processor 105 in ED 101, and consequently, when CPU 303 is executing ED Instruction Sequence 307, Single-processor System 301 functions as an ED 101.

4.2 ED 101 in a System with an lOP-Figure 4 Figure 4 illustrates an embodiment of ED 101 in a Digital Data Processing System 401 with two processors, an IOP 403 and a CPU 303, sharing a single Memory 313. Both lOP 403 and CPU 303 execute instructions stored in Memory 313. CPU 303 and IOP 403 divide the tasks involved in executing a program. CPU 303 responds to its instructions by reading data from Memory 313, processing it, and returning it to Memory 313.

lOP 403, on the other hand, controls devices such as Terminal 305 and responds to its instructions by transferring data between such devices and Memory 313.

IOP 403 and CPU 303 may coordinate their operations by means of signals between CPU 303 and IOP 403 and by means of areas in Memory 313 containing messages from CPU 303 to IOP 403 and vice-versa. In such a system, CPU 303 and IOP 403 cooperate to perform input/output operations as follows: when a User Program 404 executing on CPU 303 specifies an input-output operation, CPU 303 responds to the program by placing a message for IOP 403 in CPU-IOP Messages 411, signalling IOP 403 via CPU-IOP Signals 415, and suspending execution of the program which specified the input-output operation.The message in CPU-IOP Messages 411 specifies at least the operation which IOP 403 is to perform for CPU 303 and the locations in Memory 313 from or to which IOP 403 is transfer data. When IOP 403 receives the signal from CPU 303, it begins performing the operations specified in CPU-IOP Messages 411.

When IOP 403 is finished, it puts a return message for CPU 303 in IOP-CPU Messages 409 and then signals CPU 303 via IOP-CPU Signals 417. CPU 303 responds by resuming execution of User Program 404 which specified the execution of the input-output operation.

When IOP 403 and Memory 313 are being used to implement ED 101, Memory 313 contains Working Buffer 113, Editing Table 111, Display Buffer 309, Input Buffer 311, ED Instruction Sequence 307, ICD 119, and ECD 11 7. As the arrows in Figure 4 indicate, both CPU 303 and IOP 403 may read data from and write data to Working Buffer 113 and ECD 117. CPU 303 writes data to CPU-IOP Messages 411 and reads it from IOP-CPU Messages 409. IOP 403 alone reads Editing Instruction Sequences 215 from Editing Table 111, reads and writes data to ICD 11 9, writes data to IOP-CPU Messages 409, uses Display Buffer 309 and Input Buffer 311, executes ED Instruction Sequence 307, and controls Terminal 305.

In an embodiment of ED 101 like the one just described, ED 101 may operate as follows: When User Program 404 executing on CPU 303 performs an operation involving ED 101, instructions in User Program 404 cause CPU 303 to place data to be modified by ED 101 in Working Buffer 113 and information controlling the modification in ECD 117. CPU 303 then places a message for IOP 403 in CPU-IOP Messages 411 and signals IOP 403. Message 41 9 contains at least three items: a program identifier (PR-ID) specifying that IOP 403 is to execute instructions in ED Instruction Sequence 307 and two pointers to the data to be used in the execution. The first pointer, EC-PTR contains the location of ECD 11 7 and the second, WB-PTR, contains the location of Working Buffer 113.In embodiments having more than one Editing Table 111, Message 419 may further contain ET-ID, specifying an Editing Table 111.

IOP 403 then responds to the signal from CPU 303 by executing ED Instruction Sequence 307 using Working Buffer 113, EDC 117, and Editing Table 111 specified in the message from CPU 303. The execution proceeds as previously described. When IOP 403 is finished executing ED Instruction Sequence 307, it places a message indicating that it is finished in IOP-CPU Messages 409 and signals CPU 303 via CPU Signals 417.

4.3 ED 101 in a "Smart" Terminal-Figure 5 Figure 5 presents an embodiment of ED 101 in a "smart" terminal, that is, in a terminal which contains its own processor and memory. In systems with "smart terminals", there is a CPU 303 and a Memory 313, and CPU 303 is connected to one or more "Smart" Terminals 502. The connection between CPU 303 and a "Smart" Terminal 502" allows CPU 303 to send control signals and data to "Smart" Terminal 502 and to receive control signals and data from "Smart" Terminal 502. "Smart" Terminal 502 includes not only Display 107 and Input 109, but also Terminal Processor 503 and Terminal Memory 505.

Terminal Processor 503 executes instructions stored in Terminal Memory 505. In response to these instructions, Terminal Processor 503 produces addresses of data and instructions in Terminal Memory 505, fetches data and instructions to Terminal Processor 503, writes data to Terminal Memory 505, obtains input codes from Input 109, and controls Display 107.

In addition, Terminal Processor 503 responds to control signals from CPU 303, receives data from CPU 303, and provides data to CPU 303.

Computer System with a "Smart Terminal" 501 may operate as follows: When a User Program 404 executing on CPU 303 performs an operation requiring "Smart" Terminal 502, it may make a Terminal Message 513 containing a Program Identifier (PR-ID) identifying the operation to be executed by "Smart" Terminal 502 and the data to be used. Since the data will be worked on in Terminal Memory 505 instead of Memory 313, the data is identified by offsets from Terminal Message 513 instead of addresses in Memory 313. CPU 303 may then signal Terminal Processor 503 that data is coming and transmits Terminal Message 513 and data associated with it to Terminal Processor 503. The data is transmitted in an order corresponding to the offsets, and Terminal Processor 503 loads Terminal Message 513 and the data into Terminal Memory 505 beginning at a known location and in the order in which it is received.By adding the offsets to the location at which the Terminal Message 513 was loaded, Terminal Processor 503 can locate the contents of Terminal Message 513 in Terminal Memory 505. When Terminal Processor 503 has received all data specified in Terminal Message 513, it performs the operation specified by PR-ID in Terminal Message 513.

When it is finished, it signals CPU 303 that data is coming and returns the data.

In embodiments of ED 101 in a System with a "Smart" Terminal 501, Terminal Memory 505 may contain ED Instruction Sequence 307, Table 111, and ICD 119. User Program 404 executing on CPU 303 may then use ED 101 by preparing a Terminal Message 513 whose PR-ID specifies ED Instruction Sequence 307 and which contains offsets specifying locations of ECD 11 7 and Working Buffer 11 3 relative to Terminal Message 513. CPU 303 then transmits Terminal Message 513, Data for External Control 509, and Data to be Edited 507 to "Smart" Terminal 502.In Terminal Memory 505, Data for External Control is in the location specified in Terminal Message 513 for ECD 117 and Data to be Edited 507 is in the location specified in Terminal Message 513 for Working Buffer 11 3. "Smart" Terminal 502 then executes ED Instruction Sequence 307 using Data to be Edited 507 and Data for External Control 509 and returns that data to CPU 303 when it is finished.

As was the case with other embodiments of ED 101, some embodiments of ED 101 in "Smart" Terminals 502 may employ several Editing Tables 111. In such embodiments, ECD 11 7 may further contain ET-ID 125 specifying a specific Editing Table 111. Terminal Memory 505 may contain several Editing Tables 111 and the Editing Table 111 specified by ET-ID 125 may be one of those tables. If it is not, then Editing Table 111 specified by ET-ID 125 may be obtained from Memory 313. The mechanism for obtaining Editing Table 111 from Memory 313 may vary. In some cases, for example, in packet networks, where the cost of sending a single packet of data is the same regardless of whether the packet is full, CPU 303 may always send the Editing Table 111 specified by ET-ID 125 to "Smart" Terminal 502 along with Data to be Edited 507 and Data for External Control 509.In others, Memory 313 may contain a table specifying which Editing Tables 111 each "Smart" Terminal 502 has in its Terminal Memory 505 and provide an Editing Table 111 only if the table indicates that one is required. In still others, ED Instruction Sequence 307 may contain a sequence of instructions to which Terminal Processor 503 responds by requesting the proper Editing Table 111 from CPU 303 if it is not available in Terminal Memory 505.

Of course, digital data processing systems having lOPs 403 may also have "Smart" Terminals 502. In such systems, lOP 403 has the same relationship to a " Smart" Terminal 502 as CPU 330 in the system just described. The main difference between the systems is that IOP 403 may not produce Terminal Message 513, but may instead receive it from CPU 303 with which IOP 403 is associated.

4.4 Embodiments of ED 101 on Multiprogramming Systems In the implementations of ED 101 dealt with up to this point, ED 101 has been implemented by means of physical processors and memories.

However, in a multiprogramming digital data system, ED 101 may also be embodied by means of a process. In the following, multiprogramming systems and processes are described, and then an embodiment of ED 101 in a multiprogramming system.

4.4.1 Multiprogramming Digital Data Systems and Processes A multiprogramming digital data system is a digital data system which apparently executes programs for different users simultaneously. In such systems, each user has the illusion that he alone has access to the CPU and the memory, even though he is in fact sharing the CPU and the memory with other user. A process is the means by which a multiprogramming digital data system executes a program for a user. Each process consists of an area of memory associated with an execution of a program for a user. The area of memory contains values required to execute the program on the CPU.These values include at least a value specifying the location of the next instruction to be executed in the program being executed for the user and a value specifying a location in memory at which data currently being used in the execution of the program is stored. A multiprogramming digital data processing system may further contain a program called the process manager to which the CPU responds by loading values required to execute a given process from the area of memory belonging to the process into the CPU. Once the values are loaded, the CPU begins to execute the program for the user at the location specified in the process's area of memory. As execution continues, the value specifying the location of the next instruction to be executed and the value specifying the location in memory currently being used to store data change.After execution has continued for a while, a process interrupt may occur, either because the process has run for the maximum amount of time allowed it for a single turn on the CPU or because the program the process is executing has performed an operation such as an I/O operation for which it must await the results. On such a process interrupt, the CPU may automatically execute process manager instructions, and these instructions unload the process from the CPU, that is, they return the value for the location currently being used to store data and the value for the current location of the next instruction to be executed to the process's area in memory.

Process manager instructions then load equivalent values from another process's memory area into the CPU and that process's program is executed as just described. Thus, each process in turn may gain access to the CPU, and while it has access, the execution of its program progresses.

Since many processes may have turns on the CPU over a short period of time, the CPU seems to users of the system to be executing a number of programs simultaneously.

Processes may communicate with each other by means of Interprocess Messages (IPMs). These may resemble the messages between physical processors already described. When one process wishes another process to perform an operation for it, the first process may make an IPM specifying the operation and the data it is to be performed on for the second process and may indicate to the process manager than the second process has an IPM. The process manager then removes the first process from the CPU and from the set of processes which may have access to the CPU and adds the second process to the set of processes which may have access to the CPU.

When the second process is loaded onto the CPU, it performs the operation specified in the message. When it is finished, it sends a return IPM to the first process indicating that the operation is finished, and on the receipt of the IPM, the process manager again allows the first process to have access to the CPU.

Processes may have specialized functions; for example, one process may manage all inputoutput devices. Such a process is sometimes termed a Peripherals Manager (PMGR) process.

Other processes wishing to use these devices send IPMs to the PMGR process, which then executes programs which cause the input-output devices under its control to perform the operations specified in the IPMs on the data specified in the IPMs.

Processes may also exist on digital data processing systems with more than one processing unit. For example, in a digital data processing system with several CPUs, each CPU may be executing a different process. In a digital data processing system with an IOP, a PMGR process described above may execute solely on an IOP, and in a digital data processing system with "smart" terminals, each terminal may be treated as a separate process. In such systems, Terminal Message 513 may be equivalent to an IPM.

4.4.2 ED 101 in a PMGR Process-Figure 6 Since the relationship between processes is the same regardless of a process's function or which processing unit it executes on, the only embodiment of ED 101 on a multiprogramming digital data processing system explored in detail herein is one in which ED Instruction Sequence 307 is executed by a PMGR process. Such an embodiment is a logical consequence of the fact that the PMGR process controls terminals.

Figure 6 is a representation of an ED 101 embodied in a Multi-programming System 601 having a PMGR process. Multi-programming System 601 comprises Memory 313, CPU 303, and at least one Terminal 305. Memory 313 in a multi-programming system may contain Process Manager Instruction Sequence 603, which contains instructions executed by CPU 303 in order to store one process and load another, and Process Manager State 605, which contains data used during the execution of Process Manager Instruction Sequence 603 to determine which process is to be loaded onto CPU 303. Data in Process Manage State 605 may include an Active List 602 indicating which processes may be currently loaded onto CPU 303, an Inactive List 604, indicating which processes may not be currently loaded onto CPU 303, and a Message Flag 606, indicating whether an IPM has been sent.Memory 313 further contains instruction sequences executed by processes and the processes themselves. Instruction sequences are represented in Figure 6 by User Program 404, ED Instruction Sequence 307, and IPM Instruction Sequence 623. IPM Instruction Sequence 623 is executed by every process which sends an IPM.

Processes are represented by User Process 609 and PMGR Process 621. Each Process contains at least PC 610, specifying the next instruction to be executed by the process when it is loaded into CPU 303, and DATA 612, specifying the location of the data currently being used. User Process Data 608 indicates data specified by DATA 612 for User Process 609, and PMGR Process Data 622 indicates data specified by DATA 612 for PMGR Process 621.

Registers in CPU 303 contain Process Execution State 611 for the process currently being executed and Process Manager State 617 for the Process Manager. At a minimum, Process Execution State 611 contains CUR-PC 613, which is the location of the instruction currently being executed and CUR-DATA 615, which is the location which the process currently being executed is using for data. Process Manager State 61 7 contains information which allows CPU 303 to automatically execute Process Manage Instruction Sequence 603 whenever the execution of the process whose CUR-PC value and CUR-DATA value are currently loaded into Process Execution State 611 is interrupted.

In Figure 6, User Process 609 has just executed instructions in User Program 404 which have set up Working Buffer 113 and ECD 117 for ED 101 in User Process Data 608. Since ED 101 is executed by PMGR Process 621, User Process 609 has also executed IPM Instruction Sequence 623 to create IPM 620 in IPC Data 619 and to set Message Flag 606 in Process Manager Data 605 to indicate that a message has been sent. IPM 620 contains at least WB-PTR, specifying the location of Working Buffer 11 3 in User Process Data 608, EC-PTR, specifying the location of ECD 11 7 in User Process Data 608, a process identified (PID) specifying the process for which the message is intended, in this case, PMGR Process 621, and PR-ID, identifying the program, in this case, ED Instruction Sequence 307, to be executed by PMGR Process 621.

Since a process sending an IPM cannot proceed until it has received an answer, IPM Instruction Sequence 623 contains instructions which produce an interrupt and cause CPU 303 to execute Process Manager Instruction Sequence 603, which in turn removes User Process 609 from CPU 303 by storing the values of CURR DATA 615 and CURR-PC 613 in DATA 612 and PC 610 respectively of User Process 609 and setting Inactive List 604 to indicate that User Process 609 is currently inactive.

Each time Process Manager Instruction Sequence 603 executes, it checks Message Flag 606 to determine whether messages has been added to IPC Data 609. If any has been, Process Manager Instruction Sequence 603 examines IPC Data 61 9 for new IPMs 620 and adds the processes specified as the recipients of the IPMs, including in this case PMGR Process 621, to Active List 602. When an execution of Process Manager Instruction Sequence 603 results in PMGR Process 621 having access to CPU 303, PMGR Process 621 checks for an IPM in IPM Data 619. If PMGR Process 621 finds one, it begins executing the instruction sequence specified in the IPM on the data specified in the IPM. In this case, the IPM is IPM 620, which specifies ED Instruction Sequence 307, Working Buffer 113 in User Process 609, and ECD 11 7 in that process.

When CPU 303 begins executing ED Instruction Sequence 307, it adds storage for ICD 119, Display Buffer 309, and Input Buffer 311 to PMGR Process Data 622. Using this storage together with Working Buffer 11 3, External Control Data 413, and Editing Table 111 specified by ET-ID 125 in ECD 117, PMGR Process 621 responds to input codes from Terminal 305 in the manner previously described for ED 101. When PMGR Process 621 has finished executing ED Instruction Sequence 307, it sends an IPM to User Process 609 in the manner previously described.

5. Detailed Description of a Present Embodiment-Figure 7 In a present embodiment, ED 101 is implemented on a multiprogramming digital computer system with a single CPU 303. In this system, ED 101 in the present embodiment is executed by a User Process 609 instead of by PMGR Process 621. Consequently, instruction sequences executed by User Process 609 need not send an IPM 620 to perform an operation involving ED 101, but instead may simply execute ED Instruction Sequence 307 like any other sequence of instructions.

ED Instruction Sequence 307 in this embodiment is a sequence of instructions for CPU 303 produced by a PL/I compiler from a source program written in the PL/I programming language. Appendix A below contains a copy of this source program entitled EDITREAD-SYS CALL, and following EDITREAD-SYS-CALL, a copy of data declarations used in the source program. The data declarations carry the titles EXTENDED-READ, PACKET, and TERMINAL DATA. The remainder of the data declarations define names representing constant values and are not material to the present discussion. Figure 7 is a block diagram of the parts of EDITREAD SYS-CALL showing how the parts relate to each other and to the components of ED 101 contained in Memory 313. The parts and an overview of the operation of this embodiment of ED 101 will be presented using Appendix A and Figure 7.Having read the overview, those skilled in the art may determine the detailed operation of this embodiment by studying the source text of EDIT READ-SYS-CALL in Appendix A.

Beginning with the components of ED 101 contained in Memory 313, these components are referred to by means of variable names in EDIT READ-SYS-CALL. These variables are declared in EDITREAD-SYS-CALL itself and in the data declarations following EDITREAD-SYS-CALL in Appendix A. Turning first to the data declarations, these declarations fall into three groups: declarations for Editing Table 111 and locations therein under the title EXTENDED-READ, declarations for data which controls ED 101, under the title PACKET, and declarations for data which ED 101 requires to control Display 107, under the title TERMINAL-DATA.

5.1 Declarations for Editing Table 111 Turning first to data declarations under the title EXTENDED-READ, on page 2 of the data declarations, there may be seen data declarations for Editing Tables 111. The first data declaration, CHANNEL-DATA-ADDRESS, is a pointer to Editing Table 111, and thus corresponds to ET-ID 116 of ED 101. CHANNEL-DATA-ADDRESS has the PL/1 static external attribute, and will therefore be placed in an area in Memory 313 available to all PL/I programs executed by User Process 609. The remaining declarations are for Editing Table 111 itself and for variables specifying locations in a given Editing Table 111.

In those declarations, MACRO-TABLE corresponds to Initial Sequence 205, Final Sequence 207, Display Sequences 209, and Buffer Editing Sequences 211, and DISPATCH TABLE corresponds to Dispatch Table 203.

CHANNEL-DATA, finally, includes Locator Information 201 and other locations in Editing Table 111. The variables in Locator Information 201 are the following: * initial-macro-size specifies the number of bytes in Initial Sequence 205; * final-macro-size specifies the number of bytes in Final Sequence 207; * echo-macro-start specifies the offset in bytes of Display Sequences 209 from Initial Sequence 205; * echo-macro-size specifies the size in bytes of Display Sequences 209; * macro-table-size specifies the size in bytes of Buffer Editing Sequences 211; * . number-states specifies the number of values State 11 6 may have and therefore the number of Buffer Editing Sequences 211 in Editing Table 111.

The remaining variables specify locations in a given Editing Table 111: * macro-table-address is a pointer to the beginning of Initial Sequence 205; * dispatch-table-address is a pointer to the beginning of Dispatch Table 203.

As is apparent from the descriptions of these variables, the locations of the beginnings of Initial Sequence 205, Final Sequence 207, Display Sequences 209, and Buffer Editing Sequences 211 may be calculated using these variables.

5.2 Declarations for ECD 117 and ICD 119 Turning now to PACKET, on page 3 of the data declarations, there may be seen declarations for data passed to ED 101 on execution of ED Instruction Sequence 307. In this embodiment, the information contained in the packet corresponds to portions of ECD 117 and ICD 119.

The parts of the packet which are of interest for the present discussion are the following: * channel is a value which specifies Input 109 from which ED 101 is to receive input codes and Display 107 to which ED 101 is to output display codes.

* BUFFER-ADDRESS is a pointer to the location of Working Buffer 113 in Memory 313 * + USER-ARRAY-ADDRESS is a pointer to a location in Memory 313 containing an array of variables which ED 101 may read or modify in response to Editing Instructions 225. Different Editing Tables 111 may use these variables for different purposes. USER ARRAY-SIZE specifies the size of this array.

Editing Instruction Sequences 215 in Editing Table 211 may explicitly specify that the next group of variables, marked by the comment, /* R/W vars start here */, be read or modified during execution of the Editing Instruction Sequence 215 by ED 101. These variables have the following meanings: * VO is a general-purpose variable.

* w insert-mode's value determines the manner in which the results of an insert operation are displayed on Display 107.

* delimiter-length specifies whether the delimiter code is made up of one or two input codes.

* delimiter contains one or two input codes which specify a delimiter for a given execution of ED 101.

* state corresponds to State 121.

* status-code is used to return error status codes to programs using interpreter 101.

* buffer-index corresponds to B-I 1 23.

* max-buffer-size specifies the maximum size of Working Buffer 113.

Editing Instruction Sequences 215 may not explicitly specify the modification of the remaining variables, but the variables may change their values as a consequence of an execution of an Editing Instruction Sequence 215.

* field-size specifies the size of the field in Display 107 in which the visual representations corresponding to the contents of Working Buffer 11 3 are to be displayed on Display 107.

* already-displayed indicates whether the contents of Working Buffer 11 3 have already been displayed on Display 107.

* attribute-state specifies what display attributes representations being displayed on Display 107 have. Examples of display attributes are underscored representations, dim representations, bright representations, or colored representations.

* buffer-length specifies the number of data codes currently contained in Working Buffer 113.

* cursor-pos is equivalent to CP 126.

* char contains the input code received from Input 109.

* echo-index is the index on Display 107 of the representation currently being displayed.

The next group of variables serve to locate representations of data on Display 107. Locations on Display 107 are defined in terms of horizontal lines and vertical columns.

* visible-eol indicates a column in which a line being currently displayed on Display 107 ends.

* field-vert specifies a line making up a display field on Display 107; * field-horizontal specifies the column at which the display field begins on Display 107.

PACKET-OVERLAY 2 is a variable which occupies the same location in Memory 11 3 as PACKET, but which allows the contents of PACKET to be referenced as array elements.

OPERATOR-DiSPATCH-TABLE, finally, is an array which is used to translate codes contained in Editing Instruction Bytes 225 into case values which determine how EDITREAD-SYS-CALL responds to the codes. The values assigned to the elements of OPERATOR-DISPATCH-TABLE in the declaration remain unchanged throughout the operation of EDITREAD-SYS-CALL.

5.3 Declarations for Display 107 Turning finally to page 8 of the declarations, titled TERMINAL-DATA, this data is used by EDIT READ-SYS-CALL to control Display 107: * LPP and CPL specify the number of lines per page and columns per line which are available to Display 107; * CURSOR-TYPE specifies the type of cursor which terminals supporting more than one cursor type should employ; * CURRENT-ROW and CURRENT-COL specify the current row and column positions of the cursor on Display 107.

5.4 Declarations for ICD 119 in EDITREAD SYS-CALL The remainder of ICD 11 9 is specified in data declarations in EDITREAD-SYS-CALL and in PL/I procedures contained therein. Variables declared in PL/I procedures are allocated storage on a PL/I stack in Memory 313 each time the procedure in which the variable is declared is invoked and the storage is accessible by means of a reference to the varaible only during the life of the invocation.

Since an invocation of the EDITREAD-SYS-CALL procedure itself lasts throughout the operation of ED 101, variables declared in that procedure are available throughout the operation of ED 101. Of these variables, only four groups are of interest to the present discussion.

Variables for Working Buffer 113 and Display Buffer 309 The first group, declared on page 2 of EDIT READ-SYS-CALL defines variables by means of which Working Buffer 113, the array of user variables, and Display Buffer 309 may be accessed. The storage for these variables is defined in terms of pointers received in the packet used to invoke EDITREAD-SYS-CALL, and consequently, the variable represents the area of Memory 313 specified by the pointer. Thus, the variable buffer is defined as the storage at the location specified by the pointer buffer-ptr, which contains the location of Working Buffer 11 3, and buffer therefore represents Working Buffer 11 3 in EDITREAD-SYS-CALL.Similarly, the variable user-array is defined as the storage at the location specified by the pointer USER-ARRAY-ADDRESS, and consequently, the elements of user-array represent those variables. OUTPUT-RING BUFFER, finally, holds codes for visual representations to be output to Display 107. It thus corresponds to Display Buffer 309.

Variables for this Embodiment's Internal Stack The second group forms a LIFO (last in-first out) data structure which this embodiment of ED 101 uses to store and retrieve data while it is interpreting Editing Instruction Bytes 225. This data structure, termed herein the interpreter stack, is represented in EDITREAD-SYS-CALL by the variable stack, declared on page 2. ED 101 can always access three items of data stored in stack: * stack-prev, the item of data in the stack which precedes the item currently at the top of the stack; * stack-top, the item of data currently at the top of the stack; * stack-next, the item of data into which the next value to be stored on the stack will be stored.

As may be seen from the declarations, the locations of these variables are defined in terms of a pointer variable, stack-ptr. Thus, by changing the value of stack-ptr, the locations in stack referenced by these variables may be changed.

The value of stack-ptr is changed each time data is added to or taken from stack. When data is added to stack, stack-ptr is incremented by one, so that stack-top represents the value just added and stack-prev the value previously represented by stack-top. When data is removed, stack-ptr is decremented by one, so that stack-top represents the value formerly represented by stack-prev.

Variables Controlling Fetching of Editing Instruction Bytes 225 The third group, declared in the procedure INTERPRET on page 4 of EDITREAD-SYS-CALL, consists of variables used in locating Editing Instruction Sequences 215 and controlling the fetching of Editing Instruction Bytes 225 from Editing Table 111.

* mstrt contains the location of the start of Editing Instruction Bytes 225 in Editing Instruction Sequence 215 currently being executed.

* mstop contains the location of the end of Editing Instruction Bytes 225 in Editing Instruction Sequence 215 currently being executed.

* limit contains the location of the# end of Buffer Editing Sequence 211 containing Editing Instruction Sequence 215 currently being executed.

* lower contains LV 219 from Editing Instruction Sequence 215 currently being executed.

* upper contains UV 221 from Editing Instruction Sequence 215 currently being executed.

* macro-index contains the index in Editing Instruction Sequence 215 of the byte currently being interpreted.

* byte contains the value of the byte currently being interpreted.

5.5 Description of EDITREAD-SYS-CALL~ Figure 7 Turning now to Figure 7, Figure 7 is a block diagram showing the parts of EDITREAD-SYS CALL, the relationship between the parts of EDIT READ-SYS-CALL and other components of ED 101, and the flow of data and control between the parts of EDITREAD-SYS-CALL and between EDITREAD-SYS-CALL and other components of ED 101. Each block in Figure 7 represents a major part of EDITREAD-SYS-CALL. Each part consists of one or more PL/I procedures contained in EDIT READ-SYS-CALL. A broad arrow from one block to another indicates that at least some of the PVI procedures represented by the block which is the source of the arrow call procedures represented by the block which is the destination of the arrow.

In PVI a procedure may be invoked recursively, that is, by itself or by another procedure which it has invoked. Consequently, some arrows in Figure 7 indicate that a procedure in a block invokes itself. Inside each block are boxes indicating which parts of Editread 101's components in Memory 103 are used by a block. In the case of Control Data 11 5, each block uses different variables in Control Data 115 and consequently, only the names used to refer to the variables in EDITREAD-SYS-CALL are indicated in Figure 7; in the cases of the other components, both the name of the Editread 101 component and the variable name corresponding to the component in EDITREAD-SYS-CALL are indicated.

The following discussion first summarizes the functions of the blocks and then discusses each block in greater detail.

* ED Control 701 controls the execution of ED 101.

* Read Function 711 reads input codes from Input 109.

* Editing Table Interpreter 717 locates Editing Instruction Sequences 215 corresponding to an input code or a data code and a value of State 121 and interprets the Editing Instruction Bytes 225 in the Editing Instruction Sequence 215 so located.

* Buffer and Display Coordinator 729 coordinates operations on Working Buffer 11 3 and the display of the results of the operation on Display 107.

* Screen Control 713 controls the operation of Display 107.

* Working Buffer Control 731 controls the manipulation of data codes in Working Buffer 103.

5.5.1 ED Control 701 ED Control 701 corresponds to the main procedure EDITREAD-SYS-CALL. In this embodiment, operation of ED 101 commences with invocation of this procedure by a program using ED 101. The parts of ED Control 701 correspond to its function: Initial Control 707 performs operations involved in initiating the operation of ED 101, Control Loop 705 is a loop which causes ED 101 to keep fetching input codes from Input 109 until a delimiter code is received, and Final Control 703 performs operations involved in terminating the operation of ED 101. Variables whose values are set or read by ED Control 701 are indicated in ED Control State 705.

Operation of ED Control 701 commences when a user program using ED 101 invokes EDIT READ-SYS-CALL with a pointer to the packet of data defined in the variable PACKET. The PL/I code for ED Control 701 may be found on pages 3 through 5 of EDITREAD-SYS-CALL. Lines 370 through 413 contain the code for Initial Control 707, lines 422 through 427 contain the code for Control Loop 705, and lines 432 through 445 the code for Final Control 703.

5.5.2 Read Function 711 The block labelled Read Function 711 corresponds to the function read, on page 21 of EDITREAD-SYS-CALL. When this function is invoked by Control Loop 705, it fetches an input code from Input 109 and returns the input code to Control Loop 705. In this embodiment, an input code is fetched by means of a call to CPU 303's operating system. The operating system automatically associates an input buffer with a channel number and an input device, and the system call BINARY-READ-STRING fetches a byte from the input buffer associated with the channel.

Thus, in the read function, the variable channel, obtained from the packet used to invoke EDIT READ-SYS-CALL, specifies Input 109 and Input Buffer 311 from which the read function is to fetch an input code.

Before calling BINARY-READ-STRING to obtain the character, read calls flush-buffer, explained below, to cause Display 107 to display visual representations corresponding to display codes contained in Display Buffer 309. Then, after obtaining the byte from Input Buffer 311, the read function puts it into a proper format for ED 101 and returns it to Control Loop 705.

Screen Control 713 Screen Control 713 manages Display Buffer 309, corresponding to the variable OUTPUT RING-BUFFER, and by means of display codes contained in that buffer, Display 107. Two PL/I procedures put-chr and flush-buffer, both on page 22 of EDITREAD-SYS-CALL, perform the management. put-chr puts display codes into OUTPUT-RING-BUFFER, and flush-buffer uses the system call BINARY-WRITE-STRING to output the contents of OUTPUT-RING-BUFFER to Display 107 and empty the buffer. A component of BINARY-WRITE-STRING translates the contents of OUTPUT-RING-BUFFER into visual representations suitable for the specific Display 107 being used.

5.5.3 Editing Table Interpreter 717 Editing Table Interpreter 71 7 locates an Editing Instruction Sequence 215 corresponding to an input code or data code value and a value specifying a set of Editing Instruction Sequences 215 and then performs operations specified by individual bytes of Editing Instruction Bytes 225.

Editing Table Interpreter 71 7 is made up of the single INTERPRET procedure, on pages 4 through 12 of EDITREAD-SYS-CALL. An invocation of INTERPRET requires two pieces of data: an input code or a data code to be interpreted and a value specifying a portion of Editing Table 111. That value may be provided by State 121, or it may be a constant value.

As may be seen by the arrows in Figure 7, INTERPRET is invoked by all three subsections of ED Control 701, Buffer and Display Coordinator 729, and recursively by itself. INTERPRET is the only component of EDITREAD-SYS-CALL which reads Editing Table 111. Editing Table Interpreter 71 7 has two main subdivisions: Editing Instruction Fetcher 71 9 and Editing Instruction Interpreter 723.

Editing Instruction Fetcher 719 Editing Instruction Fetcher 719, on pages 4 and 5 of EDITREAD-SYS-CALL, first locates a set of Editing Instruction Sequences 215 in Editing Table 111 corresponding to the value provided for the invocation of INTERPRET and then locates an individual Editing Instruction Sequence 215 corresponding to the input code or data code value. Having located an Editing Instruction Sequence 215, Editing Instruction Fetcher 719 provides Editing Instruction Bytes 225 of Editing Instruction Sequence 215 one byte at a time to Instruction Interpreter 723. The manner in which Editing Instruction Fetcher 71 9 reads Editing Table 11 9 is controlled by Editing Instruction Fetcher State 721.As may be seen from Figure 7, this state consists of values sent to ED 101 in the packet CHANNEL-DATA and values used in INTERPRET to control instruction fetching.

Instruction Interpreter 723 Instruction Interpreter 723 consists primarily of a large DO CASE statement (pages 5 through 11 of EDITREAD-SYS-CALL). A DO CASE statement is a compound statement which includes groups of statements called cases. When a DO CASE statement is executed, the value of an expression specified in the DO CASE statement determines which of the cases is executed. In this DO CASE statement, the binary value of the byte provided by Editing Instruction Fetcher 719 is used as an index into Operator Dispatch Table 726. The value at that location in Operator Dispatch Table 726 then determines which group of statements in the DO CASE statement is executed. For example, if the value in Operator Dispatch Table is 1, the statements on line 518 are executed.When Instruction Interpreter 723 has finished executing statements in a case, Editing Instruction Fetcher 71 9 provides a next byte from Editing Instruction Bytes 225.

The manner in which Editing Instruction Interpreter 723 interprets Editing Instruction Bytes 225 depends on the arrangement of Editing Instruction Bytes 225 in Editing Table 111. As previously mentioned, in this embodiment, Editing Instruction Bytes 225 for a single operation consist of operand bytes followed by an operation code byte. The values of the operand bytes specify that they represent operands and also specify whether the operand byte is a literal or specifies a variable. The variable may be one of the variables in User Variable Array 727 or one of the variables declared on lines 10 through 35 of PACKET. Editing Instruction Interpreter 723 uses Interpreter Stack 725 to store operand values until it interprets the operation code byte.When an operand byte is a literal, Editing Instruction Interpreter 723 places the operand's value on Interpreter Stack 725; when it is a variable, it locates the variable in Control Data 11 5 and places the variable's value on Interpreter Stack 725. When an operation code byte is interpreted, Editing Instruction Interpreter 723 obtains the operands from Interpreter Stack 725 and performs the operation specified by the operation code byte on them. As may be seen by the arrows, Editing Instruction Interpreter 723 can invoke routines in Buffer and Display Coordinator 729 and can invoke the INTERPRET procedure recursively.

5.5.4 Working Buffer Control 731 Working Buffer Control 731 manipulates Working Buffer 113. Working Buffer Control 731 includes the procedures true-buff, insert-true-buff, is-attribute-state-marker, and true-index. The procedures may be found on Pages 24 and 25 of EDITREAD-SYS-CALL. true-buff fetches a data code from Working Buffer 113, insert-true-buff inserts a data code into Working Buffer 11 3, and replace-true-buff replaces one data code in Working Buffer 11 3 with another. The other procedures provide information about Working Buffer 11 3 required to manage Working Buffer 113. As shown by the arrows, only Buffer and Display Coordinator 729 invokes procedures in Working Buffer Control 731.

5.5.5 Buffer and Display Coordinator 729 The remaining procedures contained in EDIT READ-SYS-CALL are parts of Buffer and Display Coordinator 729. Buffer and Display Coordinator 729 coordinates modifications of Working Buffer 11 3 and the output of display codes to Display Buffer 309 so that Display Buffer 309 always reflects the most recent modification of Working Buffer 113. Buffer and Display Control State 730 contains data used by Buffer and Display Coordinator 729 to coordinate its operations.

Most of the PL/I procedures in Buffer and Display Coordinator 729 are invoked only by other procedures in that component. For present purposes, an understanding is required of only those procedures in Buffer and Display Coordinator 729 which are invoked by other components of EDITREAD-SYS-CALL. These procedures fall into two groups: those which modify only Display 107 and those which modify both Working Buffer 11 3 and Display 107. First, the procedures which modify only Display 107: * echo-binary and echo, on pages 22 and 23 of EDITREAD-SYS-CALL. These procedures invoke put-chr to output a single display code to Display Buffer 309 and modify Buffer and Display Control State 730 as required.

* paint and paint-and-restore-state, on pages 16 and 17. These procedures cause Display 107 to display a range of visual representations corresponding to a range of data codes in Working Buffer 113.

paint and paint-and-restore-state work by invoking true-buff to obtain each data code in the range of data codes and then invoking INTERPRET using the data code and a value specifying Display Sequences 209 in Editing Table 111. In the case of printable data codes, INTERPET then invokes echo with a display code corresponding to the data code and echo invokes put-chr as described above, thus causing a display code corresponding to the data code to be added to Display Buffer 309.

The remaining procedures perform operations on Working Buffer 11 3 and cause the result of the operation to be displayed on Display 107.

* MOVE, on pages 13 and 14, carries out the move operation. It updates buffer-index in Buffer and Display Control State 730, invokes the procedure paint to cause Display 107 to display the representations of the data codes affected by the move, and invokes other procedures to reset attributes and output the cursor at the new cursor position. The procedure which outputs the cursor uses put-chr with a special cursor control code to actually put the cursor into Display Buffer 309.

* DELETE, on page 14, deletes one or more data codes from Working Buffer 113. On a delete of characters to the left of a current cursor position, DELETE updates buffer-index and establishes a new cursor position before deleting the data codes; on a delete of characters to the right of a current cursor position, this step is not necessary. After deleting data codes, DELETE updates buffer length and invokes the paint procedure to redisplay the entire contents of Working Buffer 113.

* INSERT, on pages 13 and 14, inserts a data code in Working Buffer 113, updates buffer index and buffer-length, and then invokes the paint procedure to display the altered portion of Working Buffer 113 and the procedures mentioned above to put a cursor into the proper location.

* SEARCH, on pages 15 and 16, locates a data code in Working Buffer 113 which matches a data code provided as an argument to the procedure. SEARCH searches to the left or right, as specified by another argument. If it finds a matching data code, it invokes MOVE to update buffer-index so that it specifies the location of the matching data code and to display representations of the affected portions of Working Buffer 113 on Display 107, as previously described.

6. Operation of a Present Embodiment of ED 101 Having thus provided an overview of the parts of a present embodiment of ED 101, the discussion turns to a description of the operation of this embodiment using a specific Editing Table 111. The discussion first presents a specific Editing Table 1 1 1 and then describes how ED 101 uses that Editing Table 111 to execute an initial operation and a search operation and to respond to a delimiter code.

6.1 Detailed Description of a Specific Editing Table 111 Editing Tables 1 1 1 for this embodiment of ED101 are produced by a compilerfrom a source text of ASCII characters. When a user of Digital Computer System 127 wishes to make a new Editing Table 111, he writes a source text and then uses the compiler to produce an Editing Table 111 corresponding to the source text. A source text for an Editing Table 101 entitled DEFAULT-TABLE, may be found in Appendix B. A hexadecimal representation of Default Table 801, an editing table produced by the compiler from DEFAULT-TABLE, is presented in Figure 8. The discussion first explains how one skilled in the art may read DEFAULT-TABLE and then shows how Default Table 801 relates to DEFAULT-TABLE.

6.1.1 The Source Text DEFAULT TABLE Turning first to Appendix B, the actual source text for Default Table 801 begins on line 46. The words INITIAL MACRO indicate that the part of DEFAULT-TABLE which follows corresponds to Initial Sequence 205 for Default Table 801. The text enclosed in square brackets is a programming language used to produce Editing Tables 111. The text specifies Editing Instruction Bytes 225 in the Editing Instruction Sequence 215 contained in Initial Sequence 205. Similarly, FINAL MACRO on line 47 indicates that the following text (in this case, none), specifies Editing Instruction Bytes 225 for Final Sequence 207, ECHO MACROS on line 49 indicates the beginning of Editing Instruction Sequences 215 for Display Sequences 209, and STATE=0 indicates the first Buffer Editing Sequence 213, STATE=1 the next, and so on through STATE=6.

As previously explained, in Display Sequences 209 and Buffer Editing Sequences 211, each Editing lns,truc#ion Sequence 215 contains the values LV 219 and UV 221, which together specify the range of values of the data codes for which Editing Instruction Sequence 215 is valid.

These values are indicated in DEFAULT-TABLE by two hexadecimal values preceding the text in square brackets. Thus, on line 50, 20, 7F indicates that LV 219 will have the hexadecimal value 20 (decimal 32) and UV 221 the hexadecimal value 7F (decimal 127). The data codes used in this embodiment are ASCII codes and the ASCII codes in the range specified 20 and 7F are the codes for the printable characters.

Thus, the test in square brackets on line 50 specifies actions to be performed by ED 101 in response to a printable ASCII character.

Having thus provided an overview of DEFAULT TABLE, the discussion now proceeds to provide enough detail concerning the programming language used to specify operations of ED 101 in this embodiment to allow one skilled in the art to read DEFAULT-TABLE. Other embodiments may of course use other programming languages. Each operation specified by the programming language is enclosed in square brackets. An operation is defined by specifying the operation and then its operands. The operands may be literal values, variables in Control Data 11 5, and values produced by other operations. For example, [Echo char] on line 46 specifies that the Echo operation, corresponding to the echo procedure in Buffer and Display Coordinator 728, is to be performed using the current value of the variable char in Interpreter Control State 705.

A more complicated example is the following, on line 51: [ Do [Echo " " ] While [Mod cursorpos8 ] ] . As indicated by the range of values, this operation provides a visual representation on Display 107 corresponding to an ASCII Tab character (ASCII code 9). Do While specifies that the operation following the Do is to continue as long as the value returned by the operation following the While is not equal to 0. Here, the operation following the Do, [ Echo " " ] causes a blank to appear on Display 107 and also increments the variable cursor-pos in Buffer and Display Control State 730 by 1. [Mod cursor-pos 8] finds the modulo of the value currently contained incursor-pos and 8. The modulo equals 0 only if cursor-pos is evenly divisible by 8.

Consequently, the entire operation specifies that blanks are to be output on Display 107, that each time a blank is output, the modulo of cursor-pos and 8 is to be calculated, and that output of blanks is to stop when the modulo of cursor-pos and 8 reaches 0, i.e., when the position of the next tab stop in Display 107 has been reached. As will be seen when EDITREAD-SYS-CALL is examined in more detail, the names used to specify variables and operations in the programming language correspond to names defined in EDITREAD-SYS-CALL.

6.1.2 Hexadecimal Representation of Default Table 801~Figure 8 Figure 8 is a hexadecimal representation of Default Table 801. Default Table 801 is represented as an array of values represented by four hexadecimal digits. Each digit represents four bits, and consequently, each group represents 16 bits of two bytes. In order to facilitate references to parts of Default Table 801, row and column indexes have been added to Figure 8. In the ensuing discussion, a given group of hexadecimal digits is referred to by its row and column number. In addition, Figure 8 is marked to show the correspondence between the parts of Editing Table 111 as represented in Figure 2 and the bytes of Default Table 801. The correspondence is further established by the table below the representation of Default Table 801.As specified by DEFAULT-TABLE, Default Table 801 has Locator Information 201, Dispatch Table 203, Initial Sequence 205, Display Sequences 209, and 7 Buffer Editing Sequences 211, for values of State 121 from O through 6. Default Table 801 has no Final Sequence 207.

The part of Default Table 801 labelled ES 805, occupying words, 2,7 and 2,8, may serve as an example of a specific Editing Instruction Sequence 215. As may be seen by the fact that ES 805 is the first Editing Instruction Sequence in Display Sequences 109, it corresponds to line 50 of DEFAULT-TABLE. The first two bytes of ES 805 are LV 219 and UV 221; as specified on line 50 of DEFAULT-TABLE, LV contains the hexadecimal value 20 and UV the hexadecimal value 7F. The next byte is Size 223; it contains the hexadecimal value 1, so the remainder of ES 805 contains a single byte. That byte contains the hexadecimal value 76; as will be seen in detail later, that value is an operation code which causes the INTERPET procedure to invoke the echo procedure with the data code or input code used in the invocation of INTERPRET.Other parts of Default Table 801 important to the discussion have also been labelled; these parts will be explained in detail in the pertinent parts of the discussion.

6.2 Operation of a Present Embodiment of ED 101 with Default Table 801 As previously explained and as illustrated in Figure 7, operation of a present embodiment of ED 101 begins with the invocation of the procedure EDITREAD-SYS-CALL by a program using ED 101. The first portion of EDITREAD SYS-CALLto be executed is Initial Control 707.

6.2.1 Operation of Initial Control 707 Initial Control 707 begins on page 2 of EDIT READ-SYS-CALL. As may be seen there, this portion of EDITREAD-SYS-CALL first initializes various variables, and then invokes the paint procedure in order to display visual representations of the contents of Working Buffer 113 on Display 107. The paint procedure, on page 17 of EDITREAD-SYS-CALL, contains a loop (lines 136 to 153) which for each printable data code in Working Buffer 113 first invokes the true buff procedure to fetch the data code from Working Buffer 113 (line 137) and then invokes the INTERPET procedure (line 148) with the data code and a value specifying that INTERPRET is to obtain the Editing Instruction Sequence 215 corresponding to the data code from Display Sequences 209. The value is represented in the invocation by the name ECHO-STATE.

Turning now to INTERPRET, on pages 4 and 5 of EDITREAD-SYS-CALL, there may be seen on lines 466 to 470 a group of statements which are executed when INTERPRET is invoked with the value represented by ECHO-STATE. These statements set the variable mstrt from the variable echo-macro-start and mstop from the variable echo-macro-size. As previously explained, these variables, declared in CHANNEL DATA, refer to values in Locator Information 201 of Default Table 801 which locate the beginning and end of Display Sequences 209. Thus, the variable mstrt now specifies the location of the first byte first byte in Display Sequences 209 and the variable limit specifies the last byte in Display Sequences 209.

Next, the loop on lines 484 to 492 searches Display Sequences 209 for an Editing Instruction Sequence 215 whose LV 219 and UV 221 specify a range of values which includes the data code or input code used to invoke INTERPRET. If it finds such a sequence, statements in the loop set the variable mstrt to specify the first byte of Editing Instruction Bytes 225 and the variable mstop to specify the last byte. The value to which the latter variable is set is calculated from Size 223. After these variables have been set, control is transferred to START-INTERPRETING (line 495). Otherwise, the loop continues searching until it finds an Editing Instruction Sequence 215 corresponding to the code or reaches the end of Display Sequences 209.

Generally speaking, the data codes in Working Buffer 113 are data codes for printable characters. In this case, as previously explained, the relevant Editing Instruction Sequence is ES 805, whose Editing Instruction Bytes 225 consist of a single byte having the hexadecimal value 76 (decimal 11 8). Continuing the explanation on the assumption that the data code used to invoke INTERPRET is one for a printable character, when control is transferred to START-INTERPRETING, mstrt specifies the location of the last byte in ES 805 and mstop specifies the same location.

Consequently, the DO WHILE loop on lines 509 through 863 executes only once. The first statement in the DO WHILE loop assigns the value of the byte specified by mstrt to the variable byte. In the present case, the variable byte thus receives the decimal value 11 8. The value of byte is then used as an index into OPERATOR-DIS PATCH-TABLE. As may be seen on line 49 of page 3 of the declarations in Appendix A, the 118th element of OPERATOR-DISPATCH-TABLE contains the value 5.

That value is then used to determine which of the cases in the DO CASE statement on lines 516 through 845 is to be executed. The case for the value 5 is found on lines 541 through 544; the statements at this location invoke the procedure echo using the data code received when INTERPET was invoked. As previously explained, the echo procedure causes the put-chr procedure to output the data code to Display Buffer 309.

The paint procedure performs the steps described above for every data code contained in Working Buffer 113; consequently, when the paint procedure is finished, Display Buffer 309 contains display codes corresponding to the data codes in Working Buffer 11 3, and when the flush buffer procedure is invoked, Display 107 displays a visual representation of Working Buffer 113.

Returning to page 4 of EDITREAD-SYS-CALL, the portion of EDITREAD-SYS-CALL corresponding to Initial Control 707 next invokes INTERPRET in order to execute Editing Instruction Bytes 215 contained in Initial Sequence 205 (line 413). In Default Table 801, these are the bytes labelled IM 806. They correspond to the operation specified by [Set-cursor-type insert-mode] on line 46 of DEFAULT-TABLE. The operation sets the variable cursor-type to the value of the variable insert-mode and thereby determines how Display 107 will show the location of the cursor. In this operation, set-cursor-type is the operator and insert-mode the operand; as previously explained, in Editing Instruction Bytes 225, the bytes specifying the operands precede the byte specifying the operation; consequently, the hexadecimal value 42 in IM 806 specifies the operand and the hexadecimal value 9B the operator.

As may be seen from the statements for this case on lines 471 through 476, mstrt is set to 1 and mstop set to the value obtained from Initial Macro Size 803, in this case, 2, specifying 2 bytes. The statements beginning with START INTERPETING then work as previously described, except that there are two bytes to be interpreted, and consequently, the DO LOOP is executed twice.

On the first execution, the variable byte has the hexadecimal value 42 (decimal 66); the 66th entry of OPERATOR-DISPATCH-TABLE, page 3, line 47, has the value 4, and the fourth case of the DO CASE statement (lines 536-539 of EDIT READ-SYS-CALL) places the value of the variable specified by the value of byte, in this case, the variable insert-mode, onto Interpreter Stack 725.

On the second execution, byte has the hexadecimal value 9B (decimal 155); the 155th entry of OPERATOR-DISPATCH-TABLE, page 3, line 51 of the declarations, has the value 31, and the 31 sot case of the DO CASE statement (lines 684 to 693 on page 9 of EDITREAD-SYS-CALL) specifies that the value at the top of Interpreter Stack 725 be assigned to the variable CURSOR TYPE. Since that value is the value of the variable insert-mode, CURSOR-TYPE receives that value as specified on line 46 of DEFAULT-TABLE.

6.2.2 Operation of Control Loop 705 Having finished Initial Control 707, EDIT READ-SYS-CALL enters Control Loop 705, lines 422 to 427 on page 4, and continues reading input codes from Input 109 until it receives a delimiter code. As previously mentioned, Read Function 711 invokes the procedure flush-buffer of Screen Control 713, and therefore, the contents of Display Buffer 309 are displayed on Display 107 each time a character is read.For the purposes of this example, it will be assumed that EDITREAD-SYS-CALL receives three input codes: a byte containing the binary representation of 6, specifying a search to the right of the cursor for the data code specified by the next input code, a byte containing the binary representation of 65, specifying the character "A" to be searched for, and a byte containing the binary representation of 10, specifying an ASCII new-line character, which Default Table 801 defines as a delimiter.

Turning first to DEFAULT-TABLE in Appendix B to see what actions Default Table 801 defines for these input codes, the action for the search forward is defined on line 99: 06,06: [Set state 2] This portion of DEFAULT-TABLE specifies that the variable state corresponding to State 121 is to be set to the value of 2. When the next input code, 65, comes in, State 121 has the value 2, INTERPRET is invoked with that value, and the procedure uses the instruction sequence specified at lines 122 and 123 of DEFAULT-TABLE: 00,FF: [Mod-attribute V2 [Minus [Search char ] ] ] [Set state 0] The above instructions specify that ED 101 is to search for the character, if it finds it, modify the manner in which the range of characters between the beginning and the end of the search is displayed to show the range of the search, and then reset State 121 to 0.The instructions for the delimiter character are found on line 109 of DEFAULT-TABLE: OA,OF: [Delimit] The operation specified by this instruction will be explained in detail below.

The Editing Instruction Sequences 215 in Default Table 801 corresponding to these instructions in DEFAULT-TABLE are labelled in Figure 8. ES 807 corresponds to 06,06: [Set state 2]; ES 809 corresponds to O0,FF: [Mod-attribute V2 [Minus [Search/B char ] ] ] [Set state 0] and ES 811 corresponds to OA,OF: [Delimit].

ED 101~executes the above Editing Instruction Sequences in response to the input codes 6, 65, and 10 as follows: As shown on line 426 of EDITREAD-SYS-CALL, each time Control Loop 705 has obtained a new input code by invoking the read procedure, it invokes INTERPRET using the input code and the current value of State 121. Lines 462 to 465 in INTERPRET show how INTERPRET uses the input code and the value of State 121 to produce the location of the proper Editing Instruction Sequence 21 5 in Default Table 801. As previously mentioned, the variable DISPATCH TABLE identifies Dispatch Table 203, consisting in Default Table 801 of words 1,6 to 2,5.The first word in Default Table 801 contains the offset in bytes from the start of Initial Sequence 205 of Buffer Editing Sequence 213 for State=O, the second the offset for State=1, and so forth. Using the value of State 121 as an index into DIS PATCH-TABLE, INTERPRET locates the beginning and end of Buffer Editing Sequence 213 for the given state value and sets mstrt to the beginning and limit to the end. INTERPRET then locates Editing Instruction Sequence 21 5 for the input code and executes that Editing Instruction Sequence as previously described.

Since one skilled in the art may understand from the explanations already presented and from the source text of EDITREAD-SYS-CALL how the specified Editing Instruction Sequences 215 in Default Table 801 are interpreted by the INTERPRET procedure, further detail is presented only with regard to the manner in which execution of [ Delimit ] causes ED 101 to cease operation.

6.2.3 Termination of Operation of an Embodiment of ED 101 The statements executed in the INTERPRET procedure when a delimiter character is received are on lines 553 to 562. The bulk of these statements deals with the face that delimiters used in the present embodiment of ED 101 may consist of either one- or two-byte codes and are not important to this discussion. The statements which actually cause ED 101 to terminate operations are on lines 560 and 561. The assignment statement on line 560 sets State 121 to a value which is greater than the number of states for which there are Editing Instruction Sequences 21 5 in Default Table 801, and the assignment statement on line 561 sets macroindex to 1000, which is greater than any possible value of mstop. When macro-index has a value greater than mstop, the DO WHILE loop which begins on line 509 terminates.That in turn results in execution of the RETURN statement on line 866, which causes control to return to Control Loop 705, on lines 422 to 427. Since State 121 now has a value greater than the number of states in Default Table 801, the loop terminates and Final Control 703 begins executing.

6.2.3.1 Operation of Final Control 703 As may be seen from line 433, Final Control 703 once again invokes INTERPRET, this time with FINAL-STATE. The statements in INTERPRET for that state are on lines 477 to 482. These statements locate Final Sequence 211 from the value of the variable final-macro-start and the value of Final Macro Size 813. Since Default Table 801 has no Final Sequence 211, final macro-start specifies the beginning of Display Sequences 209 and, as may be seen from Figure 8, Final Macro Size 813 has the value 0. Thus, when control is transferred to START INTERPRETING, mstop is less than mstart and the DO WHILE loop beginning on line 509 is not executed. INTERPRET thus returns to Final Control 703 (lines 429 to 445) without performing any actions, and Final Control 703 concludes the operation of ED 101 by calling flush-buffer to output the contents of Display Buffer 309 to Display 107 and then returning to the program which invoked EDITREAD-SYS CALL.

Appendix A Appendix A presents the PL/I source text for the instructions used to implement the present embodiment of Editread Interpreter 101 and the PL/I data declarations required to understand the PVI source text. Pages of the source text bear the label EDITREAD-SYS-CALL in their upper lefthand corners; the pages of the data declarations follow the source text and bear the labels ERROR CODES, EXTENDED-READ, PACKET, REPLACES, and TERMINAL-DATA.

Claims (84)

Claims

1. In a data processing system, editing means for modifying data codes comprising: (1) receiving means for receiving input codes in said editing means; (2) memory means including (a) buffer memory means for storing said data codes and (b) editing table memory means for storing an editing table including (i) editing instruction sequences corresponding to said input codes for specifying editing operations modifying said data codes in said buffer memory means; and (3) processing means connected from said receiving means and said memory means for performing the operations of (a) receiving said input codes from said receiving means, (b) for each said input code, determining the location in said editing table of a corresponding said editing instruction sequence corresponding to said input code, (c) receiving said editing instructions of said corresponding said editing instruction sequence, and (d) responding to said editing instructions of said corresponding said editing instruction sequence by modifying said data codes in said buffer memory means, whereby said data codes are modified by said processing means in response to said input codes.

2. In the editing means of claim 1 and wherein: said memory means further includes (c) control data memory means for storing control data for controlling said editing means, and said processing means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

3. In the editing means of claim 1, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said data codes and said input codes, (2) memory means responsive to memory signals from said processor means for storing said data and sequences of said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said input codes from said receiving means to said memory means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means; said buffer memory means is contained in said memory means; said editing table memory means is contained in said memory means;; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

4. In the editing means of claim 3, and wherein: said editing means further includes (c) control data memory means contained in said memory means for storing control data for controlling said editing means; and said processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

5. In the editing means of claim 1, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) second processor means responsive to second instructions for processing second certain data including said data codes and said input codes, (3) memory means responsive to memory signals from said first processor means and from said second processor means for storing said first certain data, said second certain data, first certain instruction sequences containing said first instructions and second certain instruction sequences containing said second instructions, (4) means under control of said first processor means for transferring said first certain data between said memory means and said first processor means, said first instructions between said memory means and said first processor means, and said memory signals from said first processor means to said memory means, and (5) means under control of said second processor means for transferring said input codes from said receiving means to said memory means, transferring said second certain data between said memory means and said second processor means, transferring said second instructions from said memory means to said second processor means, and transferring said memory signals from said second processor means to said memory means; said buffer memory means is contained in said memory means; said editing table memory means is contained in said memory means; said second certain instruction sequences include an editing means instruction sequence; and said processing means is said second processor means.

6. In the editing means of claim 5, and wherein: said editing means further includes (c) control data memory means contained in said memory means for storing control data for controlling said editing means; and said second processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

7. In the editing means of claim 1, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) first memory means responsive to memory signals from said first processor means for storing said first certain data and first instruction sequences containing said first instructions, (3) terminal means for receiving said input codes in said data processing system, including (a) terminal receiving means for receiving said input codes, (b) second processor means responsive to second instructions for processing second certain data including said data codes and said input codes, (c) second memory means for storing said second certain data and second instruction sequences containing said second instructions, and (d) means under control of said second processor means for receiving said input codes from said terminal receiving means, transferring said second certain data between said second memory means and said second processor means, and transferring said second instructions from said second memory means to said second processor means, and (4) means under control of said first processor means for transferring said first certain data between said first memory means and said second memory means; said buffer memory means is contained in said second memory means; said editing table memory means is contained in said second memory means; said second certain instruction sequences include an editing means instruction sequence; said receiving means is said terminal receiving means; and said processing means is said second processor means.

8. In the editing means of claim 7, and wherein: said first certain data further includes at least one said editing table and said editing table stored in said editing table memory means is a said editing table from said first certain data.

9. In the editing means of claims 7 or 8, and wherein: said editing means further includes (c) control data memory means contained in said second memory means for storing control data for controlling said editing means; and said terminal processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

10. In the editing means of claim 1, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said input codes and said data codes, (2) memory means responsive to memory signals from said processor means for storing said data and instruction sequences containing said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said input codes from said receiving means to said processor means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means, (4) in said memory means, a plurality of process state memory means for retaining state for executions of said instruction sequences for a user of said data processing system, said state including at least the location in said memory means of the next said instruction to be executed in one of said instruction sequences, and (6) in said instruction sequences, a process manager instruction sequence for temporarily associating one said process state memory means with said processor means and thereby causing said processor means to execute said instructions in said one of said instruction sequences for said user; said buffer memory means is contained in said memory means and associated with one said process state memory means; said editing table memory means is contained in said memory means; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

11. In the editing means of claim 10, and wherein: said editing means further includes (c) control data memory means for storing control data for controlling said editing means, said control data memory means being contained in said memory means and associated with said one said process state memory means; and said processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

12. In a data processing system, means for displaying sequences of visual representations corresponding to data codes comprising: (1) display means for displaying said sequences of visual representations in response to display codes; (2) memory means including (a) buffer memory means for storing said data codes and (b) editing table memory means for storing an editing table including editing instruction sequences corresponding to said data codes for specifying operations producing sequences of said display codes;; (3) processing means connected from said display means and from said memory means for performing the operations of (a) receiving said data codes from said buffer memory means, (b) for each said data code, determining the location of a corresponding said editing instruction sequence corresponding to said data code, (c) receiving said editing instructions in said sequence, and (d) responding to said editing instructions by producing a sequence of said display codes and causing said display means to respond to said sequence of said display codes, whereby said sequences of visual representations are displayed on said display means in response to said data codes fetched from said buffer memory means.

13. In the editing means of claim 12, and wherein: said memory means further includes (c) control data memory means for storing control data for controlling said editing means, and said processing means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

14. In the means for displaying sequences of visual representations of claim 12, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said data codes and said display codes, (2) memory means responsive to memory signals from said processor means for storing said data and sequences of said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said display codes from said memory means to said display means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means; said buffer memory means is contained in said memory means; said editing table memory means is contained in said memory means;; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

15. In the editing means of claim 14, and wherein: said editing means further includes (c) control data memory means contained in said memory means for storing control data for controlling said editing means; and said processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

1 6. In the means for displaying visual representations of claim 12, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) second processor means responsive to second instructions for processing second certain data including said data codes and said display codes, (3) memory means responsive to memory signals from said first processor means and from said second processor means for storing said first certain data, said second certain data, first certain instruction sequences containing said first instructions, and second certain instruction sequences containing said second instructions, (4) means under control of said first processor means for transferring said first certain data between said memory means and said first processor means, said first instructions between said memory means and said first processor means, and said memory signals from said first processor means to said memory means, and (5) means under control of said second processor means for transferring said second certain data between said memory means and said second processor means, transferring said second instructions from said memory means to said second processor means, transferring said display codes from said memory means to said display means, and transferring said memory signals from said second processor means to said memory means; said buffer memory means is contained in said memory means; said editing table memory means is contained in said memory means; said second certain instruction sequences include an editing means instruction sequence; and said processing means is said second processor means.

17. In the editing means of claim 16, and wherein: said editing means further includes (c) control data memory means contained in said memory means for storing control data for controlling said editing means; and said second processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

18. In the means for displaying sequences of visual representations of claim 12, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) first memory means responsive to memory signals from said first processor means for storing said first certain data and first instruction sequences containing said first instructions, (3) terminal means for displaying said sequences of visual representations including (a) terminal display means for displaying said sequences of visual representations in response to said display codes, (b) second processor means responsive to second instructions for processing second certain data including said data codes and said display codes, (c) second memory means for storing said second certain data and second instruction sequences containing said second instructions, and (d) means under control of said second processor means for causing said terminal display means to respond to said sequences of display codes, transferring said second certain data between said second memory means and said second processor means, and transferring said second instructions from said second memory means to said second processor means, and (4) means under control of said first processor means for transferring said first certain data between said first memory means and said second memory means; said buffer memory means is contained in said second memory means; said editing table memory means is contained in said second memory means; said second certain instruction sequences include an editing means instruction sequence; said display means is said terminal display means; and said processing means is said second processor means.

19. In the means for displaying sequences of visual representations of claim 18, and wherein: said first certain data further includes at least one said editing table and said editing table stored in said editing table memory means is a said editing table from said first certain data.

20. In the editing means of claims 18 or 19, and wherein: said editing means further includes (c) control data memory means contained in said second memory means for storing control data for controlling said editing means; and said second processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

21. In the means for displaying sequences of visual representations of claim 12, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said data codes and said display codes, (2) memory means responsive to memory signals from said processor means for storing said data and instruction sequences containing said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said display codes to said display means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means, (4) in said memory means, a plurality of process state memory means for retaining state for executions of said instruction sequences for a user of said data processing system, said state including at least the location in said memory means of the next said instruction to be executed in one said instruction sequence, and (5) in said instruction sequences, a process manager instruction sequence for temporarily associating one said process state memory means with said processor means and thereby causing said processor means to execute said instructions in said one said instruction sequence for said user; said buffer memory means is contained in said memory means and associated with one said process state memory means; said editing table memory means is contained in said memory means; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

22. In the editing means of claim 21, and wherein: said editing means further includes (c) control data memory means for storing control data for controlling said editing means, said control data memory means being contained in said memory means and associated with one said process state memory means; and said processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

23. In a data processing system, editing means for modifying data codes and displaying sequences of visual representations corresponding to data codes comprising: (1) receiving means for receiving input codes in said editing means; (2) display means for displaying said sequences of visual representations in response to display codes;; (3) memory means including (a) buffer memory means for storing said data codes and (b) editing table memory means for storing an editing table containing editing instruction sequences including (i) buffer editing instruction sequences corresponding to said input codes and (ii) display editing instruction sequences corresponding to said data codes, said buffer editing instruction sequences specifying editing operations on said buffer memory means and said display editing instruction sequences specifying operations producing sequences of said display codes;; and (4) processing means connected from said receiving means, from said display means, and from said memory means for performing the operations of (a) receiving said input codes from said receiving means, (b) for each said input code, determining the location of a corresponding said buffer editing instruction sequence corresponding to said input code, (c) receiving said editing instructions of said corresponding said buffer editing instruction sequence, (d) responding to said editing instructions of said corresponding said buffer editing instruction sequence by modifying said data codes in said buffer memory means, (e) receiving data codes from said buffer memory means, (f) for each said data code, determining the location of a corresponding said display editing instruction sequence corresponding to said data code, and (g) receiving said display editing instructions of said corresponding said display editing instruction sequence and responding to said display editing instructions of said corresponding said display editing instruction sequence by producing a sequence of said display codes and causing said display means to respond to said certain sequence of said display codes, whereby said data codes are modified by said processing means in response to said input codes and said visual representations corresponding to said modified said data codes are displayed on said display means in response to said data codes.

24. In the editing means of claim 23, and wherein: said memory means further includes (c) control data memory means for storing control data for controlling said editing means, and said processing means further responds to said buffer editing instruction sequences and said display editing instruction sequences by modifying said control data.

25. In the editing means of claim 23, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said data codes, said input codes, and said display codes, (2) memory means responsive to memory signals from said processor means for storing said data and sequences of said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said input codes from said receiving means to said memory means, transferring said display codes from said memory means to said display means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means; said buffer memory means is contained in said memory means;; said editing table memory means is contained in said memory means; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

26. In the editing means of claim 25, and wherein: said editing means further includes (c) control data memory means contained in said memory means for storing control data for controlling said editing means; and said processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

27. In the editing means of claim 23, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) second processor means responsive to second instructions for processing second certain said data including said data codes, said input codes, and said display codes, (3) memory means responsive to memory signals from said first processor means and from said second processor means for storing said first certain data, said second certain data, first certain instruction sequences containing said first instructions, and second certain instruction sequences containing said second instructions, (4) means under control of said first processor means for transferring said first certain data between said memory means and said first processor means, said first instructions between said memory means and said first processor means, and said memory signals from said first processor means to said memory means, and (5) means under control of said second processor means for transferring said input codes from said receiving means to said memory means, transferring said second certain data between said memory means and said second processor means, transferring said second instructions from said memory means to said second processor means, transferring said display codes from said memory means to said display means, and transferring said memory signals from said second processor means to said memory means; said buffer memory means is contained in said memory means; said editing table memory means is contained in said memory means; said second certain instruction sequences include an editing means instruction sequence; and said processing means is said second processor means.

28. In the editing means of claim 27, and wherein: said editing means further includes (c) control data memory means contained in said memory means for storing control data for controlling said editing means; and said second processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

29. In the editing means of claim 23, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes.

(2) first memory means responsive to memory signals from said first processor means for storing said first certain data and first certain instruction sequences containing said first instructions, (3) terminal means for receiving said input codes to said data processing system and displaying said sequences of visual representations, said terminal means including (a) terminal receiving means for receiving said input codes, (b) terminal display means for displaying said sequences of visual representations in response to said display codes, (c) second processor means responsive to second instructions for processing second certain data including said input codes, said data codes, and said display codes, (d) second memory for storing said second certain data and second certain instruction sequences containing said second instructions, and (e) means under control of said second processor means for obtaining said input codes from said terminal receiving means, causing said terminal display means to respond to said sequences of display codes, transferring said second certain data between said second memory means and said second processor means, and transferring said second instructions from said second memory means to said second processor means, and (4) means under control of said first processor means for transferring said first certain data between said first memory means and said second memory means; said buffer memory means is contained in said second memory means; said editing table memory means is contained in said second memory means; said second certain instruction sequences include an editing means instruction sequence; said display means is said terminal display means;; said receiving means is said terminal receiving means; and said processing means is said second processor means.

30. In the editing means of claim 29, and wherein: said first certain data further includes at least one said editing table and said editing table stored in said editing table memory means is a said editing table from said first certain data.

31. In the editing means of claims 29 or 30, and wherein: said editing means further includes (c) control data memory means contained in said second memory means for storing control data for controlling said editing means; and said second processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

32. In the editing means of claim 23, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said input codes, said data codes, and said display codes, (2) memory means responsive to memory signals from said processor means for storing said data and instruction sequences containing said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said input codes from said receiving means to said processor means, transferring said display codes to said display means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means, (4) in said memory means, a plurality of process state memory means for retaining state for executions of said instruction sequences for a user of said data processing system, said state including at least the location in said memory means of the next said instruction to be executed in one of said instruction sequences, and (5) in said instruction sequences, a process control instruction sequence for temporarily associating one said process state memory means with said processor means and thereby causing said processor means to execute said instructions in said one of said instruction sequences for said user; said buffer memory means is contained in said memory means and is associated with one said process state memory means; said editing table memory means is contained in said memory means; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

33. In the editing means of claim 32, and wherein: said editing means further includes (c) control data memory means for storing control data for controlling said editing means, said control data memory means being contained in said memory means and being associated with one said process state memory means; and said processor means further responds to said editing instructions of said corresponding said editing instruction sequence by modifying said control data.

34. In the editing means of claim 1, 2, 3,4, 5, 6,7,8,10,11,12,13,14, 15,16,17,18,19, 21, 22,23, 24, 25,26, 27, 28,29, 30, 32, or 33, and wherein: certain said editing instruction sequences include (a) a range specifier specifying which of said input codes or said data codes correspond to said editing instruction sequence, (b) a size specifier specifying a number of bytes in said editing instruction sequence, and (c) at least one said editing instruction.

35. In the editing means of claim 1, 2, 3, 4, 5, 6,7,8,10,11,12,13,14, 15,16,17,18,19, 21, 22, 23, 24,25,26,27,28, 29, 30, 32, or 33, and wherein: certain said editing instructions include (a) at least one operand byte representing certain data to be operated on by said processing means and (b) a single operation code byte, said at least one operand byte in said second certain said editing instructions precedes said single operation code byte, said memory means further includes operand memory means for storing said certain data represented by said operand bytes, and said processing means responds to a said certain said editing instruction by fetching said at least one operand byte, storing said certain data represented by said operand byte in said operand memory means, and on execution of said operation code byte, fetching said certain data from said operand memory means and using it in said execution of said operation code byte.

36. In the editing means of claim 1, 2, 3, 4, 5, 6,7,8,10,11,12,13,14, 15,16,17,18,19, 21, 22, 23: 24, 25,26, 27, 28, 29, 30, 32, or 33, and wherein: said editing table memory means includes writable memory means, whereby users of said editing means may alter said editing table or may provide a new said editing table for said editing means.

37. In the editing means of claim 1, 2, 3' 4, 5, 6,7,8,10,11,12,13,14, 15,16,17,18,19, 21, 22, 23: 24, 25, 26, 27, 28, 29, 30, 32, or 33, and wherein: said editing table memory means includes read-only memory means containing a said editing table which may not be altered by users of said editing means.

38. In the editing means of claim 1, 2, 3, 4, 5, 6,7,8,10,11,12,13,14, 15,16,17,18,19, 21,22, 23, 24, 25, 26, 27, 28, 29, 30, 32, or 33, and wherein: said editing table memory means includes a plurality of said editing tables, each said editing table has an associated editing table identifier value, said memory means further includes editing table identifier memory means for storing a single said editing table identifier value, and said processing means responds to said editing table identifier value by locating one of said plurality of editing tables.

39. In the editing means of claim 38, and wherein: said editing table memory means includes (a) writable memory means and (b) read-only memory means, and said plurality of said editing tables includes (a) writable editing tables contained in said writable memory means and (b) read-only editing tables contained in said read-only memory means.

40. In a data processing system, the method of employing processing means responsive to editing instructions in editing instruction sequences contained in an editing table in memory accessible to said processing means to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes received by said processing means from receiving means accessible to said processing means, said method comprising the steps of: (1) receiving one input code of said input codes from said receiving means in said processing means; (2) determining in said processing means the address of a corresponding said editing instruction sequence in said editing table using said one input code: (3) receiving said editing instructions from said corresponding said editing instruction sequence in said editing table in said processing means; and (4) responsive to said editing instructions in said corresponding said editing instruction sequence, modifying by means of said processing means first certain data codes of said data codes.

41. In a data processing system, the method of employing processing means responsive to editing instructions in editing instruction sequences contained in an editing table in memory accessible to said processing means to produce visual representations on a display means responsive to display codes and accessible to said processing means by responding to data codes contained in a buffer in memory accessible to said processing means, said method comprising the steps of: (1) receiving one data code of said data codes from said buffer in said processing means; (2) determining in said processing means the address of a corresponding said editing instruction sequence in said editing table using said one data code; (3) receiving said editing instructions from said corresponding said editing instruction sequence in said editing table in said processing means; and (4) responsive to said editing instructions in said corresponding said editing instruction sequence, providing a sequence of said display codes to said display device.

42. In a data processing system, the method of employing processing means responsive to editing instructions in editing instruction sequences contained in an editing table in memory accessible to said processing means to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes received by said processing means from receiving means accessible to said processing means and to display visual representations on display means accessible to said processing means and responsive to display codes, said method comprising the steps of:: (1) receiving one input code of said input codes from said receiving means in said processing means; (2) determining in said processing means the address of-a first corresponding said editing instruction sequence in said editing table using said one input code; (3) receiving said editing instructions from said first corresponding said editing instruction sequence in said editing table in said processing means; (4) responsive to said editing instructions in said corresponding said editing instruction sequence, modifying by means of said processing means first certain data codes of said data codes;; (5) for each said data code of at least said first certain data codes, performing the steps of (a) receiving said data code from said buffer in said processing means, (b) determining in said processing means the address of a second corresponding said editing instruction sequence in said editing table using said data code, (c) receiving said editing instructions from said second corresponding said editing instruction sequence in said editing table in said processing means, and (d) responsive to said editing instructions in said second corresponding said editing instruction sequence, providing a sequence of said display codes to said display means.

43. In a data processing system, the method of employing processing means responsive to editing instructions in editing instruction sequences contained in an editing table in memory accessible to said processing means to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes received by said processing means from receiving means accessible to said processing means, said method comprising the steps of:: (1) receiving said data codes from said data processing system in said buffer; (2) receiving said input codes from said receiving means until a delimiter code of said input codes is received and for each of said input codes except said delimiter code performing the steps of (a) determining in said processing means the address of a corresponding said editing instruction sequence in said editing table using said input code, (b) receiving said editing instructions from said corresponding said editing instruction sequence in said editing table in said processing means, and (c) responsive to said editing instructions in said corresponding said editing instruction sequence, modifying by means of said processing means first certain data codes of said data codes; and (3) responsive to said delimiter code, returning said data codes in said buffer to said data processing system.

44. In the method of claim 43, and wherein: said memory accessible to said processing means contains a plurality of said editing tables; said step (1) further includes receiving an editing table specifier from said digital computer system specifying one editing table of said plurality of said editing tables; and said processing means is responsive to said editing instructions from said one editing table in said step (2).

45. In the method of claim 44, and wherein: said step (1) further includes receiving said one editing table from said data processing system.

46. In a data processing system, the method of employing processing means responsive to editing instructions in editing instruction sequences contained in an editing table in memory accessible to said processing means to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes received by said processing means from receiving means accessible to said processing means, and to display visual representations on display means accessible to said processing means and responsive to display codes, said method comprising the steps of:: (1) receiving said data codes from said data processing system into said buffer; (2) receiving said input codes from said receiving means until a delimiter code of said input codes is received and for each of said input codes except said delimiter code performing the steps of (a) determining in said processing means the address of a first corresponding said editing instruction sequence in said editing table using said input code, (b) receiving said editing instructions from said first corresponding said editing instruction sequence in said editing table in said processing means, (c) responsive to said editing instructions in said first corresponding said editing instruction sequence, modifying by means of said processing means first certain data codes of said data codes, and (d) for each said data code of at least said first certain data codes, performing the steps of (i) receiving said data code from said buffer in said processing means, (ii) determining in said processing means the address of a second corresponding said editing instruction sequence in said editing table using said data code, (iii) receiving said editing instructions from said second corresponding said editing instruction sequence in said editing table in said processing means, and (iv) responsive to said editing instructions in said second corresponding said editing instruction sequence, providing a sequence of said display codes to said display device; and (3) on receipt of said delimiter code, responding to said delimiter code by returning said data codes in said buffer to said data processing system.

47. In the method of claim 46, and wherein: said memory accessible to said processing means contains a plurality of said editing tables; said step (1) further includes receiving an editing table specifier from said digital computer system specifying one editing table of said plurality of said editing tables; and said processing means is responsive to said editing instructions from said one editing table in said step (2).

48. In the method of claim 47, and wherein: said step (1) further includes receiving said one editing table from said data processing system.

49. In a data processing system, editing means for modifying data codes comprising: (1) receiving means for receiving input codes in said editing means; (2) memory means including (a) buffer memory means for storing said data codes, (b) control data memory means for storing at least state data specifying the state of said editing means, and (c) editing table memory means for storing an editing table including (i) editing instruction sequences corresponding to said input codes for specifying editing operations modifying said data codes in said buffer memory means, and (ii) a plurality of sections containing said editing instruction sequences, each said section corresponding to one value of said state data; and (3) processing means connected from said receiving means and said memory means for performing the operations of (a) receiving said input codes from said receiving means, (b) for each said input code and one said value of said state data, determining the location of said corresponding said section corresponding to said one said value and determining the location of said editing instruction sequence corresponding to said input code in said corresponding said section, (c) receiving said editing instructions of said corresponding said editing instruction sequence, and (d) responding to said editing instructions of said corresponding said editing instruction sequence by modifying said data codes in said buffer memory means whereby said data codes are modifed by said processing means in response to said input codes.

50. In the editing means of claim 49, and wherein: said plurality of sections includes four sections and said state data may have four values.

51. In the editing means of claim 49, and wherein: said plurality of sections includes more than four sections and said state data may have one value corresponding to each section of said plurality of sections.

52. In the editing means of claim 49, and wherein: first certain said editing instruction sequences include state editing instructions for setting said state values of said state data.

53. In the editing means of claim 52, and wherein: said input codes include control input codes; second certain said editing instructions of said first certain editing instructions correspond to said control input codes; and said processor means responds to said second certain said editing instructions corresponding to one said control input code by setting said state value as specified by said corresponding said second certain editing instructions and receiving a next input code from said receiving means, whereby a said control code determines the manner in which said editing means responds to said next input code.

54. In the editing means of claim 49, and wherein: said editing table further includes (ii) an initial portion containing a said editing instruction sequence for execution by said processing means at commencement of operation of said editing means and (iii) a final portion containing a said editing instruction sequence for execution by said processing means at termination of operation of said editing means.

55. In the editing means of any of claims 49 to 54, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said data codes and said input codes, (2) memory means responsive to memory signals from said processor means for storing said data and sequences of said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said input codes from said receiving means to said memory means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means; said buffer memory means is contained in said memory means; said editing table memory means is contained in said memory means;; said control data memory means contained in said memory means; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

56. In the editing means of any of claims 49 to 54, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) second processor means responsive to second instructions for processing second certain data including said data codes and said input codes, (3) memory means responsive to memory signals from said first processor means and from said second processor means for storing said first certain data, said second certain data, first certain instruction sequences containing said first instructions and second certain instruction sequences containing said second instructions, (4) means under control of said first processor means for transferring said first certain data between said memory means and said first processor means, said first instructions between said memory means and said first processor means, and said memory signals from said first processor means to said memory means, and (5) means under control of said second processor means for transferring said input codes from said receiving means to said memory means, transferring said second certain data between said memory means and said second processor means, transferring said second instructions from said memory means to said second processor means, and transferring said memory signals from said second processor means to said memory means; said buffer memory means is contained in said memory means; said editing table memory means is contained in said memory means; said control data memory means is contained in said memory means; said second certain instruction sequences include an editing means instruction sequence; and said processing means is said second processor means.

57. In the editing means of any of claims 49 to 54, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) first memory means responsive to memory signals from said first processor means for storing said first certain data and first instruction sequences containing said first instructions, (3) terminal means for receiving said input codes in said data processing system, including (a) terminal receiving means for receiving said input codes, (b) second processor means responsive to second instructions for processing second certain data including said data codes and said input codes, (c) second memory for storing said second certain data and second instruction sequences containing said second instructions, and (d) means under control of said second processor means for receiving said input codes from said terminal receiving means, transferring said second certain data between said second memory means and said second processor means, and transferring said second instructions from said second memory means to said second processor means, and (4) means under control of said first processor means for transferring said first certain data between said first memory means and said second memory means; said buffer memory means is contained in said second memory means; said editing table memory means is contained in said second memory means; said control data memory means is contained in said second memory means; said second certain instruction sequences include an editing means instruction sequence; said receiving means is said terminal receiving means; and said processing means is said second processor means.

58. In the editing means of claim 57, and wherein: said first certain data further includes (a) at least one said editing table and (b) external control data; said editing table stored in said editing table memory means is a said editing table from said first certain data; and certain data in said control data is from said external control data.

59. In the editing means of any of claims 49 to 54, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said input codes and said data codes, (2) memory means responsive to memory signals from said processor means for storing said data and instruction sequences containing said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said input codes from said receiving means to said processor means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means, (4) in said memory means, a plurality of process state memory means for retaining state for executions of said instruction sequences for a user of said data processing system, said state including at least the location in said memory means of the next said instruction to be executed in one of said instruction sequences, and (5) in said instruction sequences, a process manager instruction sequence for temporarily associating one said process state memory means with said processor means and thereby causing said processor means to execute said instructions in said one of said instruction sequences for said user; said buffer memory means is contained in said memory means and associated with one said process state memory means; said control data memory means is contained in said memory means and associated with one said process state memory means; said editing table memory means is contained in said memory means; ; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

60. In a data processing system, editing means for modifying data codes and displaying sequences of visual representations comprising: (1) receiving means for receiving input codes in said editing means; (2) display means for displaying said sequences of visual representations in response to display codes, (3) memory means including (a) buffer memory means for storing said data codes, (b) control data memory means for storing at least state data specifying the state of said editing means, and (c) editing table memory means for storing an editing table containing editing instruction sequences including (i) editing instruction sequences corresponding to said input codes and to said data codes (ii) a plurality of sections containing said editing instructions, each said section corresponding to one value of said state data, said sections including at least a display section corresponding to an echo value of said state data, and said display section containing said editing instruction sequences specifying operations producing sequences of said display codes; and (4) processing means connected from said receiving means, from said display means, and from said memory means for performing the operations of (a) receiving said input codes from said receiving means, (b) for each said input code and a said state value, determining the location of a corresponding said section corresponding to said state value and of said editing instruction sequence corresponding to said input code in said corresponding said section, (c) receiving said editing instructions of said corresponding said editing instruction sequence in said corresponding said section, (d) responding to said editing instructions of said corresponding said editing instruction sequence by modifying said data codes in said buffer memory means, (e) receiving data codes from said buffer memory means, (f) for each said data code, (i) setting said state value to said echo value, (ii) determining the location of said editing instruction sequence corresponding to said data code in said display section, and (iii) receiving said editing instructions of said corresponding said editing instruction sequence in said display section and responding to said editing instructions of said corresponding said editing instruction sequence by producing a sequence of said display codes and causing said display means to respond to said certain sequence of said display codes, whereby said data codes are modified by said processing means in response to said input codes and said visual representations corresponding to said modified said data codes are displayed on said display means in response to said data codes.

61. In the editing means of claim 60, and wherein: said plurality of sections includes four sections and said state data may have four values.

62. In the editing means of claim 60, and wherein: said plurality of sections includes more than four sections and said state data may have one value corresponding to each section of said plurality of sections.

63. In the editing means of claim 60, and wherein: certain said editing instruction sequences include state change editing instructions for changing said values of said state data.

64. In the editing means of claim 63, and wherein: said input codes include control input codes; second certain said editing instructions of said first certain editing instructions correspond to said control input codes; said processor means responds to said second certain said editing instructions corresponding to a said control input code by setting said state value as specified by said corresponding said second certain editing instructions and receiving a next input code from said receiving means, whereby a said control code determines the manner in which said editing means responds to said next input code.

65. In the editing means of claim 60, and wherein: said editing table includes (iii) an initial portion containing a said buffer editing instruction sequence for execution by said processing means at commencement of operation of said editing means and (iv) a final portion containing a said buffer editing instruction sequence for execution by said processing means at termination of operation of said editing means.

66. In the editing means of any of claims 60 to 65, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said data codes, said input codes, and said display codes, (2) memory means responsive to memory signals from said processor means for storing said data and sequences of said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said input codes from said receiving means to said memory means, transferring said display codes from said memory means to said display means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means; said buffer memory means is contained in said memory means;; said control data memory means is contained in said memory means; said editing table memory means is contained in said memory means; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

67. In the editing means of any of claims 60 to 65, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) second processor means responsive to second instructions for processing second certain said data including said data codes, said input codes, and said display codes, (3) memory means responsive to memory signals from said first processor means and from said second processor means for storing said first certain data, said second certain data, first certain instruction sequences containing said first instructions, and second certain instruction sequences containing said second instructions, (4) means under control of said first processor means for transferring said first certain data between said memory means and said first processor means, said first instructions between said memory means and said first processor means, and said memory signals from said first processor means to said memory means, and (5) means under control of said second processor means for transferring said input codes from said receiving means to said memory means, transferring said second certain data between said memory means and said second processor means, transferring said second instructions from said memory means to said second processor means, transferring said display codes from said memory means to said display means, and transferring said memory signals from said second processor means to said memory means; said buffer memory means is contained in said memory means; said control data memory means is contained in said memory means; said editing table memory means is contained in said memory means;; said second certain instruction sequences include an editing means instruction sequence; and said processing means is said second processor means.

68. In the editing means of any of claims 60 to 65, and wherein: said data processing system includes (1) first processor means responsive to first instructions for processing first certain data including said data codes, (2) first memory means responsive to memory signals from said first processor means for storing said first certain data and first certain instruction sequences containing said first instructions, (3) terminal means for receiving said input codes to said data processing system and displaying said sequences of visual representations, said terminal means including (a) terminal receiving means for receiving said input codes, (b) terminal display means for displaying said sequences of visual representations in response to said display codes, (c) second processor means responsive to second instructions for processing second certain data including said input codes, said data codes, and said display codes, (d) second memory for storing said second certain data and second certain instruction sequences containing said second instructions, and (e) means under control of said second processor means for obtaining said input codes from said terminal receiving means, causing said terminal display means to respond to said sequences of display codes, transferring said second certain data between said second memory means and said second processor means, and transferring said second instructions from said second memory means to said second processor means, and (4) means under control of said first processor means for transferring said first certain data between said first memory means and said second memory means; said buffer memory means is contained in said second memory means; said control data memory means is contained in said second memory means; said editing table memory means is contained in said second memory means; said second certain instruction sequences include an editing means instruction sequence; said display means is said terminal display means; said receiving means is said terminal receiving means; and said processing means is said second processor means.

69. In the editing means of claim 68, and wherein: said first certain data further includes at least one said editing table and said editing table stored in said editing table memory means is a said editing table from said first certain data.

70. In the editing means of any of claims 60 to 65, and wherein: said data processing system includes (1) processor means responsive to instructions for processing data including said input codes, said data codes, and said display codes, (2) memory means responsive to memory signals from said processor means for storing said data and instruction sequences containing said instructions, (3) means under control of said processor means for transferring said data between said memory means and said processor means, transferring said input codes from said receiving means to said processor means, transferring said display codes to said display means, transferring said instructions from said memory means to said processor means, and transferring said memory signals from said processor means to said memory means, (4) in said memory means, a plurality of process state memory means for retaining state for executions of said instruction sequences for a user of said data processing system, said state including at least the location in said memory means of the next said instruction to be executed in one of said instruction sequences and (5) in said instruction sequences, a process control instruction sequence for temporarily associating one said process state memory means with said processor means and thereby causing said processor means to execute said instructions in said one of said instruction sequences for said user; said buffer memory means is contained in said memory means and is associated with one said process state memory means; said control data memory means is contained in said memory means and associated with one said process state storage means;; said editing table memory means is contained in said memory means; said instruction sequences include an editing means instruction sequence; and said processing means is said processor means.

71. In the editing means of any of claims 49 to 54 and 60 to 65, and wherein: certain said editing instruction sequences include (a) a range specifier specifying which of said input codes or said data codes correspond to said editing instruction sequence, (b) a size specifier specifying a number of bytes in said editing instruction sequence, and (c) at least one said editing instruction.

72. In the editing means of any of claims 49 to 54 and 60 to 65, and wherein: certain said editing instructions include (a) at least one operand byte representing certain data to be operated on by said processing means and (b) a single operation code byte, said at least one operand byte in said second certain said editing instructions precedes said single operation code byte, said memory means further includes operand memory means for storing said certain data represented by said operand bytes, and said processing means responds to a said certain said editing instruction by fetching said at least one operand byte, storing said certain data represented by said operand byte in said operand memory means, and on execution of said operation code byte, fetching said certain data from said operand memory means and using it in said execution of said operation code byte.

73. In the editing means of any of claims 49 to 54 and 60 to 65, and wherein: said editing table memory means includes writable memory means, whereby users of said editing means may alter said editing table or may provide a new said editing table for said editing means.

74. in the editing means of any of claims 49 to 54 and 60 to 65, and wherein: said editing table memory means includes read-only memory means containing a said editing table which may not be altered by users of said editing means.

75. In the editing means of any of claims 49 to 54 and 60 to 65, and wherein: said editing table memory means includes a plurality of said editing tables, each said editing table has an associated editing table identifier value, said memory means further includes editing table identifier memory means for storing a single said editing table identifier value, and said processing means responds to said editing table identifier value by locating one of said plurality of editing tables.

76. In the editing means of claim 75, and wherein: said editing table memory means includes (a) writable memory means and (b) read-only memory means, and said plurality of said editing tables includes (a) writable editing tables contained in said writable memory means and (b) read-only editing tables contained in said read-only memory means.

77. In a data processing system, the method of employing processing means responsive to state values contained in control data in memory accessible to said processing means and to editing instructions in editing instruction sequences contained in sections corresponding to said state values in an editing table in memory accessible to said processing means to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes received by said processing means from receiving means accessible to said processing means, said method comprising the steps of:: (1) receiving one input code of said input codes from said receiving means in said processing means; (2) determining in said processing means the address of a corresponding said editing instruction sequence corresponding to said one input code in a corresponding said section corresponding to said state value in said editing table using said input code and said state value; (3) receiving said editing instructions from said corresponding said editing instruction sequence in said corresponding said section of said editing table in said processing means; and (4) responsive to said editing instructions in said corresponding said editing instruction sequence, modifying by means of said processing means first certain data codes of said data codes.

78. In a data processing system, the method of employing processing means to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes including control codes received by said processing means from receiving means accessible to said processing means, said processing means being responsive to state values contained in control data in memory accessible to said processing means and to editing instructions in editing instruction sequences contained in sections corresponding to said state values in an editing table in memory accessible to said processing means, said editing instruction sequences including certain editing instruction sequences for setting said state values, and said method comprising the steps of:: (1) receiving one input code of said input codes from said receiving means in said processing means; (2) determining in said processing means the location of a corresponding said editing instruction sequence corresponding to said one input code in a corresponding said section corresponding to said state value using said input code and said state value; (3) receiving said editing instructions from said corresponding said editing instruction sequence in said corresponding said section of said editing table in said processing means; (4) if said one input code is a said control code, responsive to said certain editing instructions in said corresponding said editing instruction sequence, setting said state value to a new state value; (5) receiving a next input code of said input codes from said receiving means in said processing means;; (6) determining in said processing means the address of a corresponding said editing instruction sequence corresponding to said next input code in a corresponding said section corresponding to said new state value in said editing table using said next input code and said new state value; (7) receiving said editing instructions from said corresponding said editing instruction sequence for said next input code in said corresponding said section of said editing table for said new state value in said processing means; and (8) responsive to said editing instructions in said processing means, modifying by means of said processing means first certain data codes of said data codes.

79. In a data processing system, the method of employing processing means to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes received by said processing means from receiving means accessible to said processing means and to display visual representations on display means accessible to said processing means and responsive to display codes, said processing means being responsive to state values including at least an echo state value contained in control data in memory accessible to said processing means and to editing instructions in editing instruction sequences in an editing table in memory accessible to said processing means, said editing instruction sequences being contained in sections in said editing table corresponding to said state values and said sections including at least a display section corresponding to said echo value, and said method comprising the steps of: (1) receiving one input code of said input codes from said receiving means in said processing means; (2) determining in said processing means the address of a first corresponding said editing instruction sequence corresponding to said one input code in a corresponding said section corresponding to said state value in said editing table using said input code and said state value; (3) receiving said editing instructions from said first corresponding said editing instruction sequence in said corresponding said section of said editing table in said processing means;; (4) responsive to said editing instructions in said first corresponding said editing instruction sequence in said corresponding said section, modifying by means of said processing means first certain data codes of said data codes; (5) for each said data code of at least said first certain data codes, performing the steps of (a) setting said state value to said echo state (b) receiving said data code from said buffer in said processing means, (b) determining in said processing means the address of a second corresponding said editing instruction sequence in said display section of said editing table using said data code and said echo value, (c) receiving said editing instructions from said second corresponding said editing instruction sequence in said editing table in said processing means, and (d) responsive to said editing instructions in said second corresponding said editing instruction sequence, providing a sequence of said display codes to said display means.

80. In a data processing system, the method of employing processing means to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes including control codes received by said processing means from receiving means accessible to said processing means and to display visual representations on display means accessible to said processing means and responsive to display codes, said processing means being responsive to state values including at least an echo state value contained in control data in memory accessible to said processing means and to editing instructions in editing instruction sequences in an editing table in memory accessible to said processing means, said editing instruction sequences including certain editing instruction sequences for setting said state values, said editing instruction sequences being contained in sections in said editing table corresponding to said state values, and said sections including at least a display section corresponding to said echo value, and said method comprising the steps of: (1) receiving one input code of said input codes from said receiving means in said processing means; (2) determining in said processing means the address of a first corresponding said editing instruction sequence corresponding to said one input code in a corresponding said section corresponding to said state value in said editing table using said input code and said state value; (3) receiving said editing instructions from said first corresponding said editing instruction sequence in said corresponding said section of said editing table in said processing means;; (4) if said one input code is a said control code, responsive to said certain editing instructions in said corresponding said editing instruction sequence, setting said state value to a new state value; (5) receiving a next input code of said input codes from said receiving means in said processing means; (6) determining in said processing means the address of a corresponding said editing instruction sequence corresponding to said next input code in a corresponding said section corresponding to said new state value in said editing table using said next input code and said new state value; (7) receiving said editing instructions from said corresponding said editing instruction sequence for said next input code in said corresponding said section of said editing -table for said new state value in said processing means; and (8) responsive to said editing instructions in said processing means, modifying by means of said processing means first certain data codes of said data codes; and (9) for each said data code of at least said first certain data codes, performing the steps of (a) setting said state value to said echo state (b) receiving said data code from said buffer in said processing means, (c) determining in said processing means the address of a second corresponding said editing instruction sequence in said display section of said editing table using said data code and said echo value, (c) receiving said editing instructions from said second corresponding said editing instruction sequence in said editing table in said processing means, and (d) responsive to said editing instructions in said second corresponding said editing instruction sequence, providing a sequence of said display codes to said display means.

81. In a data processing system, the method of employing processing means responsive to state values contained in control data contained in memory accessible to said processor means, said state values including at least an echo state value, and to editing instructions in editing instruction sequences contained in sections corresponding to said state values in an editing table in memory accessible to said processing means, said sections including at least a display section corresponding to said echo state value, to modify data codes contained in a buffer in memory accessible to said processing means in response to input codes received by said processing means from receiving means accessible to said processing means, and to display visual representations on display means accessible to said processing means and responsive to display codes, said method comprising the steps of:: (1) receiving said data codes from said data processing system in to said buffer; (2) receiving said input codes from said receiving means until a delimiter code of said input codes is received and for each of said input codes except said delimiter code performing the steps of (a) determining in said processing means the location of a corresponding said section using said state value and the location of a first corresponding said editing instruction sequence in said corresponding said section using said input code;; (b) receiving said editing instructions from said first corresponding said editing instruction sequence in said editing table in said processing means, and (c) responsive to said editing instructions in said first corresponding said editing instruction sequence, modifying by means of said processing means first certain data codes of said data codes, (d) for each said data code of at least said first certain data codes, performing the steps of (i) setting said state value to said echo state value, (ii) receiving said data code from said buffer in said processing means, (iii) determining in said processing means the location of said display section using said echo state value and the location of a second corresponding said editing instruction sequence in said display section using said data code, (iv) receiving said editing instructions from said second corresponding said editing instruction sequence in said editing table in said processing means, and (iv) responsive to said editing instructions in said second corresponding said editing instruction sequence, providing a sequence of said display codes to said display device; and (3) on receipt of said delimiter code, responding to said delimiter code by returning said data codes in said buffer to said data processing system.

82. In the method of claim 81, and wherein: said memory accessible to said processing means contains a plurality of said editing tables; said step (1) further includes receiving a specifier from said digital computer system specifying one editing table of said plurality of said editing tables; and said processing means responds to said editing instructions from said one editing table in said step (2).

83. In the method of claim 81, and wherein: said step (1) further includes receiving said editing table from said data processing system.

84. In the method of claim 81,82 or 83, and wherein: said editing table includes an initial portion containing initial editing instructions of said editing instructions and a final portion containing final editing instructions of said editing instructions; said step (1) further includes receiving said initial editing instructions from said initial portion in said processing means and responding by means of said processor means to said initial editing instructions; and said step (3) further includes receiving said final editing instructions from said final portion in said processing means and responding by means of said processor means to said final editing instructions.