GB2120010A - Integrated circuit - Google Patents
Integrated circuit Download PDFInfo
- Publication number
- GB2120010A GB2120010A GB08303544A GB8303544A GB2120010A GB 2120010 A GB2120010 A GB 2120010A GB 08303544 A GB08303544 A GB 08303544A GB 8303544 A GB8303544 A GB 8303544A GB 2120010 A GB2120010 A GB 2120010A
- Authority
- GB
- United Kingdom
- Prior art keywords
- junction
- resistor
- island
- transistor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000694 effects Effects 0.000 abstract description 7
- 239000003990 capacitor Substances 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 239000004411 aluminium Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000002596 correlated effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000013641 positive control Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0658—Vertical bipolar transistor in combination with resistors or capacitors
Abstract
The invention relates to an integrated circuit comprising a capacitance constituted by a reverse-biassed pn junction (59,46). In order to compensate for the effect on the capacitance of batch-to-batch variations in the doping level of the less highly doped one (46) of the doped regions which define the junction the junction is reverse-biassed by the output signal of a control signal generator which includes a resistive element (47) comprising a further doped region provided with a pair of contacts (64,65). This further doped region is formed during the same doping step as the aforesaid less highly doped one (46) and is included in the generator in such a way that the junction reverse bias will be less the higher is the resistance value of the resistive element. <IMAGE>
Description
SPECIFICATION
Integrated circuit
The invention relates to an integrated circuit comprising a capacitance constituted by a pn junction which is arranged to be reversebiassed in operation, one of the doped regions defining said junction being less highly doped than the other of the doped regions defining said junction.
In such a circuit the level of doping of the less highly doped region largely determines the capacitance exhibited by the junction for given values of reverse-bias applied thereto.
This level of doping may vary from batch to batch when such integrated circuits are massproduced. It is an object of the invention to provide compensation for the effects of this variation of the capacitance.
The invention provides an integrated circuit comprising a control signal generator circuit and a capacitance constituted by a pn junction which is arranged to be reverse-biassed by the output signal of said control signal generator circuit in operation, one of the doped regions defining said junction being less highly doped than the other of the doped regions defining said junction and the control signal generator circuit including a resistive element comprising a further doped region provided with a pair of electrical contacts, which further doped region has the same conductivity type as has said one of the doped regions defining said junction and has been formed during the same doping step as has said one of the doped regions defining said junction, said resistive element being included in the control signal generator circuit in such manner that the output signal of said generator circuit will depend on the resistance value of said resistive element in such manner that said reverse bias will be less the higher is said resistance value.
An embodiment of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings in which
Figure 1 is a circuit diagram of a given integrated circuit, and
Figure 2 shows how certain elements of the circuit of Fig. 1 are constructed.
Fig. 1 shows the circuit diagram of a given integrated circuit. The circuit of Fig. 1 comprises a pass filter included between input terminal 3 and output terminal 9, the capacitive element of this pass filter being a capacitor 13, and the inductive element thereof, connected in parallel with capacitor 13, being one port 14 of a gyrator circuit the other port 15 of which is loaded by a capacitor 16. In conventional manner the gyrator circuit comprises a non-inverting voltage-controlled current source circuit coupling the port 14 to the port 16 and an inverting voltage-controlled current source circuit coupling the port 16 to the port 14. The non-inverting source circuit comprises a pair of transistors 17 and 18 respectively the emitters of which are connected to ground via resistors 19A and 19B respectively of equal value and a current source 20 which is common to both transistors.The collectors of these transistors are fed from the positive supply line via current sources 21 and 22 respectively. The base of transistor 17 constitutes the input of this source circuit and is connected to capacitor 13, and the common point of the collector of transistor 18 and current source 22 constitutes the output of this source circuit and is connected to capacitor 16. The base of transistor 18 is connected to ground. The inverting source circuit comprises a transistor 23 the emitter of which is connected to ground via a resistor 24A and a current source 25 and the collector of which is connected to the positive supply line via a current source 26.
The base of transistor 23 constitutes the input of this source circuit and is connected to capacitor 16, and the common point of tne collector of transistor 23 and the current source 26 constitutes the output of this source circuit and is connected to capacitor 13. The input terminal 3 is coupled to the parallel combination of the port 14 and the capacitor 13 via a transistor 27 the collector of which is connected to the positive supply line and the emitter of which is connected to the common point of the resistor 24A and the current source 25 via a resistor 24B of equal value to resistor 24A. The terminal 3 is connected to the base of transistor 27.The parallel combination of the port 14 and the capacitor 13 is coupled to the output terminal 9 9 via transistor 17, output terminal 9 being connected to the common point of the collector of this transistor and the current source 21. Resistors 24A and 24B are constituted by a centre-tapped shallow p-type zone in an ntype island in the semiconductor chip in which the integrated circuit is formed, as will be described in more detail hereinafter, the junction between this zone and island being reverse-biased. The said island is shown diagrammatically at 28. (In fact resistors 19A and 19B are constituted in a similar way.)
This structure forms a phase-shifting arrangement 6.
The circuit of Fig. 1 also comprises a control signal generator circuit 11 the output 10 of which is connected to the control input 7 of the phase-shifting arrangement 6, i.e. to the aforesaid n-type island. Circuit 11 comprises a transistor 29 the base and collector of which are connected together and to ground via a current source 30 and the emitter of which is connected to the positive supply line via a resistor 40, and a transitor 31 the emitter of which is connected to the positive supply line via the series combination of resistors 32 and 33, the base of which is connected to the common point of current source 30 and the base and collector of transistor 29, and the collector of which is connected to ground via the series combination of resistors 34 and 35.
The common point of the collector of transistor 31 and resistor 34 is coupled to the output 10, for impedance matching purposes, via an emitter follower circuit of the Darlington type, this emitter follower circuit comprising transistors 36 and 37 the collectors of which are connected to the positive supply line. The base of transistor 36 is connected to the common point of the collector of transistor 31 and resistor 34, the emitter of transistor 36 is connected to the base of transistor 37 and to the emitter of transistor 37 via a resistor 38, and the emitter of transistor 37 is connected to the output terminal 10 and to ground via a resistor 39. The components 29-33 and 40 form a "current mirror" circuit, a current which is in a specific ratio to the current produced by source 30 being carried by the collector of transistor 31.Thus, if the base current of transistor 36 is neglected, a predetermined constant current is passed through resistors 34 and 35 and hence a d.c. voltage proportional to their values is set up across these resistors and is fed to the output terminal 10 via the emitterfollower circuit 36-39.
Resistor 34 is constructed as a so-called "base under emitter" resistor as will be described in more detail hereinafter. It comprises doped zones which correspond to collector, base and emitter zones respectively of the transistors 17, 18, 23 and 27 and which have each been formed during the same doping step as have the corresponding zones of said transistors. As will become clear hereinafter the value of resistor 34 is in consequence related to the base widths of said transistors; the smaller these widths are the larger is the value of resistor 34 and hence the larger is the voltage at the output terminal 10.As will be evident, the potential at terminal 10 governs the reverse-bias between the n-type island 28 and the p-type zone which constitutes the resistors 24A and 24B; the higher the potential at output 10 the higher this reverse-bias will be and hence the lower the capacitance will be between the p-type zone forming resistors 24A and 24B and the n-type island 28. Because this island is effectively at ground potential as far as a.c. signals are concerned and because the emitter of transistor 27 presents a lo#? impedance to the end of resistor 24B connected thereto, the emitter of transistor 23 is in effect connected to earth via the parallel combination of the resistor 24 and the said capacitance.The presence of this parallel combination will therefore result in signals transmitted by transistor 23 from port 15 to port 14 being advanced in phase relative to the phase which they would otherwise have, the amount of phase advance occurring being greater the larger is the value of the said capacitance, i.e.
the larger are the base widths of the transistors 17, 18, 23 and 27. The larger these base widths are the lower the transition frequencies of these transistors will be and hence the greater will be the phase lag created by these transistors. The total phase lag created by the transistors 17, 18 and 23 is the important one in the circuit of Fig. 1 (these being the transistors included in the gyrator circuit) and the control signal generator circuit 11 is constructed so that this total lag is substantially exactly compensated for by the phase lead produced in the aforesaid parallel combination. (The purpose of providing resistor 35, which dilutes the effect of changes in the value of resistor 34, is to assist in achieving this end.)
The actual capacitance occurring between the p-type zone constituting the resistance 24A, 24B and the n-type island 28 for specific values of the positive control voltage applied to island 28 will, as is known, depend on the degree of doping of said n-type island (the doping concentration in which is less than that in the said p-type zone). Consequently, if steps were not taken to counteract its effect, variations in the degree of doping of island 28 which are liable to occur from batch to batch when integrated circuits as described are mass-produced would be liable to result in incomplete or overcomplete compensation for the phase lags produced by the transistors 1 7, 18 and 23 being obtained.In order to mitigate this effect the resistor 33 is constructed as an isolated island of the integrated circuit, the doping of this island being carried out during the same doping step as the doping of the island 28. The lower the degree of doping of the island 28 the lower will be the capacitance between this island and the zone constituting resistor 24A, 24B, and conversely. Because the island forming resistor 33 is formed during the same doping step as is the island 28 the lower the degree of doping of the island 28 is the lower will be the degree of doping of the island forming resistor 33 and hence the higher will be the value of resistor 33. The higher the value of resistor 33 is the lower will be the current carried by the collector of transistor 31 and hence the lower will be the voltage across resistors 34 and 35 and hecne at output 10, resulting in increased capacitance between the zone forming resistor 24A and the island 28, thereby compensating for the reduced capacitance due to the doping level of island 28 being too low. Obviously the circuit operates in the converse manner if this doping level is too high. Control signal generator circuit 11 is constructed in such manner that the dependence of the voltage at its output 10 on the value of resistor 33 is such that variations in the doping level of the island 28 are substantially exactly compensated for in this manner.
Resistor 32, which dilutes the effect of variation in the value of resistor 33, is provided to assist in achieving this end.
In practice the base of each of the transistors 17, 18 and 23 may be fed via an individual emitter-follower (not shown) having an emitter load resistor the value of which is in the order of, for example, 10 kohms. Such emitter followers can provide d.c. level shifts where required because of the d.c. couplings used. The values of each the centre-tapped resistors 19 and 24 may be, for example, in the order of 1 kohm. The various ("constant") current sources may be constituted, for example, by high-value resistors or by suitably biased transistors in common-emitter mode (pnp transistors for the sources 21, 22 and 26 and npn transistors for the sources 20 and 30). The values of the resistors 32, 34 and 39 may be for example, in the order of 1 kohm, those of the resistors 35 and 38 in the order of 10 kohm and that of resistor 33 in the order of 100 ohms.The values of resistor 40 and the output current of current source 30 may be chosen so that the collector current of transistor 31 is approximately 500 yA, giving approximately + 5 volts at output 10.
The positive supply rail may carry 12 volts with respect to ground.
Fig. 2 shows how the transistor 1 7, the resistor 34, the tapped resistor 24, and the resistor 33 of Fig. 1 may be constructed in integrated circuit form. (The transistors 18, 23 and 27 of Fig. 1 may each be constructed in the manner shown for the transistors 17 and the resistors 32 and 35 of Fig. 1 may each be constructed in the manner shown for the resistor 24 but with the tap omitted.) Fig.
2 is a perspective view (not to scale) of the significant components of those parts of the semiconductor chip on which the circuit of
Fig. 1 has been fabricated which comprise the transistor 17, the resistor 34, the tapped resistor 24, and the resistor 33, these parts having themselves been sectioned along their axes of symmetry in a plane at right angles to the plane of the chip, so that the surface 41 has become exposed. The chip is in the form of a p-type substrate 42 on which has been formed an n-type epitaxial layer 43. Layer 43 is divided electrically into first, second, third and fourth islands 44, 45, 46 and 47 respectively by a p+ isolation diffusion 48. Island 44 forms the collector of transistor 17 and is provided with an aluminium contact 49, contact 49 contacting island 44 via a shallow n+ diffused zone 75 formed in island 44.The base zone 50 of transistor 17 is formed by a shallow p-type diffusion in island 44 and is provided with an aluminium contact 51. The emitter zone 52 of transistor 17 is formed by a shallow n-type diffusion in base zone 50 and is provided with an aluminium contact 53. Resistor 34 of Fig. 1 is formed in island 45 and comprises a shallow p-type diffused zone 54 provided with aluminium contacts 55 and 56. Overlying the part of the zone 54 which extends between the contacts 55 and 56 is provided a shallow n-type diffused zone 57 each end of which (only end 58 is shown) extends into the n-type material of the island 45, so that a so-called "base under emitter" resistor is formed. Resistor 24A, 24B of Fig.
1 is constituted by a shallow p-type zone 59 formed by diffusion in island 46, this zone being provided with an aluminium contact 60 which constitutes the centre tap of the resistor and aluminium contacts 61 and 62 which constitute the two ends of the resistor. Island 46 corresponds to island 28 in Fig. 1 and is provided with an aluminium contact 63, contact 63 contacting island 46 via a shallow n+ diffused zone 76 formed in island 46. Resistor 33 of Fig. 1 is constituted by the material of the island 47, which is provided with aluminium contacts 64 and 65, these contacts contacting island 47 via shallow n + diffused zones 77 and 78 respectively formed in island 47. During manufacture of the integrated circuit islands 44, 45, 46 and 47 are all formed during the same doping step (the formation of the epitaxial layer 43), zones 50, 54 and 59 are all formed during the same doping step, and zones 52 and 57 are all formed during the same doping step, resulting in the value of the resistor 54, 55, 56, 57, 58 being correlated to the base width (collector to emitter distance) of transistor 44, 49, 50, 51, 52, 53 and the value of resistor 47,.
64, 65 being correlated to the doping level in island 46, as required.
Claims (1)
1. An integrated circuit comprising a control signal generator circuit and a capacitance constituted by a pn junction which is arranged to be reverse-biassed by the output signal of said control signal generator circuit in operation, one of the doped regions defining said junction being less highly doped than the other of the doped regions defining said junction and the control signal generator circuit including a resistive element comprising a further doped region provided with a pair of electrical contacts, which further doped region has the same conductivity type as has said one of the doped regions defining said junction and has been formed during the same doping step as has said one of the doped regions defining said junction, said resistive element being included in the control signal generator circuit in such manner that the output signal of said generator circuit will depend on the resistance value of said resistive element in such manner that said reverse bias will be less the higher in said resistance value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08303544A GB2120010B (en) | 1979-05-10 | 1983-02-09 | Integrated circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7916196 | 1979-05-10 | ||
| GB08303544A GB2120010B (en) | 1979-05-10 | 1983-02-09 | Integrated circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8303544D0 GB8303544D0 (en) | 1983-03-16 |
| GB2120010A true GB2120010A (en) | 1983-11-23 |
| GB2120010B GB2120010B (en) | 1984-05-23 |
Family
ID=26271464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08303544A Expired GB2120010B (en) | 1979-05-10 | 1983-02-09 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2120010B (en) |
-
1983
- 1983-02-09 GB GB08303544A patent/GB2120010B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB8303544D0 (en) | 1983-03-16 |
| GB2120010B (en) | 1984-05-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19970403 |