GB2117582A - Synchronising circuit for phase-locking repetitive signals, e.g. television signals - Google Patents

Abstract

A television or video synchronising circuit 10 is designed to provide from clock pulses a burst-locked oscillator 16 (or input sync-locked flywheel oscillator for monochrome operation) output line waveforms defined in a generator 22 and which are accurately phase locked with respect to input line sync pulses at terminal 14. A horizontal counter 20 counts the clock pulses, and waveform generator 22 provides a line pulse once per cycle of the counter on a line 26. A phase detector 30 determines the phase error between these line pulses and input line syncs and applies it to an accumulator 32. In normal operation the accumulator is reset before each phase error measurement and a phase detector 34 determines when the error is of sufficient magnitude or persistence to require correction, whereupon mode switch 36 is switched into a correction mode and the error standing in the accumulator is loaded by gate 38 into the counter 20 as an initial correction. Then the accumulator 32 accumulates the residual phase error for 256 active lines as counted in counter 40, at the end of which period the error is averaged and loaded by gate 42 as a fine correction to the counter 20. <IMAGE>

Description

SPECIFICATION Synchronising circuit for phase-locking repetitive signals, e.g. television signals This invention relates to a synchronising circuit for providing from a first cyclical signal an output cyclical signal which is accurately timed (e.g. phase locked) with respect to a second cyclical signal.

In television or video applications generally, waveforms are needed which are phase-locked to the horizontal and vertical synchronising (sync) pulses of the signal. This is so even though the input signal may suffer a "non-sync cut", where the line and field phases may change arbitrarily.

In a conventional system, the waveforms are phase locked to the synchronising pulses of the input signal, using line syncs and field or picture syncs to lock horizontal and vertical waveform generators. Such systems are not fully satisfactory, in that the sync pulses may be distorted or affected by noise or picture information. Thus it is difficult to obtain precise reliable timing information from these sync pulses. A conventional circuit may, for instance, use the line sync to correct the phase of the horizontal waveform generator only when an error occurs which is larger than a predetermined value, otherwise allowing the generator to 'flywheel'.Such methods thus have a range of timing errors, typically of one microsecond, within which no errors are detected, and when an error is detected of greater than this magnitude the generator is rephased using one line sync pulse and further errors within one microsecond of the line sync which was used forthe rephasing would be ignored.

The present invention is defined in the appended claim to which reference should now be made.

In an embodiment of such a synchronising circuit employed in a television system a control system monitors the phase difference between the output of a horizontal waveform generator and the input line sync, giving an indication when a selected number of errors (from one upwards) have been detected. An initial phase correction is made as soon as such an error is detected, thus ensuring that the generator is substantially correctly phased as quickly as possible.

Then the average phase error of a much larger number of lines is determined, and a second phase corrrection implemented on the basis of the mean position of the line syncs for this larger number of lines. The small timing range (typically one microsecond) is always set symmetrically about the true mean position of the line sync pulses, but this result is achieved without undue delay in making at least some correction of the phase error.

The invention will now be described in more detail by way of example with reference to the drawings, in which Figure 1 is a block circuit diagram of a simplified and somewhat diagrammatic synchronising circuit embodying the invention for use with television signals; Figure 2 is a block circuit diagram of a more complex practical synchronising circuit providing both vertical and horizontal output waveforms; and Figure 3 is a block circuit diagram illustrating the controller shown in Figure 2.

The numerical values given in the following description are those appropriate to a 625/50 PAL colour television system. Appropriate alteration should be made for television or video systems on other standards.

Referring first to Figure 1 the synchronising circuit 10 illustrated receives at an input 12 the colour subcarrier bursts of a PAL colour television signal and at an input 14 the line synchronising (sync) pulses of the PAL signal. These can be separated out from an encoded PAL signal by suitable sync separator circuitry or can be provided independently or in any other convenient way. The colour subcarrier bursts are applied to a burst locked oscillator 16 of known type to produce clock pulses at colour subcarrier frequency fsc or a multiple thereof such as three times the colour subcarrier frequency 3fsc.

These clock pulses are applied to the count input of a clock pulse counter 20 which we term the horizontal counter. The counter 20 counts from zero upwards during each line of the television signal and the count is monitored by a waveform generator 22 to provide a line frequency waveform of any desired type at an output 24. The generator 22 detects when the count in the counter corresponds to exactly one line scan and provides at an output 26 a line pulse.

For example where the clock pulses are at 3fsc in the 625/50 PAL system, the generator22 provides a line pulse whenever the count is 850. This is used on the next clock pulse to clear or reset the counter 20 to zero, thus restarting a new line.

Thus so long as 3fsc clock pulses continue to be received by the counter 20 it will continue to cycle or 'flywheel' on a line periodic basis.

In order to synchronise this flywheel operation of the counter 20 with the input line sync pulses received at input 14, a phase error detector 30 receives both the input line sync pulses and the line pulses from waveform generator 22. The detector 30 provides signals which represent the sign and the magnitude of any phase error between the input line syncs and the line pulses from the horizontal counter.

These signals from the detector 30 are applied to a phase error accumulator 32 which produces an error signal in the form of a number representing the phase error in terms of a number of clock periods. At this point each error signal applied to the accumulator 32 from the detector 30 replaces the previous signal held in the accumulator 32. If at any time the magnitude of the error received by the accumulator exceeds a small value (e.g. 6 or 7 clock pulses), this is detected by an error detection circuit 34 which activates a mode switch 36 to change the operation from an "error detection" mode to an "error measurement and correction" mode.The error detection circuit 34 may activate the mode switch immediately that an error outside the preset range is detected, or may alternatively only activate the mode switch when several such errors are detected within a predetermined small period, this giving a degree of immunity to spurious operation.

In either event, once the mode switch 36 is activated it instructs a first load switch 38 to apply the error in the phase error accumulator to the horizontal counter as a correction signal. The error count in the accumulator 32 is thus loaded into the counter 20 to vary the start point of the count from zero by an amount sufficient to cancel out the phase error. This completes the first part of the error correction sequence.

However, the error correction sequence does not stop there. Nowthe mode switch simultaneously instructs the accumulator 32 to accumulate successive phase error measurements provided by the phase error detector 30, and starts a counter 40 which counts 256 line pulses provided for example from the generator 22. These are arranged to cover the 256 active lines of one field.

After 256 such line periods the counter 40 enables a line switch 42 which is arranged to divide the accumulated count in the counter 32 by 256 to give a measure of the average phase error during 256 line periods. This average error is then loaded into counter 20 to provide a fine correction of the actual phase error, again by causing the counter to start from an appropriate value other than zero. At the same time the mode switch 36 is reset.

It should be noted that because the accumulator count which caused the detector 34 to trigger has already been loaded into the counter 20 by load switch 38, the second or fine phase of the measurement operation is carried out after an intitial coarse timing correction has been effected. Thus a coarse correction is provided as soon as possible while the accuracy of the eventual correction is high.

Figures 2 and 3 show a more complex practical system incorporating the essence of the system shown in Figure 1. Where appropriate correspond ing parts have been given the same reference numerals.

The system of Figures 2 and 3 is capable of operation either with monochrome signals or with colour signals. When used with monochrome sig nals the clock pulses are derived from the line sync pulses, but when used with colour signals the clock pulses are derived from the subcarrier burst as in Figure iA A 'mono/colour' signal received at an input 50 switches the circuitry between the two conditions. The system will first be described for use with colour signals with brief mention only being made of the components for monochrome operation which will be described subsequently.

As shown in Figure 2, the circuit includes a sync pulse separator 52 connected to receive mixed synchronising pulses from an input 54 and to provide line sync and picture sync pulses on respective lines. A vertical counter 56, which counts line pulses, is reset by the picture syncs. and has its count decoded by PROMs (programmable read-only memories) 58 which provide desired vertical frequency waveforms at an output 60. The PROMs 58 also generate three control signals, namely field sync pulses, a field blanking signal, and a signal identifying the alternate lines (even or odd) of the PAL signal.

The horizontal counter 20 counts clock pulses received from burst locked oscillator 16, and is decoded by PROMs 22 constituting the waveform generator to provide horizontal waveforms at output 24 and line pulses on line 26.

The burst locked oscillator 16 is essentially of conventional construction and includes a burst phase comparator 62 coupled to the burst input 12 and to the output of a clock oscillator 64 which it also controls. A switch 66 enables the control from the comparator 62 to be interrupted in response to the mono/colour signal at input 50 indicating monochrome operation and substituted by control from a so-called charge pump 68 which is itself controlled by the phase detector 30 (Figure 3).

The phase detector 30 and associated circuitry form part of a controller 70 shown in Figure 2 and the block circuit diagram of which is given in Figure 3.

In the particular example described, the oscillator oscillates at the colour subcarrier frequency and the oscillator output is modified in a frequency modifier 72 to provide circuit clock pulses for the horizontal counter 20, etc. This clock signal has an instantaneous frequency of three times the colour subcarrier frequency, and is then perturbed to give a field-locked structure in which there are 851 clock pulses per line. This gives a discontinuity of approximately 19ns (one-twelfth of a subcarrier period) once per line and a discontinuity of approximately 113 ns (one-half of a subcarrier period) once per field. These discontinuities are arranged to occur during the line and field sync pulses.

In normal operation, the horizontal counter 20 counts from zero to 850 and is then reset to zero by its own decoded line pulse from line 26, this being routed through the controller 70. The counter 20 cannot use the line sync pulse from the sync separator 52 as a timing reference because these are subject to phase disturbances due to picture information, noise, or distortion. The vertical counter 56 counts from zero to 624, using line pulses from line 26 derived from the horizontal counter output, and is reset to zero by picture sync pulses from the sync separator 52. Thus the vertical counter 56 has the phase stability of the horizontal counter 20, but is reset by the picture sync pulses the stability of which is adequate for this purpose.The horizontal counter 20 is brought into the correct phase relationship with the line syncs by the controller 70 as will now be described with reference to Figure 3.

The controller includes the phase error detector 30, phase error accumulator 32, and error detector 34 of Figure 1,togetherwith a control memory (PROM) 74, which takes over the functions of and may be regarded as equivalent to the elements 36 to 42 of Figure 1 and also provides certain further control functions as will become apparent. The phase error detector 30 produces signals to drive the charge pump circuit 68 for use when the clock oscillator is to be operated in the sync-locked (monochrome) mode. It also produces waveforms which describe the sign and magnitude of the phase error between line syncs from the sync separator 52 and line pulses from the horizontal counter 20 supplied on line 26.

As with Figure 1 the controller 70 operates in two modes, namely error detection and error measure ment. In this instance the detection mode is slightly different from burst-locked clock (colour) and synclocked clock (monochrome) operation.

Detection is only permitted during 256 lines of each active field in order to avoid effects due to field rate disturbance of the line syncs, and this is effected by the control PROM 74 on the basis of the field blanking signal received from the PROMs 58.

Sign and magnitude information from the phase error detector 30 is fed to the phase error accumulator 32 which produces, conveniently on alternate lines only, an error signal in the form of a number representing the phase error in terms of a number of clock periods. This facilitates the use of the accumulator alternately for accumulation and measurement.

If the magnitude exceeds a preset small value le.g.

equivalent to approximately 0.5 microseconds) then the error detector 34 registers a measurement and, in burst-locked operation, a 'non-sync cut flag' signal is outputted on a line 76 as an indication for use in associated apparatus that a non-sync cut may have occurred in the video signal and thus that the horizontal counter may be about to be rephased. The 'flag' is held for about 3ms. If, during that time, the error detector 34 registers 15 more such errors, then an 'error' signal is sent to the control PROM 74 which immediately changes into the measurement mode.

Throughout this operation the horizontal counter 20 continues to be reset to zero by its own decoded line pulses. thus operating as a flywheel.

When entering the measurement mode, the control PROM 74 instructs the accumulator 32 to apply the count it contains to the horizontal counter 20 as a correction signal, and this is loaded into it as a non-zero start point Thus the final phase error measurement which triggered the detector 34 is immediately used to make a coarse correction of the horizontal counter 20 and hence of the line pulse timing. Thus for one line only the counter 20 starts from such a number as would bring it to approximate phase accuracy and then it reverts to flywheeling for the rest of the measurement process.

During the measurement mode, the phase errors continue to be detected in the detector 30 and their magnitude applied to the accumulator 32. The accumulator is now instructed by the controller 74to accumulate these measurements for 256 active lines and then to take the average. Thus at the end of this time the accumulator 32 produces a number which represents in terms of clock periods the remainder of the phase error after the initial correction was made which used only one measurement. After this average error has been found the PROM 74 reverts to the detection mode while the average error signal is again loaded into the counter 20 to act as a fine correction.

The 'non-sync cut flag' on line 76 is held at all times, while in the measurement mode and for a further 20 ms thereafter, to allow time for the detection of any remaining or subsequent errors.

Thus it is seen that the horizontal counter is rephased only when a signal timing disturbance has been detected and confirmed, the counters are initially corrected as soon as possible and finely corrected after integration of many measurements.

A 'flag' is 'raised' to indicate the onset of timing perturbations and is 'lowered' only when the counters have been set correctly to be in phase with the input signal.

In monochrome operation the sequence is essentially the same except for the detection mode which differs as follows. In this case the 'error' signal is produced by the error detector 34 as soon as it registers the first phase error, the flag is raised, the PROM 74 immediately changes the control system to the measurement mode, and signals from the phase error detector 30 to the charge pump 68 are stopped.

In this way the clock oscillator 64 is not unnecessarily disturbed by mis-timed sync pulses. In this case the clock pulses are of course at an appropriate multiple of the line frequency.

The synchronising circuits described are designed for use with television or analogous video display systems, but the principles of operation of the circuits are applicable more generally to synchronising circuits for providing from a first cyclical signal (cf. the clock pulses) an output cyclical signal (ci. the horizontal waveforms) which is accurately timed with respect to a second cyclical signal Icf. the burst input or input line syncs). The synchronising circuit has particular application where the first cyclical signal is of much higher instantaneous frequency than the second cyclical signal andlor where portions of a signal from which the first cyclical signal is derived are absent. both of which apply with the burst-locked clock system described. The circuits illustrated operate to provide correction in terms of a multiple of the period of the first cyclical signal, it being noted that the first and second cyclical signals are not locked to each other accurately, if at all.

Claims (1)

1. CLAIM

   7. A synchronising circuit for providing from a first cyclical signal an output cyclical signal which is accurately timed with respect to a second cyclical signal, and comprising: a first cyclical signal generator for generating a first cyclical signal; a cyclical counter for cyclically counting cycles of the first cyclical signal and for providing an output once per cycle of the counter; phase comparison means connected to receive the output of the cyclical counter and a second cyclical signal and for providing a phase error signal representing the phase difference therebetween; and error detection and correction means coupled between the phase comparison means and the cyclical counter and operative when the phase error signal indicates an unacceptable error: (a) forthwith to correct the cyclical counter by a coarse correction dependent upon the said phase error signal, (b) then to average the magnitude of the phase error signal for a plurality of cycles of the cyclical counter and of the second cyclical signal, and (c) thereafter to correct the cyclical counter by a fine correction dependent upon the said average.