GB2113907A - Reverse-breakdown PN junction devices - Google Patents

Reverse-breakdown PN junction devices Download PDF

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Publication number
GB2113907A
GB2113907A GB08138575A GB8138575A GB2113907A GB 2113907 A GB2113907 A GB 2113907A GB 08138575 A GB08138575 A GB 08138575A GB 8138575 A GB8138575 A GB 8138575A GB 2113907 A GB2113907 A GB 2113907A
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United Kingdom
Prior art keywords
region
junction
buried
semiconductor device
reverse
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GB08138575A
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GB2113907B (en
Inventor
Stephen Wilton Byatt
Richard Anthony Rodrigues
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Texas Instruments Ltd
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Texas Instruments Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

A semiconductor device has a PN junction between first and second regions 1, 2 and which includes, adjacent to the junction and in the first region 1 which is of lower impurity concentration than the second region 2, a buried region 3, 3A, 6 of the same conductivity type as the first region and of higher impurity concentration than the first region. The effect of the buried region is such that, in the intended operation of the device with reverse-breakdown of the junction, the breakdown occurs through the buried region in the device bulk rather than where the junction meets the surface of the first region. <IMAGE>

Description

SPECIFICATION Improvements in and relating to semiconductor junction devices The invention relates to semiconductor junction devices.
Some semiconductor junction devices are intended for operation in a state where there is reverse-voltage breakdown of a junction without damage to it. Reverse voltage breakdown takes place in devices used as voltage references or in devices used as surge suppressers, for example.
A simple PN junction does not generally meet the requirements for reverse-breakdown operation, since, in practice, reverse-breakdown occurs at a relatively unpredictable voltage where the junction meets a surface of the P and N regions. Reverse-breakdown would occur in the PN bulk at a more predictable voltage which is above that at which reverse-breakdown occurs in practice.
Apart from the fact that reverse-breakdown of a simple PN junction recurs at an unpredictable voltage level, there is the difficulty that the breakdown takes place in a small part of the P and N regions, which results in localised heating in the breakdown region, making it likely that there will be overheating and the junction will be damaged by the flow of a relatively small current.
The present solutions to the problems of achieving a predictable reverse-breakdown voltage relay on encouraging reverse-breakdown in the PN bulk by so modifying the junction structure that, under reverse bias, there is less electrical stress where the junction meets a surface of the P and N regions than in the PN bulk. These solutions achieve the desired result at the penalty of a complex junction structure and consequently increased unit cost.
It is an object of the present invention to achieve the desired result of a predictable reverse-breakdown voltage in a PN junction device by means of a simpler structure than hitherto proposed.
According to the invention, a semiconductor device includes a PN junction between first and second regions in which, in the intended operation of the device, reverse-break-down of the junction occurs, there being provided, adjacent to the junction and in the first region which is of lower impurity concentration than the second region, a buried region of the same conductivity type as the first region and of greater impurity concentration than the first region, so that reverse-breakdown of the junction occurs through the buried region.
The first region may be a substrate region.
The buried region and the second region may both be islands in the first region, the buried region and the second region both falling in impurity concentration with penetration into the first region, the buried region being of initially lower impurity concentration than the second region and falling in concentration at a lower rate than the second region.
The buried region may have an initial impurity concentration of 1017 atoms/cc and the second region may have an initial impurity concentration of 10'9 atoms/cc. in a substrate region having an impurity concentration of 10'5 atoms/cc.
The impurity concentrations of the buried region and the second region may fall to that of the first region in about 40 microns and 20 microns, respectively.
The semiconductor device may be a semiconductor junction diode having a buried region as defined at the junction.
The semiconductor device may include a fourlayer diode (PNPN) device having a buried region, as defined, at the or each junction which, in operation, is reverse biased.
The semiconductor device may include a plurality of four-layer diode (PNPN) devices having respective buried regions, as defined, at junctions which, in operation, are reverse biased.
The or each four-layer diode (PNPN) device may be a bi-directional deviecs.
The or each four-layer diode (PNPN) device may have a planar junction structure.
The or each buried region may be an ionimplanted region.
According to another aspect of the invention, a method of fabricating a semiconductor device which includes a PN junction between first and second regions in which, in the intended operation of the device, reverse-breakdown of the junction occurs, includes the step of providing, in the first region and adjacent to the junction, a buried region of the same conductivity type as the first region and of greater impurity concentration than the first region, so that reverse-breakdown of the junction occurs through the buried region.
The method may include the step of ionimplanting the buried region and the second region in the first region.
The method may include the step of so treating the first, second and buried regions as to cause diffusion of the ion-implanted regions.
Semiconductor devices according to the invention will now be described by way of example only and with reference to the accompanying drawings, in which: Fig. 1 is a diagrammatic representation of a PN junction diode with a buried N-type region in Ntype bulk material, and including a representation of the depletion layer distribution under reverse bias conditions.
Fig. 2 is a graphical representation of the doping pattern in the PN junction diode, Fig. 3 is a diagrammatic representation of the structure of a four-layer (PNPN) device of part planar construction, with a buried N-type region in an N-type substrate, Fig. 4 is a diagrammatic representation of the voltage to current characteristics of the four-layer device of Fig. 3, Fig. 5 is a diagrammatic representation of a four-layer device which includes symmetrically placed buried N-type regions, Fig. 6 is a diagrammatic representation of the voltage to current characteristic obtainable for the four-layer device of Fig. 3 by unequal doping of the buried N-type regions, Fig. 7 is a diagrammatic representation of a dual planar four-layer device which includes buried N-type regions, Fig. 8 is a diagrammatic representation of the variation of breakdown voltage with doping level for a junction with a normal breakdown voltage of around 600 V, Fig. 9 is a diagrammatic representation of the variation of breakdown voltage with the surface concentration level of phosphorus dopant, Fig. 10 is a circuit diagram representation of a spark generator including a four-layer device according to the invention, and Fig. 11 is a circuit diagram representation of a discharge lamp circuit including as a lamp starter, a four-layer device according to the invention.
With reference to Fig. 1, a semiconductor junction diode consists of an N-type substrate 1 and a diffused P-type region 2 formed in the Ntype substrate 1. A suitable N-type dopant is phosphorus and a suitable P-type dopant is boron.
The diode has a conventional planar junction which has a selectively flat central region and curved edge regions which terminate at the surface of the N-type substrate 1. A buried N-type region 3 lies in the N-type substrate 1, adjacent to the central region of the planar junction. The Ptype region 2 has a higher impurity concentration than both the N-type substrate 1 and the buried N-type region 3, while the buried N-type region 3 has a higher impurity concentration than the substrate 1.
Fig. 2 represents the impurity concentration profile of the PN junction diode of Fig. 1. As shown in Fig. 2, the P-type region 2 extends from the surface of the diode to a depth of about 20 microns and varied in impurity concentration from a maximum level of about 1019 atoms/cc to that of the N-type substrate 1 which is 1015 atoms/cc.
The buried N-type region 3 extends from the surface of the diode to a depth of about 40 microns and varies in impurity concentration from a maximum level of about 1017 atoms/cc to that of the N-type substrate 1. The P-type region 2, being initially of higher impurity concentration than the buried N-type region 3, is the dominant region to a depth of some 1 5 microns. The buried N-type region 3 dominates in the depth range from some 15 to 40 microns.
The presence of the buried N-type region 3 causes a reduction in the reverse-breakdown voltage for the junction in the material bulk. The extent of the possible reduction in the reversebreakdown voltage is shown in Fig. 10 which applied to an ion implanted phosphorus-doped region 3 implanted at between 1013 and 20x 1013 atoms/cm2. It will be noted that the reversebreakdown voltage falls linearly from about 250 volts to about 70 volts for the dose range 1013 to 20x 1013 atoms/cm2.
The voltage for reverse-breakdown through the buried N-type region 3 is chosen to be below the reverse-breakdown voltage where the planar junction terminates at the surface of the N-type substrate 1 and the P-type region 2.
In Fig. 3 is shown a four-layer diode in which a buried N-type region 3 is provided in a lightly doped N-type region 1 at a junction with a more heavily doped P-type region 2. As is explained with reference to Fig. 2, the P-type region 2 overdopes the buried N-type region 3 and extends to a depth of some 20 microns from the surface of the device. The remainder of the four-layer diode is of conventional planar construction with a P-type anode region 5 and an N-type cathode region 4.
The four-layer diode of Fig. 3 is an asymmetrical device having a voltage-current characteristic of the form shown in Fig. 4, in which, at a breakover voltage VBO set by the buried N-type region 3 the device switches from a blocking state to a conducting state with a holding voltage VH and a current set by the external circuit, and in which, in the reverse sense, junction breakdown without switching occurs at a voltage VRA.
It is possible to obtain a bi-directional voltagecurrent characteristic, as shown in Fig. 6, by means of a four-layer diode structure such as that shown in Fig. 5.
In the bi-directional four-layer diode shown in Fig. 5, the "forward" part of a four-layer diode characteristic may be provided by the regions 1, 2, 2A, 3 and 4 of the device shown, and the "reverse" part of the characteristic is then provided by the region 1, 2, 2A, 3A and 4A.
The buried N-type regions 2 and 3A may have different doping levels to produce the asymmetrical characteristic of Fig. 6, or the buried N-type regions 3 and 3A may be very similar to produce a symmetrical characteristic in which V901 equals VBO2 A planar bi-directional four-layer diode may take the form shown and Fig. 7 in which an N-type substrate 1 has separate P-type islands 2 and 2A with respective N-type emitter regions 4 and 4A.
Each of the P-type islands 2 and 2A has a buried N-type region 3 and 3A below it, in the N-type substrate 1. The N-type region 1 lies within a Ptype block 5 and a further N-type region 6 is present in the N-type region 1 at its junction with the P-type block 5.
The device shown in Fig. 7 includes one fourlayer diode consisting of the regions 2A(P), 1 (N), 2(P), 4(N) with a buried N-type region 3A, and a second four-layer diode consisting of the regions 2(P), 1(N), 2A(P), 4A(N) with a buried N-type region 3. The first and second four-layer diodes form a bi-directional device.
In addition, in Fig. 7 parallel four layer diodes consisting of the regions 5(P), 1(N), 2A(P), 4A(N) and 5(P), 1(N), 2(P), 4(N), respectively, with a buried N-type region 6, are present.
The region 5 in Fig. 7 may be connected to a reference voltage as a means of limiting the negative voltage excursions at the regions 4 and 4A.
The additional N-type region may be introduced by diffusion before the adjacent P-type region. The N-type diffusion should be of lower impurity concentration than the P-type diffusion so that the P-type diffusion overdopes the N-type diffusion. Ion implantation is one method of introducing dopants to form both the buried Ntype and adjacent P-type region and enables a predetermined avalanche voltage to be obtained with reasonable accuracy.
The buried N-type region may be included in a conventional planar diode to provide a reversevoltage breakdown reference diode. The additional N-type region is also suitable for inclusion in more complex semiconductor structures to provide devices with consistent reverse-breakdown characteristics.
A PNPN device with a buried N-type region as described is suitable for use as a transient suppressor because of its high current surge handling characteristics and predictable behaviour.
An ideal application for PNPN devices with a buried N-type region as described is as a transient suppressor in a solid-state telephone system, since, in such a telephone system, severe transients can occur and failure to suppress them adequately can result in extensive damage to solid-state components. PNPN devices as described above are well suited to transient suppression in modern subscriber line interface circuit (SLIC) in telephone systems.
PNPN devices as described above are, of course also suitable for use in circuits in which it is known to use conventional four-layer trigger diodes, as in, for example, spark generators and fluorescent tube starters represented respectively by Fig. 7 and Fig. 8.

Claims (16)

Claims
1. A semiconductor device including a PN junction between first and second regions in which, in the intended operation of the device, reverse-breakdown of the junction occurs, there being provided, adjacent to the junction and in the first region which is of lower impurity concentration than the second region, a buried region of the same conductivity type as the first region and greater impurity concentration than the first region, so that reverse-breakdown of the junction occurs through the buried region.
2. A semiconductor device as claimed in claim 1, wherein the first region is a substrate region.
3. A semiconductor device as claimed in claim 2, wherein the buried region and the second region are islands in the first region, the impurity concentrations of the buried region and the second region, falling with penetration into the first region, the impurity concentration of the buried region being initially lower than that of the second region and falling at a lower rate than that of the second region.
4. A semiconductor device as claimed in claim 3, wherein the buried region has an initial impurity concentration of 10'7 atoms/cc and the second region has an initial impurity concentration of 10'9 atoms/cc. in a substrate region having an impurity concentration of 10'5 atoms/cc.
5. A semiconductor device as claimed in claim 4, wherein the impurity concentrations of the buried region and the second region fall to that of the first region in about 40 microns and 20 microns, respectively.
6. A semiconductor device as claimed in any one of claims 1 to 5, which is a junction diode having a buried region, as defined at the junction.
7. A semiconductor device as claimed in any one of claims 1 to 5, which includes a four-layer diode (PNPN) device having a buried region, as defined, at the or each junction which, in operation, is reverse biased.
8. A semiconductor device as claimed in any one of claims 1 to 5, which includes a plurality of four-layer diode (PNPN) devices having respective buried regions as defined, at junctions which, in operation, are reverse biased.
9. A semiconductor device as claimed in claim 7 or claim 8, wherein the or each four-layer diode (PNPN) device is bi-directional.
10. A semiconductor device as claimed in any one of claims 1 to 9, wherein the or each junction is a planar junction.
11. A semiconductor device as claimed in any one of claims 1 to 10, wherein the or each buried region is an ion-implanted region.
12. A semiconductor device substantially as herein described with reference to and as illustrated by Fig. 1, or Figs. 1 and 2, or Fig. 3, or Fig. 5, or Fig. 9 of the accompanying drawings.
13. A method of fabricating a semiconductor device which includes a PN junction between first and second regions in which, in the intended operation of the device, reverse-breakdown of the junction occurs, includes the step of providing, in the first region and adjacent to the junction, a buried region of the same conductivity type as the first region and of greater impurity concentration than the first region, so that reverse-breakdown of the junction occurs through the buried region.
14. A method of fabricating a semiconductor device as claimed in claim 13, which includes the step of ion-implanting the buried region and the second region in the first region.
15. A method of fabricating a semiconductor device as claimed in claim 14, which includes the step of so treating the first, second, and buried regions, as to cause diffusion of the ion-implanted regions.
16. A method of fabricating a semiconductor device substantially as herein described with reference to the accompanying drawings.
GB08138575A 1981-12-22 1981-12-22 Reverse-breakdown pn junction devices Expired GB2113907B (en)

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GB2113907B GB2113907B (en) 1986-03-19

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2149205A (en) * 1983-10-31 1985-06-05 Burr Brown Corp Integrated circuit reference diode and fabrication method therefor
EP0217780A2 (en) * 1985-10-04 1987-04-08 General Instrument Corporation Anisotropic rectifier and method for fabricating same
EP0255971A2 (en) * 1986-08-08 1988-02-17 Philips Electronics Uk Limited A semiconductor diode
US4739378A (en) * 1986-02-18 1988-04-19 Sgs Microelettronica S.P.A. Protection of integrated circuits from electric discharge
GB2208257A (en) * 1987-07-16 1989-03-15 Texas Instruments Ltd Overvoltage protector
US4886762A (en) * 1985-08-06 1989-12-12 Motorola Inc. Monolithic temperature compensated voltage-reference diode and method for its manufacture
EP0347778A2 (en) * 1988-06-21 1989-12-27 Siemens Aktiengesellschaft Diode with a modified turn-off capability
US4967256A (en) * 1988-07-08 1990-10-30 Texas Instruments Incorporated Overvoltage protector
EP0520636A2 (en) * 1991-06-25 1992-12-30 Texas Instruments Incorporated Surge protection device and system
WO1993005539A1 (en) * 1991-09-12 1993-03-18 Robert Bosch Gmbh Semiconductor device and a method of manufacturing it
US5285100A (en) * 1988-07-22 1994-02-08 Texas Instruments Incorporated Semiconductor switching device
US5336924A (en) * 1991-12-16 1994-08-09 U.S. Philips Corporation Zener diode having a reference diode and a protective diode
US5516705A (en) * 1993-09-10 1996-05-14 Teccor Electronics Method of forming four layer overvoltage protection device
WO2002082556A1 (en) * 2001-04-07 2002-10-17 Power Innovations Limited Overvoltage protection device
EP1895595A2 (en) 1996-10-18 2008-03-05 Hitachi, Ltd. Semiconductor device and electric power conversion apparatus therewith
JP2008124051A (en) * 2006-11-08 2008-05-29 Shindengen Electric Mfg Co Ltd Thyristor
US7755102B2 (en) 2006-10-03 2010-07-13 Vishay General Semiconductor Llc High breakdown voltage diode and method of forming same

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2149205A (en) * 1983-10-31 1985-06-05 Burr Brown Corp Integrated circuit reference diode and fabrication method therefor
US4886762A (en) * 1985-08-06 1989-12-12 Motorola Inc. Monolithic temperature compensated voltage-reference diode and method for its manufacture
EP0217780A2 (en) * 1985-10-04 1987-04-08 General Instrument Corporation Anisotropic rectifier and method for fabricating same
EP0217780A3 (en) * 1985-10-04 1989-03-29 General Instrument Corporation Anisotropic rectifier and method for fabricating same
US4891685A (en) * 1985-10-04 1990-01-02 General Instrument Corporation Rectifying P-N junction having improved breakdown voltage characteristics and method for fabricating same
US4739378A (en) * 1986-02-18 1988-04-19 Sgs Microelettronica S.P.A. Protection of integrated circuits from electric discharge
EP0255971A2 (en) * 1986-08-08 1988-02-17 Philips Electronics Uk Limited A semiconductor diode
EP0255971A3 (en) * 1986-08-08 1988-07-20 Philips Electronic And Associated Industries Limited A semiconductor diode
GB2208257B (en) * 1987-07-16 1990-11-21 Texas Instruments Ltd Overvoltage protector
GB2208257A (en) * 1987-07-16 1989-03-15 Texas Instruments Ltd Overvoltage protector
EP0347778A3 (en) * 1988-06-21 1991-02-06 Siemens Aktiengesellschaft Diode with a modified turn-off capability
EP0347778A2 (en) * 1988-06-21 1989-12-27 Siemens Aktiengesellschaft Diode with a modified turn-off capability
US4967256A (en) * 1988-07-08 1990-10-30 Texas Instruments Incorporated Overvoltage protector
US5285100A (en) * 1988-07-22 1994-02-08 Texas Instruments Incorporated Semiconductor switching device
EP0520636A2 (en) * 1991-06-25 1992-12-30 Texas Instruments Incorporated Surge protection device and system
EP0520636A3 (en) * 1991-06-25 1993-06-23 Texas Instruments Incorporated Surge protection device and system
US5224008A (en) * 1991-06-25 1993-06-29 Texas Instruments Incorporated Surge protection device and system
WO1993005539A1 (en) * 1991-09-12 1993-03-18 Robert Bosch Gmbh Semiconductor device and a method of manufacturing it
US5336924A (en) * 1991-12-16 1994-08-09 U.S. Philips Corporation Zener diode having a reference diode and a protective diode
US5516705A (en) * 1993-09-10 1996-05-14 Teccor Electronics Method of forming four layer overvoltage protection device
EP1895595A2 (en) 1996-10-18 2008-03-05 Hitachi, Ltd. Semiconductor device and electric power conversion apparatus therewith
EP1895595A3 (en) * 1996-10-18 2008-06-04 Hitachi, Ltd. Semiconductor device and electric power conversion apparatus therewith
WO2002082556A1 (en) * 2001-04-07 2002-10-17 Power Innovations Limited Overvoltage protection device
US7755102B2 (en) 2006-10-03 2010-07-13 Vishay General Semiconductor Llc High breakdown voltage diode and method of forming same
EP2960944A1 (en) 2006-10-03 2015-12-30 Vishay General Semiconductor LLC High breakdown voltage diode and method of forming same
JP2008124051A (en) * 2006-11-08 2008-05-29 Shindengen Electric Mfg Co Ltd Thyristor

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Effective date: 20011221