GB2112187A

GB2112187A - Programmable frequency generator

Info

Publication number: GB2112187A
Application number: GB08138579A
Authority: GB
Inventors: Timothy Alan Roper; Malcolm George Robinson
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1981-12-22
Filing date: 1981-12-22
Publication date: 1983-07-13
Also published as: FR2518847A1; DE3245007A1; JPS58114508A

Abstract

A programmable frequency generator comprising a stable oscillator (14) whose output is supplied to an M stage rate multiplier (16) to which a predetermined program number (N) is applied, the output therefrom is applied to a divider (18) which divides the dividend by a divisor K. The value of the divisor K is such that any jitter in the output of the multiplier (16) can be reduced to an acceptable level. By using a rate multiplier the frequency increment for successive values of N is identical and also the frequency can be changed without any discontinuities in phase so that the generator is suited to producing audio tones in frequency shift keying. For this purpose an S stage waveform simulator (22) can be coupled to the output of the divider (18) thereby enabling small frequency increments to be produced. The programmable frequency generator can comprise binary and/or decimal elements. The programmable frequency generator is applicable to general purpose frequency generators for say test equipment as well as in signalling. <IMAGE>

Description

SPECIFICATION Programmable frequency generator The present invention relates to a programmable frequency generator and to a signal generator incorporating the programmable frequency generator.

It is known to provide a programmable frequency generator in the form of a crystal oscillator and a frequency divider which divides the frequency by a programmed number, N, so that the output frequency fout=fir/N where fin is the oscillator frequency. A disadvantage of such a type of frequency generator is that the frequency increment is determined by the value of N which is usually an integer and in consequence the frequency increments may be somewhat coarse.

Additionally, in the case of wanting to obtain a plurality of frequencies from a single oscillator, then it may be necessary for the oscillator to produce a very high frequency which is the lowest common multiple of the desired frequencies. High frequency oscillators tend to radiate more and be a source of radio interference. Additionally the divider circuit has to comprise a large plurality of stages which consume a lot of power, a factor which is relevant with battery powered equipment, and which also are a source of radio interference. Another disadvantageous feature of using a frequency divider is that if it is decided to change the value of the divisor N, for example in say frequency shift keying, then the change cannot be effected until the frequency divider has completed its particular dividing cycle.

Accordingly it is an object of the present invention to provide a programmable frequency divider which overcomes the disadvantages of the known circuit.

According to the present invention there is provided a programmable frequency generator comprising an oscillator, a programmable rate multiplier coupled to the output of the oscillator, the rate multiplier comprising a plurality of stages and having a program number input whereby the output frequency from the rate multiplier is determined in response to the applied program number, and a divider coupled to the output of the rate multiplier for dividing the output frequency therefrom.

The main advantages of the programmable frequency generator in accordance with the present invention over using a high frequency oscillator and a plurality of dividers are that a plurality of frequencies can be derived from a lower frequency oscillator merely by changing the program number applied to the rate multiplier, thus the likelihood of radio interference is reduced. By coupling a divider to the output of the rate multiplier the jitter effect of the rate multiplier whose output pulses are not spaced at equal intervals of time is reduced to an acceptable level so that the output frequency has the stability of the oscillator, for example a crystal oscillator.

Further, the rate multiplier which may comprise a binary or decimal rate multiplier enables the oscillator frequency to be effected substantially instantaneously by changing the program number, there being no need to wait for a cycle of division to be completed.

According to another aspect of the present invention there is provided a signal generator comprising a programmable frequency generator in accordance with the present invention and a waveform simulator connected to the output of the divider.

The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a block schematic circuit diagram of a signal generator incorporating a programmable frequency generator made in accordance with the present invention, and Figure 2 is a schematic circuit diagram of a signal generator incorporating a programmable frequency generator which is adapted to produce one of four audio frequency tones at any one time Referring to Figure 1, the blocks to the left of the vertical broken line 10 represent a programmable frequency generator 12 made in accordance with the present invention and the blocks to the right of the broken line 10 represent those circuit elements which utilise the output of the generator 12 to produce a simulated waveform, for example a sinewave.The generator 12 comprises a stable frequency oscillator 14 such as a crystal oscillator. An output of the oscillator 14 is coupled to a binary rate multiplier (BRM) 16 having M stages. The BRM 16 has an input 17 for a program number N for example a binary number applied in parallel. An outupt of the BRM 16 is coupled to a divider 18 having a fixed divisor. In the illustrated embodiment the dividier 18 is a binary divider in which the divisor K is 2P where P is the number of stages.

In the operation of the generator 12 the signal from the oscillator 14 has a stable frequency fin and this signal is applied to the BRM 16. The signal fout at the output of the BRM 1 6 consists of a train of pulses which are not all equally spaced relative to each other, there being N output pulses for each group of 2M pulses applied from the oscillator 14. Consequently the output frequency fout from the BRM 16 can be expressed conveniently as fout=(N/2M)fin. Since 2M is fixed then the output frequency can be changed in steps of (1/2M)fin and hence each step is therefore an identical frequency increment. Further there are a total of 2M-1 different output frequencies available, all of which are an exact multiple of the frequency increment.It follows therefore that by a suitable selection of fin and the number M of stages in the BRM 16, the circuit can be used to provide a selection of frequencies over any desired range with any desired increment.

There are two characteristics of a BRM which are relevant to the application of this invention to, for example, a signalling system or a piece of test equipment such as a signal generator and these are firstly that the BRM responds substantially instantaneously to a change in the program number N and secondly the output frequency will be accurately the program fraction of the input frequency and will be as stable as the input frequency. However within each group of N pulses out of every 2M pulses applied from the oscillator the output pulses are not evenly distributed in time, there being larger gaps between successive pulses in certain cases. If such a signal is applied to a waveform simulator then these uneven intervals produce an undesirable "jitter" in the waveform being simulated.

The jitter is reduced to an acceptable level using the divider 18 so that fout is divided by K, where K may be typically 25 (i.e. by 32). Because of this extra division step, then the output frequency fout from the BRM 16 must be K times higher than would be the case if one was not using a divider to reduce the jitter. The actual value of K has to be selected having regard to the desired oscillator frequency, the step in frequency for successive values of N, the maximum output frequency, and the amount of jitter in the amount from the BRM 16.

Referring to the blocks to the right of the broken line 16 in Figure 1 which represent a waveform genarator 20, the generator 20 comprises a waveform simulator 22 which may comprise what is known as a Johnson counter having weighted resistors connected to its outputs to simulate the desired waveform, for example a sinewave, from the pulses from the divider 18. Typically a sinewave is simulated from 10 pulses which in effect means that the pulse repetition frequency from the divider 18 is divided by S, the division ratio in the counter. In consequence the frequency increment of the simulated waveform can be made quite small as will be illustrated by the following example which assumes that M=8(2M=256), K=32(=2P where P=5) and S=10 and f,n=1.2288 MHz.

The minimum frequency fm,n, which also corresponds to the frequency increment, will be when the program number N=1, thus: 111 fmin=1 228800x-x-x-=1 5 Hz.

256 32 10 Also it can be shown that the maximum frequency fmax (when N=255) is 255 1 1 fmax=1 228800x x-x-=3825 Hz.

256 32 10 As there will be some harmonics in the output of the simulator 22 these are removed using a low pass filter 24.

Since the values of M, K and S are fixed then by varying the program number N substantially instantaneous frequency changes can be effected to the signal at the output of the simulator 22 without there being a noticeable deformation in the waveform being produced.

Referring now to Figure 2 in which the various parts corresponding to the blocks shown in Figure 1 have been identified by the same reference numbers.

The illustrated circuit is intended to provide one of four audio frequency sinewaves at any one time, the particular frequency being produced in response to associated values of program number N applied to the BRM 1 6. By way of example the frequencies are a keying signal at 2970 Hz (N=1 98), high and low frequency shift keying (FSK) signals of 2505 Hz (N=1 67) and 2295 Hz (N=1 53) and an FSK mid-frequency signal of 2400 Hz (N=1 60).

The oscillator 14 is a well-known crystal oscillator circuit based on a transistor type MPS 918 and having a crystal of 1.2288 MHz. The output of the oscillator is applied to a pulse shaping circuit 30 in the form of a Schmitt trigger circuit such as an integrated circuit type CD 4093B. An output of the circuit 30 is applied to a clock input of the BRM 16 which in the illustrated embodiment is formed by two cascaded, 4 stage devices sold by the Radio Corporation of America under the type number CD 4089B, the details of which devices can be determined from the manufacturer's published data sheets. The program numbers are applied to the various inputs of the BRM 16 via an addressing circuit 32 and various OR-gates, as shown.

The output from the BRM 16 is applied to the clock input of the divider 18 which comprises in this example a binary divider type CD 4024B. As the value of P is 5 then the input to divider 22 is taken from the Q5 output of the divider 18. A tone disable signal is applied via a terminal 58 to the reset input of the divider 18 and to a pin of the integrated circuit forming a part of the sinewave simulator 22.

The sinewave simulator 22 is based on a presettable divider/counter sold by the Radio Corporation of America under type number CD 401 8B. The outputs Q1 to Q4 are resistively weighted by resistors 40, 42, 44, 46, 48 and 50 of values 26.1 KQ, 100 KQ, 90.9 KQ, 90.9 KQ, 26.1 KQ and 100 KQ, respectively, these values being chosen to minimise the harmonic content of the output waveform. Output Q5 is fed back to define the count length, in this case 10. The simulated sinewave is low pass filtered in a two stage filter 24 implemented by operational amplifiers Motorola type MC 1458.

The values of the components used in the oscillator 14, the simulator 22 and the low pass filter 24 have the values shown. The pin numbers of certain of the integrated circuits have also been referenced.

Although the illustrated circuit has been described with reference to binary devices it is to be understood that the circuit could be implemented using a decimal rate multiplier and decimal dividers and counters or a combination of binary or decimal devices.

Obviously different values of oscillator frequency and divisors M, K and S could be used to get the desired frequency increments and wave shapes. If it is desired to prdouce two or more outputs simultaneously as may be necessary when using test equipment then the oscillator 14 may be common but the remainder of the illustrated circuit would have to be repeated for each simultaneous output desired. In such a case the output oscillator signal to the other circuit(s) is derived from the terminal 60 in Figure 2.

Claims

1. A programmable frequency generator comprising an oscillator, a programmable rate multiplier coupled to the output of the oscillator, the rate multiplier comprising a plurality of stages and having a program number input whereby the output frequency from the rate multiplier is determined in response to the applied program number, and a divider coupled to the output of the rate multipler for dividing the output frequency therefrom.

2. A generator as claimed in Claim 1, wherein the divider has a fixed divider.

3. A generator as claimed in Claim 1 or 2, wherein the programmable rate multiplier is a binary rate multiplier.

4. A generator as claimed in Claim 1 or 2, wherein the programmable rate multiplier is a decimal rate multiplier.

5. A programmable frequency generator substantially as hereinbefore described with reference to the accompanying drawings.

6. A signal generator comprising the programmable frequency generator as claimed in any one of the preceding claims, and a waveform simulator connected to the output of the divider.

7. A signal generator as claimed in Claim 6, in which the waveform simulator is adapted to simulate a sinewave.

8. A signal generator as claimed in Claim 6, substantially as hereinbefore described with reference to the accompanying drawings.