JPS61265918A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS61265918A
JPS61265918A JP10687685A JP10687685A JPS61265918A JP S61265918 A JPS61265918 A JP S61265918A JP 10687685 A JP10687685 A JP 10687685A JP 10687685 A JP10687685 A JP 10687685A JP S61265918 A JPS61265918 A JP S61265918A
Authority
JP
Japan
Prior art keywords
circuit
frequency
signal
output
logical output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10687685A
Other languages
Japanese (ja)
Inventor
Takehiko Hoshino
星野 武彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP10687685A priority Critical patent/JPS61265918A/en
Publication of JPS61265918A publication Critical patent/JPS61265918A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007Fail-safe circuits

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To simplify the circuit constitution while attaining contactless configuration and fail safe by deciding whether or not the frequency of output signal of a multiplier circuit is a prescribed frequency and generating a logical output based on the decided result. CONSTITUTION:An output is given from a decision circuit 18 with the input condition of logical output '1' and logical output '1' is obtained. No output is supplied from the decision circuit 18 with the input condition corresponding to logical output '0' or circuit fault and logical output '0' is outputted. That is, the frequency f1 of the signal inputted from a frequency division circuit 12 is multiplied by a ratio L being a constant write signal fW inputted to a multiplier circuit 17 to a multiple rate signal fR, a signal having the multiplied frequency f1 is outputted from the multiplication circuit 17 is outputted and compared with a prescribed frequency f0 at the circuit 18. When the relation of f1=f0 exists, the logical output of the circuit 18 goes to '1', a relay 19 is excited and when f1not equal to f0, the logical output goes to '0' and the relay 19 is not excited.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明はリレーを用いない無接点式の論理回路に関する
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a non-contact logic circuit that does not use relays.

(従来の技術〉 多数の入力情報を得てその組み合わせにより負荷を制御
する場合に、論理回路により入力情報群の条件に応じた
論理値を出力して負荷を制御するのが一般的である。
(Prior Art) When a large amount of input information is obtained and a load is controlled by combining the input information, it is common to control the load by outputting a logical value according to the conditions of a group of input information using a logic circuit.

例えば新交通システムではゴムタイヤの車両を用いるた
めに列車検知に従来からある軌道回路方式を採用できな
い。従って、かかる新交通システムの場合、従来では多
数のリレーを用いて列車検知用の論理回路を構成して列
車位置情報に基づいてこれらリレ一群を動作させ列車の
存在又は不在を検知するようにしている。
For example, new transportation systems use rubber-tired vehicles, so conventional track circuit methods cannot be used for train detection. Therefore, in the case of such a new transportation system, conventionally, a logic circuit for train detection is constructed using a large number of relays, and a group of these relays is operated based on train position information to detect the presence or absence of a train. There is.

かかる列車検知方式の一例を第2図及び第3図に示す。An example of such a train detection method is shown in FIGS. 2 and 3.

図において、1は列車で、その前頭部から信号r、と後
頭部から信号f2を発振する。IT、3T、5T・・・
は列車軌道の各区間毎に設けられた誘導ループである。
In the figure, reference numeral 1 indicates a train, which oscillates a signal r from its front head and a signal f2 from its back head. IT, 3T, 5T...
is the induction loop provided for each section of the train track.

2は照査信号rcnを発信する信号源、3は誘導ルー1
3Tを介して照査信号rc11を受信するf、1.受信
器、4,5はそれぞれ信号f、、f、を誘導ループ3T
を介してそれぞれ受信するf、受信器、f2受信器であ
る。FCHR,F+R,FzRは、それぞれ各受信器3
〜5からの信号により動作するリレーでリレーF t 
R。
2 is a signal source that transmits the reference signal rcn, 3 is a guidance route 1
f, which receives the reference signal rc11 via 3T; 1. Receivers 4 and 5 each send signals f, ,f, through induction loops 3T
f, receiver, and f2 receiver, respectively. FCHR, F+R, FzR are each receiver 3
Relay F t is a relay operated by a signal from ~5.
R.

F、Rは列車1が誘導ループ3Tの領域に進入してルー
プ3Tを介して信号f 、、f2が受信されると励磁さ
れ、またリレーFcHRは常時は照査信号fCMにより
励磁されるが、列車1の進入により信号f、又はf2が
誘導ループ3Tを介して受信されると照査信号fcHが
抑圧されて無励磁となる。尚、各受信器3〜5及び各リ
レーFCNR,FtR,FzRは図示しないが、各誘導
ループ毎に設けられている。そして、各区間での列車検
知は、前述のように動作する各リレーFc、R,FAR
,FzRの各接点を用いて、第2図に示すような論理回
路を構成し、各区間における列車1の存在又は不在の条
件により各接点を開閉させて、列車検知リレーの励磁又
は無励磁条件を成立させて各区間での列車の存在又は不
在を検知するようにしている。尚、第2図は誘導ルー1
3Tの領域についての列車検知用論理回路を示しており
、3TFzr、3TF+r、3TFc、、rは誘導ルー
13Tに接続する各リレーFCHR,F+R,FtRの
接点、5TFzrは誘導ループ5Tに接続するリレーF
、Rの接点、I T F Irは誘導ループITに接続
するリレーFIRの接点である。また、3TRは誘導ル
ープ3Tの領域における列車検知リレーを示し、3Tr
は前記リレー3TRの接点である。更に、17r。
F and R are energized when train 1 enters the area of induction loop 3T and signals f,, f2 are received via loop 3T, and relay FcHR is normally energized by reference signal fCM, but When signal f or f2 is received via the induction loop 3T due to the entry of signal fcH, the reference signal fcH is suppressed and becomes non-excited. Note that although the receivers 3 to 5 and the relays FCNR, FtR, and FzR are not shown, they are provided for each induction loop. Train detection in each section is carried out by each relay Fc, R, FAR operating as described above.
, FzR are used to configure a logic circuit as shown in Figure 2, and each contact is opened or closed depending on the presence or absence of train 1 in each section, and the train detection relay is energized or de-energized. is established to detect the presence or absence of a train in each section. Furthermore, Figure 2 shows guidance route 1.
3TFzr, 3TF+r, 3TFc, , r are the contacts of the relays FCHR, F+R, FtR connected to the induction loop 13T, and 5TFzr is the relay F connected to the induction loop 5T.
, R contacts, I T F Ir are the contacts of the relay FIR which connects to the inductive loop IT. In addition, 3TR indicates a train detection relay in the area of the induction loop 3T, and 3TR
is a contact point of the relay 3TR. Furthermore, 17r.

5Trはそれぞれ誘導ループIT、5Tの領域における
列車検知リレーの接点を示す。Bは電源のプラス側を示
し、Cは接地例を示す。
5Tr indicates the contact point of the train detection relay in the area of the induction loop IT and 5T, respectively. B indicates the positive side of the power supply, and C indicates a grounding example.

〈発明が解決しようとする問題点〉 ところが、従来のようにリレーを用いて論理回路を構成
するのでは、入力情報の数が多くなるに従ってリレーの
数も増え回路構成が極めて複数になると共に耐久性にも
問題がある。これを解消するには、TTL等による無接
点式の論理回路を使用すればよいが、この場合には、高
度の安全性が要求される鉄道信号において最も重要であ
るフェイルセーフ性を確保できないという問題がある。
<Problems to be solved by the invention> However, when configuring a logic circuit using relays as in the past, as the number of input information increases, the number of relays increases, resulting in extremely multiple circuit configurations, and the durability is poor. There are also problems with sexuality. To solve this problem, it would be possible to use a non-contact type logic circuit such as TTL, but in this case, fail-safe performance, which is most important for railway signals that require a high degree of safety, cannot be ensured. There's a problem.

そこで、本発明は上記の実情に鑑みてなされたもので、
無接点式で回路構成も簡単で、しかもフェイルセーフな
論理回路を提供することを目的とする。
Therefore, the present invention was made in view of the above-mentioned circumstances.
The purpose is to provide a fail-safe logic circuit that is non-contact type and has a simple circuit configuration.

く問題点を解決するための手段〉 このため本発明では、入力情報に対応する分周率を記憶
するROMと、lROMの出力する分周率により入力信
号を分周する分周回路と、該分周回路の出力信号の周波
数を逓倍して出力する逓倍回路と、前記ROMの人力情
報と同一の情報が入力し当該入力情報に応じて前記逓倍
回路の逓倍率信号を出力する逓倍率信号形成回路と、逓
倍回路の出力信号の周波数が所定周波数か否かを判定し
この判定結果に基づいた論理出力を発する判定回路とで
構成するようにした。
Means for Solving the Problems> For this reason, the present invention includes a ROM that stores a frequency division ratio corresponding to input information, a frequency division circuit that divides an input signal according to the frequency division ratio output from the ROM, and A multiplier circuit that multiplies and outputs the frequency of the output signal of the frequency divider circuit, and a multiplier signal generator that receives the same information as the manual information of the ROM and outputs a multiplier signal of the multiplier circuit in accordance with the input information. The present invention includes a circuit and a determination circuit that determines whether the frequency of the output signal of the multiplier circuit is a predetermined frequency or not and generates a logical output based on the determination result.

く作用) これにより、論理出力が“1”となる入力条件のときに
は、分周回路の出力信号周波数を逓倍率信号形成回路の
逓倍率信号で逓倍したときに所定周波数となり、判定回
路から出力が発せられ論理出力“1”が得られる。また
、論理出力″0”に相当する入力条件のとき及び回路故
障時には、逓倍したときの逓倍回路からの出力信号が所
定周波数以外の周波数となり判定回路からは出力がなく
論理出力“0”が出力される。
As a result, when the input condition is such that the logic output is "1", when the output signal frequency of the frequency divider circuit is multiplied by the multiplication rate signal of the multiplication rate signal forming circuit, the predetermined frequency is reached, and the output from the determination circuit is A logic output of "1" is obtained. In addition, when the input condition corresponds to the logic output "0" or in the event of a circuit failure, the output signal from the multiplier circuit when multiplied becomes a frequency other than the predetermined frequency, and there is no output from the judgment circuit, and a logic output "0" is output. be done.

〈実施例) 以下本発明の一実施例を第1図に基づいて詳細に説明す
る。
<Example> An example of the present invention will be described in detail below with reference to FIG.

第1図において、11は人力情報に応じた分周率を記憶
するROM、12は信号源13から入力する信号の周波
数を前記ROMLLから出力された分周率で分周して出
力する分周回路である。14は前記ROM11と同一の
入力情報が入力し、この入力情報に応じた逓倍率信号を
出力する逓倍率信号形成回路である。かかる逓倍率信号
形成回路14は具体的にはROM15と分周回路16と
からなり、前記ROM15には入力情報に応じた分周率
が記憶されており、分周回路16は、前述の分周回路1
2と同一の入力信号をROM15の出力する分周率で分
周して出力し、かかる出力が逓倍率信号として出力され
る。
In FIG. 1, 11 is a ROM that stores a frequency division ratio according to human input information, and 12 is a frequency divider that divides the frequency of the signal input from the signal source 13 by the frequency division ratio output from the ROMLL and outputs the frequency. It is a circuit. 14 is a multiplication rate signal forming circuit which receives the same input information as the ROM 11 and outputs a multiplication rate signal according to this input information. The multiplication rate signal forming circuit 14 specifically includes a ROM 15 and a frequency division circuit 16. The ROM 15 stores a frequency division rate according to input information, and the frequency division circuit 16 is configured to perform the aforementioned frequency division. circuit 1
2 is frequency-divided by the frequency division ratio output from the ROM 15 and outputted, and this output is output as a multiplication ratio signal.

17は、分周回路12からの出力信号の周波数を逓倍率
信号形成回路14の逓倍率信号に基づいて逓倍する逓倍
回路である。
17 is a multiplier circuit that multiplies the frequency of the output signal from the frequency divider circuit 12 based on a multiplier signal from the multiplier signal forming circuit 14.

この逓倍回路17は特開昭58−143605号公報に
開示されているものと同様の構成であり、入力信号を書
き込み信号によりRAMに書き込み、次にRAMに記憶
された入力信号を読み出し信号によって読出すようにし
、この際に、書き込み信号と読み出し信号の周期の比だ
け入力信号が逓倍されるようになっている。
This multiplier circuit 17 has a configuration similar to that disclosed in Japanese Patent Laid-Open No. 58-143605, in which an input signal is written into the RAM using a write signal, and then the input signal stored in the RAM is read using a read signal. At this time, the input signal is multiplied by the ratio of the periods of the write signal and the read signal.

18は逓倍回路17の出力信号の周波数が予め設定した
所定周波数か否かを判定し、その判定結果に基づいた論
理出力を発する判定回路であり、具体的には例えば所定
周波数の信号のみ通過させるフィルタと、シュミットト
リガ回路で構成され、逓倍回路18の出力信号が所定周
波数のときだけシュミットトリガ回路がトリガされて論
理出力“1”が出力される。19は判定回路18の出力
に基づいて駆動制御される負荷としての例えば列車検知
リレーである。
Reference numeral 18 denotes a determination circuit that determines whether the frequency of the output signal of the multiplier circuit 17 is a predetermined frequency set in advance or not, and issues a logical output based on the determination result. Specifically, for example, only a signal of a predetermined frequency is passed through. It is composed of a filter and a Schmitt trigger circuit, and only when the output signal of the multiplier circuit 18 has a predetermined frequency, the Schmitt trigger circuit is triggered and a logic output of "1" is output. Reference numeral 19 designates, for example, a train detection relay as a load whose drive is controlled based on the output of the determination circuit 18.

次に動作を説明する。Next, the operation will be explained.

入力情報、例えば第2図の各接点の開閉条件に相当する
情報をROMIIに与えると、これら情報に対応する分
周率Nが検索され分周回路に出力される。すると、分周
回路12に入力する信号の周波数f、を前記分周率Nで
分周した周波数f、(=f。
When input information, for example, information corresponding to the opening/closing conditions of each contact shown in FIG. 2, is given to the ROMII, the frequency division ratio N corresponding to this information is retrieved and output to the frequency division circuit. Then, the frequency f of the signal input to the frequency dividing circuit 12 is divided by the frequency division ratio N, (=f.

/N)が分周回路12から逓倍回路17に入力される。/N) is input from the frequency divider circuit 12 to the multiplier circuit 17.

また、これと同時に逓倍率信号形成回路14のROM1
5にも同一内容の入力情報が与えられ、これに応じて分
周率Mが決定される。そして、分周回路16から逓倍率
信号、即ち周波数f*(=fs/M)の信号が逓倍回路
17に入力される。
At the same time, ROM1 of the multiplication rate signal forming circuit 14
5 is also given the same input information, and the frequency division ratio M is determined accordingly. Then, a multiplication factor signal, that is, a signal of frequency f* (=fs/M) is input from the frequency dividing circuit 16 to the multiplication circuit 17.

一方、逓倍回路17には一定の書き込み信号f1が人力
されており、この書き込み信号f8と逓倍率信号fll
の比L (= f */ f w)だけ分周回路12か
ら入力する信号の周波数f、は逓倍され、逓倍回路17
からこの逓倍された周波数f L(= f tX L)
の信号が出力され、判定回路18で所定周波数f0と比
較される。そして、fL=f、であれば判定回路18の
論理出力が“1”となり、リレー19が励磁されf、≠
f0であれば“0”の論理出力となってリレー19は励
磁されない。
On the other hand, a constant write signal f1 is manually input to the multiplier circuit 17, and this write signal f8 and the multiplication rate signal fll
The frequency f of the signal input from the frequency dividing circuit 12 is multiplied by the ratio L (= f * / f w), and the frequency f of the signal input from the frequency dividing circuit 12 is multiplied by
This multiplied frequency f L (= f tX L)
A signal is output and compared with a predetermined frequency f0 in the determination circuit 18. Then, if fL=f, the logic output of the determination circuit 18 becomes "1", and the relay 19 is energized so that f, ≠
If it is f0, the logic output is "0" and the relay 19 is not excited.

即ち、リレー19を励磁する条件が入力したときのみ、
f、とfRに基づく逓倍回路17の出力信号周波数f、
がf、=f、となるようにf、とflの関係を設定する
ことにより、リレー19を励磁する。
That is, only when the condition for exciting the relay 19 is input,
The output signal frequency f of the multiplier circuit 17 based on f, and fR,
The relay 19 is excited by setting the relationship between f and fl so that f,=f.

また、リレー19を励磁しない条件が入力したときには
、f、≠foとなるようにfiとfRの関係を設定する
ことにより、リレー19は励磁されない。更に、ROM
II、15が故障すればf、とfRの関係においてfL
=f0が成立せず論理出力は0”となるので、フェイル
セーフにできる。
Furthermore, when a condition for not energizing the relay 19 is input, the relay 19 is not energized by setting the relationship between fi and fR so that f,≠fo. Furthermore, ROM
If II, 15 fails, then fL in the relationship between fR and fR.
Since =f0 does not hold and the logical output becomes 0'', it can be made fail-safe.

このようにすれば、リレーで構成する論理回路に比べて
回路構成は極めて簡潔となり、無接点なので耐久性も半
永久的なものにできる。しかも、故障時には出力が“O
”となりフェイルセーフであるから安全対策上極めて有
効である。
In this way, the circuit configuration is extremely simple compared to a logic circuit composed of relays, and since there is no contact, the durability can be made semi-permanent. Moreover, in the event of a failure, the output will be “O”.
”As it is fail-safe, it is extremely effective in terms of safety measures.

〈発明の効果〉 以上述べたように本発明によれば、論理回路の無接点化
を達成でき、しかもフェイルセーフに構成できるので、
回路構成が格段に簡素化できると共に、耐久性及び安全
性を大幅に向上できるという効果を有する。
<Effects of the Invention> As described above, according to the present invention, a logic circuit can be made contactless and can be configured in a fail-safe manner.
This has the effect that the circuit configuration can be significantly simplified, and durability and safety can be significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック構成図、第2
図は従来のリレー使用論理回路の適用例を示す図、第3
図は同上リレー論理回路の回路図を示す。 11・・・ROM   12・・・分周回路  13・
・・信号源14・・・逓倍率信号形成回路  17・・
・逓倍回路18・・・判定回路
FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
Figure 3 shows an example of application of a conventional logic circuit using relays.
The figure shows a circuit diagram of the same relay logic circuit. 11... ROM 12... Frequency divider circuit 13.
... Signal source 14 ... Multiplication rate signal forming circuit 17 ...
・Multiplier circuit 18...judgment circuit

Claims (1)

【特許請求の範囲】[Claims] 入力情報に対応する分周率を記憶するROMと、該RO
Mの出力する分周率により入力信号を分周する分周回路
と、該分周回路の出力信号の周波数を逓倍して出力する
逓倍回路と、前記ROMの入力情報と同一の情報が入力
し当該入力情報に応じて前記逓倍回路の逓倍率信号を出
力する逓倍率信号形成回路と、逓倍回路の出力信号の周
波数が所定周波数か否かを判定しこの判定結果に基づい
た論理出力を発する判定回路とで構成したことを特徴と
する論理回路。
A ROM that stores a frequency division ratio corresponding to input information, and the RO
A frequency divider circuit that divides the input signal according to the frequency division ratio output by M, a multiplier circuit that multiplies and outputs the frequency of the output signal of the frequency divider circuit, and the same information as the input information of the ROM is input. A multiplication factor signal forming circuit that outputs a multiplication factor signal of the multiplier circuit in accordance with the input information, and a determination device that determines whether the frequency of the output signal of the multiplier circuit is a predetermined frequency or not and generates a logical output based on this determination result. A logic circuit characterized by comprising a circuit.
JP10687685A 1985-05-21 1985-05-21 Logic circuit Pending JPS61265918A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10687685A JPS61265918A (en) 1985-05-21 1985-05-21 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10687685A JPS61265918A (en) 1985-05-21 1985-05-21 Logic circuit

Publications (1)

Publication Number Publication Date
JPS61265918A true JPS61265918A (en) 1986-11-25

Family

ID=14444728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10687685A Pending JPS61265918A (en) 1985-05-21 1985-05-21 Logic circuit

Country Status (1)

Country Link
JP (1) JPS61265918A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114508A (en) * 1981-12-22 1983-07-07 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Programmable frequency generator
JPS5928725A (en) * 1982-08-09 1984-02-15 Hitachi Ltd Logical system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114508A (en) * 1981-12-22 1983-07-07 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Programmable frequency generator
JPS5928725A (en) * 1982-08-09 1984-02-15 Hitachi Ltd Logical system

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