GB2111334A - An FM radio receiver incorporating a muting circuit - Google Patents

Abstract

In an FM radio receiver (Figs. 8 and 10) incorporating a muting circuit 10, the output signal of a detuning detector circuit (4) is applied to the input terminals of first and second mute control circuits (11, 12) which control the muting operations of a pre- amplifier (7) for amplifying a stereo composite signal and the muting circuit (10) connected to the output of a stereo demodulation circuit respectively. Discrimination levels these first and second mute control circuits are set to mutually different levels so that when the receiver becomes in a detuned state the signal transmission of the muting circuit is inhibited and thereafter the signal transmission of the pre-amplifier (7) is inhibited. This eliminates popping noise at the time of changes from tuning to detuning and vice versa. In examples of the muting circuit (Figs. 5 and 7) signal transmission is effected when a first constant current source (Q5), connected to the emitters of (Q1, Q2) is operative and a second constant current source (Q6) connected to the emitters of (Q3, Q4) is operative. No signal transmission is effected in the opposite case. To eliminate the popping noise when the power source is switched on, a switching element (Q7) is connected in parallel to a bias resistor (RB) and is kept in the ON state for a predetermined period of time after switching on the power source. <IMAGE>

Description

SPECIFICATION An FM radio receiver incorporating a muting circuit The present invention relates to an FM radio receiver incorporating a muting circuit.

A known muting circuit providing a large signal attenuation has been previously disclosed by us in an electronic switching circuit which makes use of a differential transistor circuit such as the one shown in Figure 1 of the accompanying drawings.

In this circuit, the collector electrodes of differential amplification transistors Qt and Q2 for signal transmission are connected in common to respective collector electrodes of differential transistors Q3 and 04 for forming a D.C. signal at the time of muting operation. Constant current transistors Os, Q8are connected to common emitter electrodes of the respective pairs of differential transistors Qi, Q2 and Q3, Q4. The constant current transistors 05, ops are selectively and alternately operated by a switch SW,.

An input signal is applied to the base electrode of the differential transistor Q,. A bias voltage Ve1 is applied to the base electrode of transistor Q, via a bias resistor R r and also directly to the base electrode of the differential transistor Q3. A negative feedback signal is applied to the base electrodes of the transistors Q2 and Q4 via a feedback circuit P, in order to set the gain of the differential amplification transistor circuit and also to provide a D.C. bias voltage.

This circuit operates as follows: when the switch SW, is set to position a, the constant current transistor Q5 becomes non-conductive whilst the constant current transistor Q6 becomes conductive so that the differential amplification transistors Q, and Q2 are turned off whilst the differential transistors Q3 and Q4 are turned on.

Consequently, only the same D.C. signal as the bias voltage Vei, that is formed by the differential transistors Q3 and Q4, can be obtained from the output OUT.

On the other hand, when the switch SW, is set to the position b, the differential amplification transistors Q, and Q2 become conductive and transmit the input signal IN. Accordingly, a large signal attenuation can be obained without changing the D.C. output signal.

We have found that in this muting circuit when the input signal IN is applied via a coupling capacitor C, the foilowing problem occurs.

It is to be assumed that the inputterminal IN in Figure 1 is substantially earthed through the practically negligible impedance of a signal source (not shown), so that the bias voltage Vei rises instantly at the time t1, immediately after the power is connected as shown in Figure 2 of the accompanying drawings, whereas the voltage V,,, at the junction beween the coupling capacitor C, and the bias resistor RBT rises gradually due to the time constant of the capacitor C, and the resistor RB.

Accordingly, if the switch SW1 is set to the position a during a predetermined period from the time t, to the time t2, the base voltage of both differential amplification transistors Q3 and Q4 is equal to the bias voltage Vei and consequently, the collector potential of the transistor Q4 becomes VB1/ Since an output coupling capacitor CO connected to the output terminal OUT and the impedance of a load (not shown) from a differential circuit together, the waveform obtained by differentiating the collector potential Vei/ of the transistor Q4 occurs at the output terminal OUT at the time t1, as shown in the waveform diagram of Figure 2.This transient response waveform occurring at the time t, eventually results in a popping noise, but can be prevented by arranging a muting circuit (not shown) at a subsequent stage in this circuit.

When the switch SW, is switched from position a to position b at the time t2, the base electrode of the transistor Os is biased by the bias voltage VB1 whereas the base electrode of the transistor 0, is biased by the voltage VB1 which is lower than the bias voltage Vai Consequently since a voltage difference AV as shown in the waveform diagram of Figure 2 is applied between the base electrodes of the differential amplification transistors Q, and 02, the collector potential of the transistor Q2 drastically drops at the time t2.The waveform obtained by differentiating this collector potential by the output coupling capacitor CO and the impedance of the load occurs at the output terminal OUT at the time t2 as shown in the waveform diagram of Figure 2.

We have found that prevention of the popping noise at the time t2 can be accomplished by reducing the time constant at the rise of the voltage VB11 to an extremely small value.

Accordingly, we have examined the idea of reducing the capacitance of the coupling capacitor C1, but this idea was abandoned because a problem of phase inversion of low frequency signals arises.

Reducing the resistance of the bias resistor Re was also attempted, but this idea was also abandoned because of the lowering of the input impedance at the input terminal IN.

Occurrence of the popping noise due two the transient response waveform at the time t2 can be prevented by arranging another muting circuit (not shown) at a subsequent stage of this circuit, but when the capacitance of the coupling capacitor and the resistance of the bias resistor Re are set to about 1 OMF and about 40Kohms, respectively, the muting time of the muting circuit arranged at the subsequent stage of this circuit must be set to about three seconds. However, if the muting operation is carried out for such a relatively long period after turning on the power source, the listener might think that the radio receiver was out of order.

On the other hand, as one of the additional functions of an FM radio receiver, a muting circuit for eliminating offensive noise between stations during selection of the stations has previously been known, such as that disclosed in "Hl-FI FM Tuner", p. 193-199, published on August 20, 1 976 by Nippon Hoso Kyokai.

FM radio receivers employing this muting circuit in a monolithic semiconductor integrated circuit for FM intermediate frequency amplification and detection are commercially available from both RCA and Hitachi Ltd.

Figure 3 of the accompanying drawings shows a block diagram of an FM radio receiver including the monolithic semiconductor integrated circuit.

This radio receiver was examined by us prior to the filing of this patent application.

The FM radio receiver shown in Figure 3 includes a monolithic semiconductor integrated circuit IC, to FM intermediate frequency amplification and detection. This integrated circuit IC, includes an FM intermediate frequency amplification stage 1, an FM detection stage 2, a low frequency amplification stage 3, a detuning detection circuit 4, and a mute control circuit 6 for controlling the muting operation at the low frequency amplification stage 3. Additionaliy, this monolithic semiconductor integrated circuit includes an AFC circuit and a level detection circuit, the output signals of which are used as the input signals to the detuning detection circuit 4. A time constant circuit 5 is provided for removing high frequency components contained in the detuning detection signal.

The FM radio receiver also includes a monolithic semiconductor integrated circuit IC2 for FM stereo demodulation. This integrated circuit IC2 includes a pre-amplifier 7, a PLL (phase locked loop) circuit 8 for forming a 38KHz switching signal synchronous with a 1 9KHz pilot signal contained in a stereo composite signal, and a stereo demodulation circuit 9. The stereo composite signal formed by the FM detection circuit 2 is applied to the input of the pre-amplifier 7 via a coupling capacitor C100 whilst the stereo demodulation circuit 9 forms stereo demodulated signals L, R of the left and right channels by receiving at its input the stereo composite signal passing through the pre-amplifier 7 and the 38KHz switching signal formed by the PLL circuit 8.

The monolithic semiconductor integrated circuit IC2 also includes additional circuits for stereo-monaural detection, selection and display.

In the monolithic semiconductor integrated circuit IC,, the popping noise VpOp originates from the FM detection stage 2 due to changes in the D.C. voltage in the S characteristic curve of the FM detection circuit 2 as shown in Figure 4 of the accompanying drawings during the muting operation for changing over from tuning to detuning upon detection of detuning.

Accordingly, we have examined the possibility of providing a muting circuit 10 at the output of the stereo demodulation circuit 9 as the subsequent stage. In such a case, the muting circuit 10 must exhibit fast mute-release timing for shifting from detuning to tuning and retarded mute timing for shifting from tuning to detuning in its muting operation in the monolithic semiconductor integrated circuit IC,. Since these muting operations are independentiy controlled, the timings are difficult to set and are highly susceptible to variance of element characteristics.

Moreover, the coupling capacitor C100 which is positioned between the two muting circuits 6 and 10, causes a time advance of the signal to the subsequent muting circuit, so that it becomes extremely difficult for the subsequent muting circuit 10 to eliminate the popping noise generated in the preceding muting circuit 6.

It is an object of the present invention to provide an FM radio receiver incorporating a muting circuit which is capable of reliably eliminating the popping noise.

present invention there is provided a muting circuit including: (a) first and second transistors having their emitter electrodes connected to each other; (b) third and fourth transistors having their emitter electrodes connected to each other; (c) a first constant current source connected to the emitter electrodes of said first and second transistors; (d) a second constant current source connected to the emitter electrodes of said third and fourth transistors; (e) a coupling capacitor for feeding an input signal to the base electrode of said first transistor; (f) a bias resistor having one end thereof connected to the base electrode of said first transistor and the other end connected to the base electrode of said third transistor; (g) bias voltage generation means connected to the base electrode of said third transistor and to said other end of said bias resistor;; (h) load means connected to the collector electrode of said second transistor and to the collector electrode of said fourth transistor; (i) a feedback circuit connected between said load means and the base electrodes of said second and According to the present invention there is provided an FM radio receiver including: : (a) an FM intermediate frequency amplification stage; (b) an FM detector having its input terminal connected to the output terminal of said FM intermediate frequency amplification stage; (c) a detuning detection circuit responsive to the intermediate frequency signal of said FM intermediate frequency amplification stage; (d) a pre-amplifier having its input terminal connected to the output terminal of said FM detector, the signal transmitting operation of said pre-amplifier being virtually inhibited when a control input signal is applied to the control input terminal of said pre-amplifier; (e) a phase locked loop circuit for obtaining a switching signal in synchronism with a pilot signal contained in a stereo composite signal obtained from said FM detector;; (f) a stereo demodulation circuit for providing right-hand and left-hand channel demodulation output signals when applied with said stereo composite signal and said switching signal; (g) a muting circuit having first and second input terminals, first and second output terminals and a control input terminal, said first and second input terminals receiving said right-hand and lefthand channel demodulation output signals, respectively, and said control input terminal receiving the control input signal, thereby virtually inhibiting the signal transmitting operation between said first input terminal and said first output terminal and the signal transmitting operation between said second input terminal and said second output terminal, respectively;; (h) a first mute control circuit receiving at its input terminal the output signal of said detuning detection circuit and applying the output signal thereof to said control input terminal of said preamplifier, said first mute control circuit further having a first discrimination level with respect to the output signal of said detuning detection signal to be applied to the input terminal thereof; and (i) a second mute control circuit receiving at its input terminal the output signal of said detuning detection circuit and applying the output signal thereof to the control input terminal of said muting circuit, said second mute control circuit further having a second discrimination level with respect to the output signal of said detuning detection circuit to be applied to the input terminal thereof; whereby a level difference is set between said first discrimination level and said second discrimination level so that when the reception condition of said FM radio receiver changes from the tuning state to the detuning state, the signal transmitting operation of said muting circuit is virtually inhibited and thereafter the signal transmitting operation of said pre-amplifier is virtually inhibited.

The present invention will now be described in greater detain by way of example with reference to the remaining figures of the accompanying drawings, wherein: Figure 5 is a circuit diagram of a preferred form of muting circuit; Figure 6 is a waveform diagram to explain the operation of the muting circuit shown in Figure 5; Figure 7 is a detailed circuit diagram of the preferred form of muting circuit; Figure 8 is a block diagram of an FM radio receiver incorporating a muting circuit; Figure 9 is a waveform diagram to explain the operation of the FM receiver shown in Figure 8; and Figure 10 is a detailed circuit diagram showing the second part of the FM radio receiver shown in Figure 8.

Referring first to the muting circuit shown in Figure 5, the collector electrodes of differential amplification transistors Q1 and Q2 for signal transmission are connected in common to respective collector electrodes of differential transistors Q3 and Q4 for forming the D.C. signal at the time of the muting operation. Constant current transistors Q5 and Q6 are alternately operated by a switch SW, and are connected to the common emitter electrodes of the respective pairs of differential transistors 01,O2and Q3,Q4.

The bias voltage Vex is applied to the base electrode of the differential amplification transistor Q1' to which the input signal IN is also applied via the bias resistor RB' whilst the bias voltage Vie1 is directly applied to the base electrode of the differential transistor Q3. A negative feedback signal is applied to the base electrodes of the transistors Q2 and 04 via a feedback circuit , in order to set the gain of the differential amplification transistor circuit and provide the D.C. bias voltage.

A load resistor RL is connected to the collector electrodes of the transistors Q2a and Q4 and also to the output terminal OUT. An input signal IN is applied to the base electrode of the transistor Q1 via a coupling capacitor C,.

A switching transistor 07 is arranged in parallel to the bias resistor RB in order to prevent occurrence of the popping noise at the time of mute release after turning on the power source, and is controlled by a voltage V applied via a switch SW2. The switch SW2 is placed into position a', when the power source is applied, thereby turning on the transistor 07. The transistor 07 is kept ON until the switch SW, is changed over to position b or before the release of the muting operation, and is turned off after the release of the muting operation. It is therefore preferred that both switches SW1 and 8W2 be operated in an interlocking arrangement by the same control signal.

The muting operation by the switch SW, when the power source in this circuit is turned on is the same as in the circuit shown in Figure 1, and so its explanation is omitted. The bias resistor RB is short-circuited by the transistor Q7 which is rendered conductive by the switch SW2 immediately after the power source is turned on.

Therefore, as shown in the waveform diagram of Figure 6, the base voltage Vie1' of the differential amplification transistor Q1 substantially follows the bias voltage Vei, which quickly rises immediately the power source is turned on at the time t1. Accordingly, when the switch SW1 is changed over to position b at the time t2 to release the muting operation, the bias voltage Ve1 and the voltage VBl' become equal to each other so that the popping noise does not occur.

Incidentally, the voltage fluctuation occurring at the time t1 immediately after turning on the power source (or the popping noise) can be eliminated by the muting circuit of the subsequent stage which also functions to protect the speaker connected to a power amplifier that is simultaneously turned on. However, when the popping noise occurs at the time t2, the muting operation of the muting circuit at the subsequent stage has already released so that the amplification circuit at the subsequent stage is operative and the voltage fluctuation is amplified as a loud popping noise.

Referring now to the second preferred form shown in Figure 7, the muting circuit includes circuit elements that are formed on a single chip silicon substrate in accordance with a well known semiconductor manufacturing technique.

However, a capacitor C1, a resistor R20 and a capacitor C3 connected via terminals P, and P2 are formed by external components. The muting circuit of this embodiment also functions as a preamplifier for a stereo demodulation circuit in an FM stereo tuner.

Accordingly, the differential amplification transistor circuit for signal transmission consists of transistors Q1, Q1', and Q2, 0; connected in Dariington configuration in order to realize a high input impedance and also to increase the open loop gain. The emitter electrodes of the transistors Q1' and 02, on the input side are provided with constant current source circuits formed by transistors Q" and Qr2 and resistors RB and R7 respectively. The emitter electrodes of the transistors Q1 and Q2 are coupled via emitter resistors R, and R2.A resistor R3 is located between the junction of these resistors and the collector electrode of the constant current transistor Q5.

A resistor R4 is likewise located between the collector electrode of the constant current transistor Q6 and the emitter electrodes of the differential transistors Q3 and Q4 which are connected to each other.

A current mirror circuit is arranged at the collector electrodes of the amplification transistors Q1 and Q2 as a load, and consists of transistors Qa and Og.

This amplified output is applied to an emitter follower output circuit consisting of a transistor Q10 and a resistor R5.

An output signal is obtained from an output terminal OUT and is fed back to the base electrodes of the transistors Q4 and Q2'. A capacitor C2 for preventing oscillation is connected to the base electrode of the emitter follower transistor Q10, the capacitor being an MOS (metal oxide semiconductor) capacitor.

A resistor RB' for preventing electrostatic breakdown is connected to the base electrode of the input amplification transistor Q1'.

When the power source is turned on, an integration voltage from the RC circuit R20, C3 connected to the terminal P2 is applied to the base electrode of a transistor Q13 via a resistor R1l. Level shift diodes Q14 and Q15 (the term "diode" will hereinafter include diode connected transistors) and a resistor R13 are connected in series with the emitter electrode of the transistor Q13. The voltage drop across the resistor R13 is applied to the base electrode of the transistor Q16 via a resistor R12. Resistor R10 is arranged between the collector electrode of this transistor Q16 and a voltage source Vcc2 which is higher than the bias voltage V51.The collector voltage of the transistor Ql6is applied to the base electrode of the transistor Q7 as its controlling signal.

Accordingly, the transistor Q16 and the resistor R10 together form the switch SW2.

The voltage drop across the resistor R13 is applied to the base electrode of the transistor Q1" and a diode Q18 is connected between the emitter electrode of this transistor Q17 and earth to act as a constant voltage source. Further, a resistor R14 is located between the collector electrode of the transistor Q1, and a stabilized voltage source Vcc1.

A voltage from the stabilized voltage source Vccr which has been level-shifted by level shift diodes Q2. Q22 and a resistor R15 is applied to the base electrode of a transistor Oso whilst the collector voltage of the transitor 17 is applied to the base electrode of a transistor Q19 through a resistor R15.

The emitter electrodes of these transistors Q19 and Q20 are connected to each other and to the stabilized voltage source Vcci through a resistor Ris.

These transistors 0,, and Oso are p-n-p transistors whose collector electrodes are connected to earth through resistors R17 and R18, respectively. The collector voltages of these transistors Q19 and Oso are applied as the controlling signals to the base electrodes of the constant current transistors Q5 and Q6 through resistors R5 and Rg respectively. Accordingly, these circuit elements form the switch SW1.

The operation of these switches 8W1 and 8W2 is as follows.

During the period from immediately after the power source is turned on until its integrated voltage at the terminal P2 reaches 4VBE (base emitter voltage of the transistor or forward voltage of the diode), the transistor is is held non-conductive so that the base voltage of the transistor Q7 is as high as the voltage source Vcc2, and hence the transistor 07 is turned on.

When the voltage exceeds the above mentioned voltage 4V BE, the transistor Q16 is turned on so that the transistor 07 is turned off.

On the other hand, since the transistor Q17;S held non-conductive during the period before the abovementioned integration voltage reaches 5VBE the differential transistor Q19 is held nonconductive whilst the differential transistor Oso is held conductive. Accordingly, the constant current transistor We is operative whilst the constant current transistor 05 is inoperative, thereby performing the same operation as when the switch 8W1 is set to the position a. Thus, the muting operation is carried out.

When the voltage at the terminal P2 exceeds 5V55, the transistor Q17;S turned on so that the differential transistor Q19 is turned on with the differential transistor Oso being turned off.

Consequently, the constant current transistor Qe is operative whilst the constant current transistor We is inoperative, thereby performing the same operation as when the switch 8W1 is set to the position b. Hence, muting is released and signal transmission is started.

Accordingly, the circuit operates so that the switching transistor Q7 is turned off before the muting operation is released.

It should be noted that it is possible to employ a construction in which the constant current transistors Q5 and Q6 are alternatively turned off when the switching transistors are turned on.

As the switching means for short-circuiting the base bias resistor RB' a MOSFET can be employed in a modified form of the circuit.

Figure 8 is a block diagram showing the principal portions of a preferred form of an FM radio receiver which incorporates the above described muting circuit.

The FM radio receiver includes an FM intermediate frequency amplification-detection monolithic semiconductor integrated circuit IC,' which includes an FM intermediate frequency amplification stage 1, an FM detection stage 2, a low frequency amplification stage 3 and a detuning detection circuit 4 and in which the mute control circuit is deleted in the low frequency amplification stage 3. Except in that the mute control circuit is omitted, this integrated circuit is the same as the above referred to monolithic semiconductor integrated circuit IC1 for FM intermediate frequency amplification and detection as shown in Figure 3. However, the above described monolithic semiconductor integrated circuit IC1 for FM intermediate frequency amplification and detection can be used in this embodiment by rendering its mute control circuit 6 inoperative.

The FM radio receiver also includes a monolithic semiconductor integrated circuit IC; for FM stereo demodulation. Except those features which will hereinafter be described, this circuit is analogous to the above described monolithic semiconductor integrated circuit IC2 such as one disclosed in the magazine "Eiectronics", pages 62-66, November, 1971 or to the "HA1 196" circuit available commercially from us.

In the monolithic semiconductor integrated circuit IC2, for FM stereo demodulation in this embodiment, the muting function is added to the pre-amplifier 7. A first mute control circuit 11 for controlling this muting function as well as a second mute control circuit 12 for controlling the muting circuit 10 are provided in the stereo demodulation output. A detection signal formed by the detuning detection circuit 4 is applied to both these mute control circuits 11 and 12, and different detection levels V,1, V,2 are provided to discriminate the necessary mute control.

As shown in Figure 9, the discrimination level V,1 of the first mute control circuit 11 is set to the high level whilst the discrimination level V,2 of the second mute control circuit 1 2 is set to the low level so as to read the level difference from a detuning detection signal VM of the detuning detection circuit 4, which reaches the high level when the tuning frequency deviates excessively from the centre frequency f0 of the S characteristic of the FM detection stage 2 and reaches the low level when tuning is established.

Accordingly, when detuning changes to tuning and the muting operation is released, the detuning detection signal VM reaches a level below the first discrimination level V Li so that the muting operation in the pre-amplifier 7 is released before the muting operation of the muting circuit 10 is released. In this instance, the voltage fluctuation VpOp occurs due to the change in the D.C. voltage in the S characteristic but since the muting operation in the muting circuit 10 is not yet released, the occurrence of the popping noise is eliminated.

On the other hand, when tuning changes to detuning and the muting operation starts, the detuning detection signal VM first reaches a level above the second discrimination level V,2 so that muting of the pre-amplifier 7 is started after the muting operation of the muting circuit 10.

Accordirigly, the popping noise occurring for the reason noted above is eliminated by muting circuit 10 which has already started its muting operation.

Since the mute control circuits 11 and 12 are formed in the same monolithic semiconductor integrated circuit IC2, the discrimination levels V,1 and V,2 for restricting their mute control operation are not affected by variance of the semiconductor elements, and consequently the mute control operation can be set to a high level of accuracy as described above.

Since no circuit element for shortening the signal transmission time such as a coupling capacitor C100 is positioned between the muting circuit in the pre-amplifier 7 and the muting circuit 10 for the stereo demodulation circuit 9, it is possible to make the timing difference for the start and release of muting operation, corresponding to the level difference of the discrimination levels V,1 and V,2, coincide with the time difference for the elimination of the popping noise.

In other words, the popping noise can be reliably eliminated by a simple circuit design in which the level difference between V,1 and V,2 is set in accordance with the pulse width of the popping noise.

Incidentally, sufficient attenuation to eliminate noises between broadcasting stations cannot be obtained by use of only the muting circuit 10.

Hence, it is necessary to arrange two muting circuits as described above.

Referring to the detailed circuit diagram shown in Figure 10, the circuit elements of the portion IC2, encircled by dotted lines are formed on one silicon semicoductor chip by a known semiconductor manufacturing technique, and numerals in circles represent terminal numbers.

In the pre-amplifier 7, differential amplification transistors Q1, Q2 and Q3, Q4 for the signal transmission of the input signal IN from the low frequency amplification stage 3 are connected to each other in Darlington configuration with their collector electrodes respectively connected together, whilst the collector electrodes of differential transistors Q10 and Q11 for forming the D.C. signal at the time of the muting operation are connected to the collector electrodes of the Darlington pairs Q1Q2 and Q3Q4 respectively.

Constant current circuits consisting of transistors Q6 and 0, and resistors RB and R5, respectively, are connected to the emitter electrodes of the input transistors Q1 and Q3 respectively. A constant bias voltage V52 is applied to the base electrodes of these transistors Q6 and Q,. The emitter electrodes of the transistors Q2 and Q4 are connected to each other via emitter resistors R1 and R2 respectively.A resistor R3 is located between the junction of these resistors and the collector electrode of the constant current transistor Os. A resistor R4 is likewise located between the emitter electrodes of the differential transistors Q,O and Q11 and the collector electrode of the constant current transistor Q12 A current mirror circuit consisting of transistors Q8 and Q9 is connected as a load to the mutually connected collector electrodes of the differential amplification transistors 01,02and Q3, Q4 and to the mutually connected collector electrodes of the differential transistors Q10 and Q11.

This amplification output is applied to an emitter follower output circuit consisting of a transistor Q13 and a resistor R9. A negative feedback signal is obtained from the output of the emitter follower output circuit to be fed back to the base electrodes of the transistors Q3 and Q11 and an output signal (composite signal VCON) to be applied to a stereo demodulation circuit 9 which will be described in greater detaii hereinafter.The composite signal is produced as an output from a second terminal via an inverting amplifier circuit consisting of a transistor Q14- a collector resistor R10 and an emitter resistor R1l, and via an emitter follower circuit consisting of a transistor Q,5 and an emitter resistor R,2.

A capacitor C1 for preventing oscillation is connected to the base electrode of the transistor Q13 and in a preferred form this capacitor is composed of an MOS (metal oxide semiconductor) capacitor.

The base bias voltage V51 is applied to the base electrode of the input differential amplification transistor Q1 via a base bias resistor R, and resistor R8 and is applied directly to the base electrode of the differential transistor 010.

The base electrode of the transistor Q1 is connected to the first terminal via the resistor R5 which is provided in order to prevent dielectric breakdown. A composite input signal IN (in the case of the stereo broadcasting) is applied to this first terminal as an FM detection output signal through a coupling capacitor C100. A bias circuit 1 3a constitutes the bias voltages Vei and VB2.

In the pre-amplifier 7, either one of the constant current transistors Q5 and Q12 is alternatively rendered conductive in order to carry out the signal transmission of the input signal IN or the muting operation.

When the constant current transistor Q5 is conductive and the constant current transistor Q12 non-conductive, the differential transistors Q10 and Q11 are turned off whilst the differential amplification transistors Q2 and Q4 are rendered conductive so that the input signal IN is transmitted. In the opposite case, the differential amplification transistors Q2 and Q4 are turned off with the differential transistors Q10 and Q11 being conductive so that the signal transmission of the input signal IN is inhibited and muting is carried out.In this case, only the same D.C. signal as the bias voltage V51 is obtained at the emitter output of the transistor Q13 due to the operation of the differential transistors Q10 and Q11.

A transistor Q16 for short-circuiting the bias resistor R7 is arranged across both ends of this resistor in order to prevent occurrence of the popping noise when the power source is turned on.

Emitter electrodes of differential transistors Q35 and Q36 are connected to a stabilized voltage sourceVcc3 through a resistor R34, and resistors R32 and R33 are connected between the collector electrodes of these transistors and earth respectively.The transistors Q35 and Q36 together form a switching circuit for alternatively actuating either one of the constant current transistors Q5 and Q12 A voltage (VCC32VBE) generated by level shift diodes Q37 and Q38 (the term "diode" will hereinafter include transistors of the diode type) and a resistor R35 is applied to the base electrode of the transistor Q36 A diode 034 is connected to the emitter electrode of the transistor Q33 as a constant voltage element and a resistor R30 is connected to its collector electrode.A control voltage is applied to the base electrode of this transistor Q33, whose collector voltage is in turn applied to the base electrode of the transistor Q35 through a resistor R31. Accordingly, when the transistor Q33 is held conductive, the transistor 035 is turned on whilst the transistor Q36 is turned off so that the constant current transistor 05 is rendered conductive to transmit the input signal IN to the pre-amplifier 7. On the other hand, when the transistor Q33 is held non-conductive, the transistor Q35 is turned off whilst the transistor 035 is turned on so that the constant current transistor 012 is rendered conductive to carry out the muting operation in the pre-amplifier 7.

A resistor R45 is located between a voltage source Vcc2, which is higher than the bias voltage source V51, and the collector electrode of a transistor 032' and a control signal similar to the abovementioned control signal is applied to the base electrode of the transistor Q32, the collector voltage of which is in turn applied to the base electrode of a switching transistor Q16 An integration voltage of the voltage source Vcc due to an integration circuit R103 and C107 formed by external components at the eighth terminal is applied to the base electrode of a transistor Q23 through a resistor R21, and level shift diodes Q24 and Q25 and a resistor R22 are connected in series between the emitter electrode of this transistor Q23 and earth. The voltage drop across the resistor R22 generates the abovementioned control signal that is to be applied to the base electrode of the transistor Q32 The terminal voltage of this resistor R22 is applied to the base electrode of transistor Q32 through a resistor R29 and to the base electrode of transistor Q33 through a resistor R23, respectively.

The integrated voltage from this eighth terminal when the power source is turned on is utilized for eliminating the popping noise when the power source is turned on.

On the other hand, a detuning detection signal VM generated by the detuning detection circuit 4 is converted into D.C. by an RC time constant circuit consisting of resistors R104 and R105 and a capacitor C105, and is then applied to the seventh terminal. This detuning detection signal is applied to the base electrode of a transistor Q26 which is provided with a diode Q27 to act as a constant voltage element being connected between the emitter electrode of the transistor Q26 and earth.

The collector electrode of the transistor Q2 is connected to the base electrode of the transistor Q33 Accordingly, the circuit including this transistor Q26 forms the first mute control circuit 11.

The detuning detection signal is applied to the second mute control circuit 12 via a resistor R24 and the base and emitter electrodes of transistors Q28 and Q29.

The second mute control circuit 12 employs: a Schmidt circuit consisting of a reference voltage circuit formed by differential transistors 03g and Q40 provided with a resistor R38 at their common emitter electrodes, a resistor R41, a transistor Q45 connected in diode configuration a diode 046, and voltage dividing resistors R39 and R40 arranged between the collector and emitter electrodes of the transistor Q45 for generating a reference voltage to be applied to the base electrode of the transistors Oso A current feedback circuit formed as a current mirror circuit is interposed between the collector and the base electrodes of the other transistor Q39 and is composed of transistors Q43 and Q44 and emitter resistors R35 and R37. This Schmidt circuit has hysteresis with respect to an applied voltage which turns it on and an applied voltage which turns it off.Diodes Q41 and Q42 for performing the voltage clamp are connected to the base electrode of the transistor Q39 and the detuning detection signal obtained from the emitter electrode of the transistor Q2 is applied, via a resistor R27, to an inverter circuit consisting of a transistor Q30 and a resistor R50. A transistor Q31' which is controlled by the collector output of the transistor Q30, is connected to the base electrode of the transistor 03.

The output signal from the pre-amplifier 7 generated at the second terminal via the dielectric breakdown prevention resistor R13 is applied to a PLL circuit 8 from the third terminal via a capacitor C10l. In the PLL circuit a 38KHz switching signal for stereo demodulation in synchronism with 19 KHz pilot signal is formed, and is applied to the stereo demodulation circuit 9.

The stereo demodulation circuit 9 is composed of a known switching type stereo demodulation circuit. This stereo modulation circuit 9 consists of transistors 017 to Q22 forming a balanceddifferential type multiplication circuit and resistors R15 to R20. The stereo demodulation circuit 9 of this switching type has been disclosed in the periodical "IEE Transactions on Broadcast and Television Receivers", Volume BTR-14, Number 3, pp. 58 to 73, October 1968, and a semiconductor integrated circuit for an FM stereo demodulation circuit using the PLL circuit has been disclosed in "Electronics" above referred to.

A bias circuit 1 3b is provided for generating a bias voltage V53.

The output of this stereo demodulation circuit 9 passes through post-amplifiers 1 4L, 1 4R so that the left-hand channel output is obtained from the fourth terminal and the right-hand channel output is obtained from the fifth terminal.

Lowpass filters 1 5L, 1 5R are also connected to the fourth and fifth terminals, respectively. Pairs of capacitors C103, C104 and C105, C105 are connected in series and are also connected to the fourth and fifth terminals, respectively. Transistors Q100 and are are located between the respective junctions of these series capacitors and earth. These capacitors and transistors together form the muting circuit 10.

The base electrodes of these transistors Q100 and Q101 are connected to the sixth terminal through resistors R1ol and R102, respectively.

The collector voltage of transistor Q36 which permits the muting operation in the pre-amplifier 7, is applied to the base electrode of transistor Q43 through a resistor R44 and transistor Q51 generates a mute control output signal. Diodes Q49 and Oso connected to the collector electrode of the transistor Q4B apply an operating voltage to this transistor Q51 A resistor R45 is located between the series diodes Q49 and Oso and the collector electrode of the transistor Q4BT and a resistor R45 is connected in parallel with the series diodes Q49 and 050.

The feedback output current of the above referred to Schmidt circuit is also applied to the base electrode of the output transistor Q47 and a mute control output signal to the sixth terminal is generated via a resistor R49 from the commonly connected collector electrodes of the output transistors Qs1 and Q47.

The above described circuit operates as follows.

First, when the power source is turned on, transistor Or2 is held non-conductive and transistor 0,, is held conductive until the integration voltage to the eighth terminal reaches 4 VBE (base-to-emitter voltage of the transistor or forward voltage of the diode). Accordingly, in response to the rising bias voltage which is following the voltage source Vccl, the coupling capacitor C100 charges and the bias voltage of the transistor Q1 rises rapidly so that the bias voltage of the transistors Q3 and Q11 generated by the feedback also rises rapidly.

On the other hand, during the period until the above-mentioned integration voltage reaches 5 VBEI the transistors Q33 and Q35 are held non- conductive so that the constarit current transistor 05 is turned off whilst the constant current transistor 012 is turned on. When the transistor 035 is turned on, the transistors 045 and Q51 are also turned on. Accordingly, the transistors Q1OO and Q101 of the muting circuit 10 are turned on and carry out the muting operation in the preamplifier 7 and in the muting circuit 10.

Before the integration voltage reaches 5V,,, the transistor Os2 is turned on and hence the transistor is is turned off. When the integration voltage reaches 5VBE the transistors Q33 and Q35 are turned on whilst the transistors Q4B and Q5, are turned off so that the muting operation ceases in the pre-amplifier circuit 7 and in the muting circuit 10.

Since during the rise of the bias voltage of the transistor Q, no delay is caused by the time constant determined by the capacitor C100 and the resistor R7 no difference is generated between the bias voltage Ve1 and the bias voltage formed by the feedback operation. Consequently, the popping noise can be prevented.

On the other hand, when tuning to a desired station, the integration voltage at the eighth terminal is fully charged to the power source voltage Vcc, so at the time of detuning the voltage at the seventh terminal is at the high level and transistor Os6 is turned on. Accordingly, the transistor 033 is turned off, whereby the muting operation is carried out in the pre-amplifier 7 and in the muting circuit 10. In'this case, since the eighth terminal is at the high level, the transistor Q32 is turned on and the switching transistor Q16 which is connected to the bias resistor R7 is turned off.

Since the seventh terminal is at the high level due to the detuning detection signal, the transistor Q39 forming the Schmidt circuit is turned on and the muting circuit 10 is also made to perform the muting operation by this mute control circuit 12.

When the detuning detection signal VM drops below 2VBE upon tuning, the transistor Q2 is turned off and the transistor 03 is turned on so that the muting operation in the pre-amplifier 7 ceases. In this case, due to the S characteristic of the FM detection output, the voltage fluctuation occurs but is removed by the continued muting performed by the muting circuit 10.

When the detuning detection signal VM drops further below V55, the transistor Oso is turned off and thereby turns on the transistor Osi so that the differential transistor 039 is turned off, and the action of the muting circuit 1 0 ceases at this time.

When the detuning is again effected and the rise voltage of its detection signal VM reaches Vee, the transistor Or0 is turned on, turning off the transistor Ops1. In this case, however, a voltage higher than VeE, e.g. about 1 .SVes, is applied to the base electrode of the transistor Q40 by the transistors Q45 and Q46 and the resistors R39 and R40, and consequently the transistor 039,is kept off and the muting circuit 10 does not operate as yet.

When the detuning detection signal VM reaches the reference voltage (1 .SVBE), the transistor 03 is turned on, and muting is effected in the muting circuit 10.

In this manner, the mute control circuit 12 has a hysteresis characteristic which has its discrimination levels at VBE and 1 .5vie Next, when the detuning detection signal reaches 2vex, transistor 25 is turned on in order to actuate transistor Q33 and begin muting in the pre-amplifier 7. In this case, too, due to the S characteristic in the FM detection output, the voltage fluctuation occurs but is eliminated because the muting circuit 10 has already started operating.

The hysteresis characteristic is provided by use of the Schmidt circuit because, as can be clearly understood from the operation waveform diagram shown in Figure 9, no problem occurs even if the difference of timing between the start of the muting operation in the pre-amplifier 7 and the start of the muting operation in the muting circuit 10 at the beginning of the muting operation is made smaller than the difference of timing at the release of the muting operation. In other words, since the differential waveform in the D.C. voltage fluctuation of the S characteristic is produced as the popping noise, it is necessary for the timing difference to correspond to the pulse width of this popping noise in order to stop the muting operation silently, and the timing of muting circuit 10 should be slightly advanced at the start of the muting operation.Additionally, the hysteresis characteristic is an extremely effective means for compensating for unstability of the detuning detection signal.

It should be understood that the monolithic semiconductor integrated circuit IC2, forming the FM stereo demodulation circuit can be provided with additional circuits such as a circuit for FM stereo-monaural detection, selection and display, and a circuit for cancelling the 19KHz pilot signal. Any signal can be used as the detuning detection signal so long as it is capable of discriminating between tuning and detuning, and the polarity of its signal level may become simultaneously high levels. In this case, the discrimination level may be set to the reverse level difference.

Attention is drawn to our copending Application No. 81.26544 in which there is claimed in Claim 1 a muting circuit including: (a) first and second transistors having their emitter electrodes connected to each other; (b) third and fourth transistors having their emitter electrodes connected to each other; (c) a first constant current source connected to the emitter electrodes of said first and second transistors; (d) a second constant current source connected to the emitter electrodes of said third and fourth transistors; (e) a coupling capacitor for feeding an input signal to the base electrode of said first transistor; (f) a bias resistor having one end thereof connected to the base electrode of said first transistor and the other end connected to the base electrode of said third transistor; ; (g) bias voltage generation means connected to the base electrode of said third transistor and to said other end of said bias resistor; (h) load means connected to the collector electrode of said second transistor and to the collector electrode of said fourth transistor; (i) a feedback circuit connected between said load means and the base electrodes of said second and fourth transistors; 0) means for alternatively controlling and bringing either one of said first and second constant current sources into the operative state and the other into the inoperative state; and (k) a switching element connected between said one end and said other end of said bias resistor and actuated into the ON state for a predetermined period after the switching on of the power source.

Claims (5)

Claims

1. An FM radio receiver including: (a) an FM intermediate frequency amplification stage; (b) an FM detector having its input terminal connected to the output terminal of said FM intermediate frequency amplification stage; (c) a detuning detection circuit responsive to the intermediate frequency signal of said FM intermediate frequency amplification stage; (d) a pre-amplifier having its input terminal connected to the output terminal of said FM detector, the signal transmitting operation of said pre-amplifier being virtually inhibited when a control input signal is applied to the control input terminal of said pre-amplifier; (e) a phase locked loop circuit for obtaining a switching signal in synchronism with a pilot signal contained in a stereo composite signal obtained from said FM detector;; (f) a stereo demodulation circuit for providing right-hand and left-hand channel demodulation output signals when applied with said stereo composite signal and said switching signal; (g) a muting circuit having first and second input terminals, first and second output terminals and a control input terminal, said first and second input terminals receiving said right-hand and lefthand channel demodulation output signals, respectively, and said control input terminal receiving the control input signal, thereby virtually inhibiting the signal transmitting operation between said first input terminal and said first output terminal and the signal transmitting operation between said second input terminal and said second output terminal respectively;; (h) a first mute control circuit receiving at its input terminal the output signal of said detuning detection circuit and applying the output signal thereof to said control input terminal of said preamplifier, said first mute control circuit further having a first discrimination level with respect to the output signal of said detuning detection signal to be applied to the input terminal thereof; and (i) a second mute control circuit receiving at its input terminal the output signal of said detuning detection circuit and applying the output signal thereof to the control input terminal of said muting circuit, said second mute control circuit further having a second discrimination level with respect to the output signal of said detuning detection circuit to be applied to the input terminal thereof: whereby a level difference is set between said first discrimination level and said second discrimination level so that when the reception condition of said FM radio receiver changes from the tuning state to the detuning state, the signal transmitting operation of said muting circuit is virtually inhibited and thereafter the signal transmitting operation of said pre-amplifier is virtually inhibited.

2. An FM radio receiver according to Claim 1, wherein there is provided a detection circuit for detecting the switching on of the power source, and the signal transmitting operation of said preamplifier and that of said muting circuit are virtually inhibited on the basis of the output signal of said detection circuit for detecting the switching on of the power source.

3. An FM radio receiver according to Claim 1 or 2, wherein said second discrimination level of said second mute control circuit is determined by the hysteresis of a Schmidt circuit, and a level difference is provided between the start level of virtual inhibition of the signal transmitting operation of said Schmidt circuit and the release level of virtual inhibition of the signal transmitting operation of said muting circuit.

4. An FM radio receiver according to Claim 1 or 2, wherein the pre-amplifier, the phase locked loop circuit, the stereo demodulation circuit, the first mute control circuit and the second mute control circuit are formed within one monolithic semiconductor integrated circuit.

5. An FM radio receiver constructed and arranged to operate substantially as herein described with reference to and as illustrated in Figures 8 and 10 of the accompanying drawings.