GB2110031A - Loop filter for phase locked loop - Google Patents

Abstract

A loop filter for a phase locked loop includes an A/D converter having an input (20) to which the analogue error signal is applied which is connected to a first input of an amplitude comparator 22. A reference source (23) which produces a uniformly distributed random amplitude reference signal is connected to the second input of the comparator (22) which as a consequence produces a stocastic sequence of pulses in which the number of logic '1' pulses depends on the amplitude of the error signal. These pulses are fed to an accumulator (28) which accumulates the pulses over a given period defined by pulses generated in the timing generator (37) and applied to input (43) of the accumulator (28). The accumulated total is stored in a latch (49) and applied to the input (30) of a digital filter 31. The filter enables the use of a digital filter (31) while simplifying the analogue to digital converter to a comparator (22), an accumulator (28) and a reference source (23) all of which can be conveniently integrated. <IMAGE>

Description

SPECIFICATION Loop filter for phase locked loop The invention relates to a loop filter for a phase locked loop comprising a phase comparator, a voltage controlled oscillator and a loop filter.

The major diffulty in producing a phase locked loop as an intergrated circuit is the implementation of the loop filter. Although the filter is normally comparatively simple it often has a very low cut-off frequency leading to the requirement for large values of capacitance.

The capacitance values even when reduced as far as possible by means of increasing the resistor values and using a capacitance multiplier are still relatively large for integration.

One possible solution is to replace the analogue loop filter by a digital filter. The difficulty here, however, lies in the integration of the analogue-digital interfaces and in particular in the integration of the input analogue to digital converter.

It is an object of the invention to provide a phase locked loop which is easier to implement as an integrated circuit than those described in the preceding paragraph.

The invention provides a loop filter for a phase locked loop as described in the opening paragraph charcterised in that the loop filter comprises a reference source for producing a uniformly distributed random amplitude reference signal, means for comapring the amplitude of the reference signal with that of the output of the phase comparator at regular intervals and producing a signal having first or second logic status depending on the results of the comparison, means for accumulating the results of the comparison over a predetermined plurality of said intervals, means for applying the accumulated signal to the input of a digital filter, and means for feeding the output signal from the digital filter to the input of a digital to analogue converter, the output of the digital to analogue converter being the output of the loop filter.

In a phase locked loop the rate at which the phase changes is normally low compared with the rate at which phase is measured. For example, if the maximum difference between the frequency of the input signal and that of the voltage controlled oscillator is 1% when the loop is out of lock then the maximum frequency of the phase variation is 1% of the input signal frequency. Usually the bandwidth of the loop filter is an even smaller fraction of the input signal frequency. The invention is based on the representation of the analogue output from the phase detector by stochastic sequences rather than by a deterministic series of binary numbers. The continuously varying phase comparator output is represented by a stream of binary digits which change randomly in time, at regular intervals.The stream of binary digits has the property that the probability of a binary 1 occurring is proportional to the amplitude of the output of the phase comparator. If the long term average of the sequence is obtained it will be equal to the value of the input variable. Thus the stochastic sequence may be considered as consisting of an average level with added noise. Since the loop filter will normally have a low pass characteristic the noise will be filtered out leaving substantially only the wanted average level.

The phase locked loop of the invention enables the use of a digital filter while simplifying the analogue to digital converter to a comparator an accumulator and a reference source all of which can be conveniently integrated.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows in block schematic form a known phase locked loop arrangement, Figure 2 shows in block schematic form a loop filter for a phase locked loop according to the invention, Figure 3 shows timing waveforms for the loop filter shown in Fig. 2, and Figure 4 shows the attenuation/frequency characteristic of the loop filter shown in Fig.

2.

Figure 1 shows in block schematic form a typical known phase locked loop arrangement which comprises an input terminal 1 which is connected to a first input 2 of a phase comparator 3 having an output 4 which is connected to an input 5 of a loop filter 6. The output 7 of the filter 6 is connected to a control input 8 of a voltage controlled osillator (VCO) 9. The output 10 of the VCO 9 is connected to a second input 11 of the phase comparator 3 and to an output terminal 1 2.

As is known, the phase comparator 3 produces an output signal which is proportional to the phase difference between the signal applied to the input terminal 1 and the output of the VCO 9. This output signal is fed through the loop filter 6 to the control input 8 of the VCO 9 to adjust its frequency so that it becomes locked to the input signal. The loop filter which is generally a low pass filter limits the rate at which the voltage at the input 8 of the VCO 9 can change so that the loop is not broken by transient voltages which may appear at the output of the phase comparator.

As has been stated hereinbefore the loop filter 6 may have a low cut off frequency and consequently may require the use of large value capacitors. Such components are difficult to produce as part of an integrated circuit. Fig. 2 shows an arrangement in which the loop filter 6 is replaced by a loop filter according to the invention, which loop filter comprises digital filter together with appropri ate analogue-digital interfaces.

The loop filter shown in Fig. 2 has an input terminal 20 which is equivalent to the input 5 of the filter 6 and which is connected to a first input 21 of an amplitude comparator 22. A reference source 23 which produces a uniformly distributed random amplitude reference signal at its output 24 is connected to a second input 25 of the comparator 22. The output 26 of the comparator 22 is fed to the input 27 of an n bit accumulator 28 whose output 29 is fed to the input 48 of a latch 49 whose output 50 is fed via an n way bus to the input 30 of a digital filter 31. The output 32 of the digital filter 31 is fed to an input 33 of a digtal to analogue converter 34 whose output 35 is fed to an output terminal 36 which output terminal is equivalent to the output 7 of the filter 6.A timing generator 37 has a first output 38 which is connected to a strobe input 39 of the comparator 22 and which produces pulses as shown in Fig. 3b; a second output 40 which is connected to an accumulate command input 41 of the accumulator 28 and which produces pulses as shown in Fig. 3c; a third output 42 which is connected to a reset input 43 of the accumulator 28 and which produces pulses as shown in Fig. 3e; and a fourth output 44 which is connected to a second input 45 of the digital filter 31, to a second input 47 of the digital to analogue converter 34, and to a strobe input 46 of the latch 49 and which produces pulses as shown in Fig. 4d.

The reference source 23 produces a reference signal having a randomly varying amplitude in which all amplitude values are equiprobable, the range of amplitudes being substantially equal to the input signal range. The reference source 23 may, for example, be constructed as described in a paper entitled "A Uniformly Distributed Analogue Random Voltage Generator" by F. Castanie which was published in Proceedings of the IEEE, Volume 66, No. 5, May 1978 at pages 605 to 606.

When an input signal is applied to terminal 1 (Fig. 1) the comparator 3 produces a voltage at its output 4 which is proportional to the phase difference between the input signal and the output of the VCO 9. This output voltage is fed to the first input 21 of the comparator 22 via the input terminal 20. The comparator 22 compares the amplitudes of the signals at its first and second inputs and when a signal is present on the strobe input produces an output signal at a logic '1' if the input signal amplitude is greater than the reference source output amplitude and a logic 'O' if the input signal amplitude is less than the reference source output amplitude. The strobe signal on input 39 causes the output to obtain the logic state appropriate to the input signals and to retain that state until the next strobe pulse.To achieve this function the output of the comparator 22 may be stored in a clocked bistable circuit which produces the output 26 and which is clocked by the strobe pulse. Thus as the input signal amplitude varies the number of logic 'l's at the output of the comparator varies proportionately. Thus if the input range is - V to + V and the current signal amplitude is vthen the average number of 'l's in a sequence is v+V 2V By using a strobed comparator which is strobed at intervals T as shown in waveform 3b) a stochastic sequence is generated the sequence being 2n- ' bits long.

The output from the comparator 22 is fed to the n-bit accumulator 28. The accumulator 28 is preset to 2"-' by a signal, Fig. 4e, from the timing generator at its reset input 43, this state being full negative in 2s-complement representation. On application of an accumulate signal the input 41, Fig. 4c, the accumulator will increment its state if the input signal at input 27 is a logic '1' and no change will occur if the input signal is a logic '0'. After 2n-' input values have occurred the total is fed from the accumulator output 29, by the action of the pulses shown in Fig. 4d which are applied from output 44 of the timing generator 37 to input 46 of the latch 49, to the input 48 of the latch 49. The output 50 of the latch 49 is fed to the input 30 of the digital filter 31 via an n line highway.The accumulator is then reset to 2n-1 by the signal Fig. 4e, from the timing generator 37 applied to its input 43. The combination of the strobed comparator and accumulator fulfills two purposes. The first is to average out the fluctuations in the input signal giving additional filtering at high frequency and the second is to reduce the rate at which signals are passed to the digital filter, the reduction factor being 2n-1.

The frequency characteristic of the digital filter 31 is as shown in Fig. 4 as curve A the attenuation increasing at a rate of 6dB/octave from the frequency w1 to the frequency w2. It is clear from this characteristic that the attenuation at high frequencies is limited and that noise will therefore not be eliminated. However a further low pass characteristic is added, curve B, having a cut off frequency remote from the loop filter corner frequencies by the combination of the comparator and accumulator to reduce the noise at high frequencies to an acceptable level.

The digital filter is a perfectly standard implementation of the required function which is derived by transforming the analogue transfer function, using the normal bilinear transformation, and making some approximations consequent upon the fact that the cut-off frequency is much smaller than the sample frequency. The derived transfer function is:

W2 where a = 1 wlT 2 k = cot 2 T' is sample period 1 ' is a delay of T'.

The implementation shown within the dotted rectangle shows the required operations and their sequence; in practice the details of the implementation may vary according to the technology being used, i,e. serial or parallel processing, multiplexed adders. The dimensions of the digital filter, i.e. number of bits used for processing and output, are dependent upon the individual application.

In the implementation shown block 300 is an adder, 301 a register which acts as a delay element having a delay period T' i.e. the period of the shift signal, Fig. 3d block 302 a second adder and the elements 303, 304 and 305 amplifiers having gains of - k, k/a and - 1 respectively.

The digital to analogue converter 34 should be selected to have the required resolution and operating speed to provide adequate control of the VCO.

The timing generator 37 comprises a clock oscillator giving an output signal of the form shown in Fig. 3a, a divider chain and decoding gates. Many detailed arrangements to give the required output waveforms as shown in Fig. 3 would be apparent to one skilled in the art.

Claims (3)

1. A loop filter for a phase locked loop comprising a phase comparator, a voltage controlled oscillator and a loop filter characterised in that the loop filter comprises a reference source for producing a uniformly distributed random amplitude reference signal, means for comparing amplitude of the reference signal and the output of the phase comparator at regular intervals and producing a signal having first or second logic status depending on the result of the comparison, means for accumulating the results of the comparison over a predetermined plurality of said intervals, means for applying the accumulated signal to the input of a digital filter, and means for feeding the output signal from the digital filter to the input of a digital to analogue converter, the output of the digital to analogue converter being the output of the loop filter.

2. . A loop filter for phase locked loop substantially as described herein with reference to Figs. 2 to 4 of the accompanying drawings.

3. A phase locked loop including a loop filter as claimed in Claims 1 or 2.