GB2103909A - Display control system - Google Patents

Abstract

A display control system for a cathode ray tube display (28) utilizing interlaced scanning includes a recirculating charge coupled device (CCD) memory (18). A main timing chain (12) provides clock signals to a clock control device (14) which includes a logical array (70) which controls the masking of selected ones of said clock signals whereby the stepping pulses utilized by the CCD memory (18) may be modified. In operation, the clocks for the CCD memory (18) are stopped during periods of horizontal retrace of the display (28) whereas during vertical retrace the CCD memory (18) is operated through one half of its recirculation cycle. The clock control device (14) is effective to modify the timing signal masking in response to scrolling control signals whereby the displayed image can be moved in an upward or downward direction. In a modification, the display (28) utilizes full field scanning and the CCD memory (18) is recirculated through a full recirculation cycle during each vertical retrace period. <IMAGE>

Description

SPECIFICATION Display control system This invention relates to display control systems for cathode ray tube display devices.

According to the invention there is provided a display control system for a cathode ray tube display device, including a recirculating memory adapted to store data to be displayed, timing signal generating means adapted to generate timing signals for controlling said recirculating memory, and control means coupled to said timing signal generating means and to said recirculating memory and adapted to stop the recirculation of said recirculating memory during periods of horizontal retrace of said display device and to operate said recirculating memory during periods of vertical retrace of said display device.

A display control system according to the invention has the advantage that the recirculating memory can be implemented as a volatile dynamic memory such as a charge coupled device (CCD) memory. A further advantage is that the system is readily adapted to permit scrolling, that is movement of the displayed image in an upward or downward direction.

In the preferred embodiment of the invention there is utilized a dynamic semiconductor memory in the form of a presently available COD memory device, the clocking of which may be momentarily halted for as long as 1 5 microseconds once each interval of 64 or more clock cycles. Horizontal retrace (blanking) of a CRT display can be accomplished in approximately 9 microseconds so the memory is directly compatible with a CRT insofar as horizontal scanning is concerned. However, since vertical retrace requires approximately 1.25 milliseconds, the memory clocks cannot be stopped for that period of time because stored data will be lost due to charge leakage.

One embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a block schematic diagram of the preferred embodiment of the invention; Figs. 2 through 6 are integrated circuit schematic diagrams of the main timing chain block of Fig.

1; Figs. 7A through 7D are integrated circuit schematic diagrams of the clock source block of Fig. 1; Fig. 8 is an integrated circuit schematic diagram of a buffer used in the preferred embodiment of Fig. 1; Figs. 9A and 9B are integrated circuit schematic diagrams of a portion of the clock interface block of Fig. 1; Figs. 10 and 11 are integrated circuit schematic diagrams of a portion of the clock interface block of Fig. 1; Figs. 1 2A through 14C are integrated circuit schematic diagrams of the memory block of Fig. 1; Fig. 1 5A and 1 5C are integrated circuit schematic diagrams of the serializer block of Fig. 1; Fig. 1 5C is an integrated circuit schematic diagram of the video combiner block of Fig. 1;; Fig. 1 6 is an integrated circuit schematic of the dot clock generate block of Fig. 1; Fig. 1 7 is a circuit schematic of the composite video generator block of Fig. 1; Fig. 1 8 is a logic schematic of a portion of a field programmable logic array of the type used in the preferred embodiment of Fig. 1; Figs. 1 9A and 1 9B are a truth table for a logic array; Fig. 20 is a truth table for a programmable read only memory; and Fig. 21 is a partially cut-away Table illustrating a memory map usable for programming the volatile memory block of Fig. 1.

Referring to Fig. 1, wherein a main timing chain 12 receives dot clock signals generated from a crystal control dot clock generator 22 which signals are labeled DCLK and DCLK. These signals have an occurrence rate equivalent to the dot spacing desired for the CRT display. The CRT display 28 of the present embodiment utilized a 30.24 MHz. dot signal. The main timing chain 1 2 in response to the dot clock signals generates character clock signals, CARCLK and CARCLK, which signals are utilized by a COD clock source 1 4 to generate memory clock signals MCLK and MCLK.In addition, the main timing chain 12, from the carrier clock signals, generates signals which indicate which line the scanning beam of the CRT is on, which character within the line that the beam is positioned at, whether the line scan is on an even or odd interlace, and whether there is an end of page corresponding to a completed display of a frame of data. Various horizontal, vertical and dot blanking signals are also generated by the main timing chain 12.

The COD clock source 1 4 operates upon the character and line position information through programmable memory logic units to derive memory clocking and accessing signals and to also provide vertical and horizontal sync. signals VSYNC and HSYNC, respectively to a composite video generator 26.A COD clock interface circuit 1 6 receives the memory clocking signals from the clock source 14 and converts these signals through various driver circuits into the clocking signals needed to clock the COD memory 1 8. The COD memory 18 receives input data on twenty lines labeled BDO- BD19. Data is written into memory under control of a write enable signal applied to the terminal labeledWE The CCD memory utilized in the preferred embodiment of the invention is manufactured by the Fairchild Company under their Part No. F464. The F464 charge coupled dynamic serial memory is a 65,536 bit memory. It is configured from 1 6 randomly accessible shift registers, each 4096 bits long.

The device is configured with an interlaced serial-parallel-serial register structure which structure requires the use of four different clocks. Two of the clocks are utilized for serial register shifting and two of the clocks are utilized for parallel register shifting. The serial clocks, and 02, control the movement of data within the input and output serial registers and have a frequency equai to the data rate. The transfer clock T1 [ is used to transfer data from the input serial register to the parallel registers while the transfer clock m is used to transfer data from the parallel registers to the output serial register.In the preferred embodiment of the invention the COD clock interface circuit 1 6 contains driver circuits for inverting thetsignals and for increasing the power level of thetsignals so as to drive the registers used in the COD memory. Character addressing of memory is accomplished utilizing the signals CAO--CAB from the buffer 30.

The output data from the COD memory 18 is in the form of twenty bits identified as ODO--OD19.

This data is directed to a serializer 20 comprised of a bank of shift registers. The shift registers operate to buffer the data and to place the data into a serial format and to forward the serialized data to a video combiner 24. The video combiner again synchronizes the data to the data clock, DCLK, and additionally subjects the data to blanking. The output signal from the video combiner 24 is labeled VID and is directed to a composite video generate circuit 26. Within the composite video generate circuit 26 the vertical sync and horizontal sync signals VSYNC and HSYNC, respectively, are appropriately mixed with theWsignal to provide an output video signal VIDEO OUT which is directed to the CRT display 28.

The serial signal received by the CRT display 28 consists of the data to be displayed, the synchronizing signals, vertical and horizontal sync., and the various blanking signals for permitting horizontal and vertical blanking without the loss of data.

Figs. 2 through 1 7 comprises the schematic diagram, at the integrated circuit level, of the preferred embodiment of the invention. Each sheet of drawing displaying the above Figures is marked in the upper right hand corner with a key number. The key number groups selected drawings and facilitates the tracing of interconnections between circuits. For example, in Fig. 2 there are a number of conductors having an arrowed index box numbered 11. This means that a corresponding conductor, one bearing for example the signal DCLK, can be found in the Figures bearing the key number 11. As another example the conductor labeled CARCLK having the arrowed box termination numbered 4, 5 and 8 is connected to a like labeled conductor appearing in the Figures associated with the key numbers 4, 5 and 8.

Referring now to the main timing chain 12 shown in schematic level in Figs. 2-6, bearing the key number 4, and specifically to Fig. 2, within the main timing chain the dot clock signal DCLK is applied as the clocking input to a four stage counter 40. The DCLK is also applied to the clocking inputs of the SR type flip-flops 44 and 41. The negated dot clock signal DCLK is applied to the clocking input terminal of the SR flip-flop 45. An AND gate 42 receives the count from three stages of counter 40 and provides a negated load digit signal labeled LD. The signal LD is directed to the CD input of flip-flop 44.

This signal is gated through flip-flop 44 by the dot clock and appears at the Q output. The signal at the Output is identified as S/L1 (shift load 1). The signal at the Q output of flip-flop 45 is identified as S/L2 (shift load 2). These signals are utilized in the gating of the shift registers shown in Figs. 1 5A and 1 5C. The other outputs from the counter 40 are the basic character clock signal, CARCLK and the character clock signal negated CARCLK. The inversion process is by an inverter 46. An AND gate 43 receives the outputs of each of the four stages of counter 40, and directs its gated signal to the CD input of the SR flip-flop 41. The output signal from flip-flop 41 is the end of character signal labeled EC.

This signal is directed back to an ANDing input of the counter 40. A counter 48 (Fig. receives as its clock the CARCLK signal and at another of its inputs an end of line signal identified by EOLI. in response to these two signals, a count is generated which count is a function of the first sixteen character positions. A counter 49 also receives the CARCLK signal and the end of line signal EOLI. The EOLi signal occurs when 91 characters, corresponding to a line, are traced across the CRT display, and causes the counters 48 and 49 to reset. Counter 49 provides outputs corresponding to character counts 16, 32 and 64. The signals on counter terminals C64, C16, C2 and C8 are ANDed together in AND gate 50 (Fig. 5) to provide a count of 90 when each terminal is active.The next clock, corresponding to count 91, will reset counters 48 and 49 to zero. The signal SOLI corresponds to count 91. An inverter 51 (Fig. 5) provides the signal EOLI. The end of line signal EOLI from inverter 51 is directed as an input to an AND gate 52 (Fig. 3) along with an end of page signal labeled EOP which signal is derived from the COD clock source shown in Figs. 7A and 7B. The ANDed signals result in an end of page signal identified as ENP. The signal ENP along with the signal EOLI and the signal CARCLK are applied as logic inputs and a clocking input respectively to line counters 53, 54 and 55 (Fig. 3). The outputs from these counters are the line count signals identified respectively as lines 128, 64, 32, 16, 2048, 1024,512 and 256. Counters 53,54 and 55 are incremented when an EOLI signal and a CARCLK signal occur. During the scanning process of the CRT an output appears on each of the respective terminals when the line count corresponds to the number adjacent the particular counter output. When an ENP (End of Page), and CARCLK signal are applied to counters 53, 54 and 55 the counters are reset to zero. Thus far the major signals developed are the character clock signal which occurs at the occurrence of each character, a character count signal which occurs and identifies the position of each character displayed on the CRT and a line count signal which identifies the positioning of the scanning line at any point in time.

A pair of quad D flip-flops 58 and 59 (Fig. 6) operate upon input signals C64, L512, BLI, CARCLK and CARCLK to provide horizontal and vertical blanking outputs, HBLANK and VBLANK, data blanking outputs, DBLANK and DBLANK along with a character blank CBLANK and a OBLANK signal. These signals are utilized by the system to blank the display system during periods when data is not to be displayed. For example the QBLANK signal is used to blank the screen in quarter screen increments.

Inverter 56, AND gate 57, AND gate 60 and inverter 61 operate upon signals appearing at outputs of the quad D flip-flop 58 and upon the signals L51 2 and C64 to provide an output signal BLANK and a WBLANK signal.

Referring now to Figs. 7A-7D, a field programmable logic array 70 receives as inputs the line count signals labeled "L" along with the character count signals C4, C8, C16 and C64. In the preferred embodiment of this invention there are 91 characters per line. The signal labeled FR indicates whether an even or odd field is being scanned. The signals SCD and SCU indicate whether there is to be a scroll up or a scroll down.The outputs of the field programmable logic array are a vertical sync signal which appears on output 1 8 (Fig. 7C), an end of page signal which appears on output 1 3 and a horizontal sync signal which appears on output 1 5. The signals on outputs 10-1 2 select one of eight clock signals for the COD memory device. These signals are directed to an 8:1 line data selector 74.

Additional inputs to the data selector 74 are received from a programmable read-only memory mask generator 73. The output from the data selector is directed to counters 77 and 78 which counters count at the rate dictated by the output signal from selector 74. The counter outputs are the memory access clock signals MA0-MA5. Additional outputs from the field programmable logic array 70 are directed to JK flip-flops 71 and 72, the outputs of which are the vertical and horizontal sync signals.

The selected memory clock signal from selector 74 is also directed to a pair of Exclusive OR gates 79 and 80 which provide the memory clock signal inverted MCLK and the memory clock signal MCLK respectively. Additionally, an inverter 75 and an SR flip-flop 76 operate upon the line count signal L51 2 to effectively divide the signal by two to provide the signal FR and its inverted value FR.

Additionally, the inverter 75 provides the signal L512. The signal FR indicates whether the line scan is on an even or an odd interlace.

The field programmable logic array 70 is programmed according to the truth table shown in Figs.

1 9A and 19B. The programmable read-only memory (PROM) mask generator 73 is programmed according to the truth table of Fig. 20. The PROM masks selected clocks from the continuous clock train CARCLK to provide 8 selectable clock trains to the 8:1 line data selector 74.

Referring now to Fig. 8, a plurality of AND gates labeled 102-105 receive the line count signals L64, L128, L256 and the signal FR at their respective inputs and provide at their outputs the character signals CAO, CA1, CA2 and CA3. These signals are utilized as addresses for the 1 6 internal 4096 bit shift registers in the COD memory shown in Figs. 12 through 14.

Referring now to Figs. 9A and 9B wherein a portion of the circuitry for the COD clock interface 1 6 is shown in detail. The basic clocking signals1 ,(il2 and T1 and OWT2 are generated by logically combining the memory accessing clocks MAO-MA5 with the memory clocks, MCLK and MILK. The clocks MAO, MA2, MA3 and MA4 are applied to the inputs of an AND gate 90. An X to Y coder 91 receives the output from AND gate 90 along with memory accessing clock signals MA1 and MA5 to provide four signals to the inputs of a quad D-type flip-flop 92. The MCLK signal is applied to a delay line 82.Four of the output delays, 130, 80, 50 and 25 nsec. are directed to inverters 83, 84, 85 and 86, respectively, and to the inputs of AND gate 88 and the logic gating arrays 93 and 94. The logic gating arrays 93 and 94 also receive the outputs from the quad D flip-flop 92 to provide at their outputs the signals T1 and (iiT2. The AND gates 87 and 88 additionally receive the MCLK and the MCLK signals to derive the clocking signals 1 and2.

Referring to Figs. 1 0 and 11 wherein the remaining portion of the COD clock interface 1 6 is shown, six MOS driver circuits 95-100 receive as their inputs the clocking signals 1 and 2 and for MOS drivers 99 and 100 the clocking signals (t'T1 and T2. Each driver circuit provides at its output four clocking signals. These clocking signals are particularly adapted for application to a CCD-type memory shown specifically in Figs. 12-14. The drivers provide eight of the 1 signals, eight of the 2 signals and four each of the T1 and T2 signals. Several driver circuits are needed because of the high capacitance of the COD memory.Each CCD memory chip has, for example, 100 pf. on 1, and 2 and 20 pf. on T1 and Q)T2. Each clock driver circuit can drive 300 pf. The timing of the COD memory is selected by the manufacturer to provide the best performance for their product. In the disclosed embodiment of the invention a Fairchild F464 COD memory was used and the data sheet for that particular memory was complied with.

The CCD memory 1 8 is shown in integrated circuit schematic form in Figs. 1 2 through 14. The memory elements are interconnected in a standard configuration and require no further description.

The total memory is shown for purposes of displaying the interconnects between the memory and the other block elements of applicant's system.

The chart of Fig. 21 depicts a memory map that was used for the COD memory 18. The memory map shows what locations in the COD memory hold what lines of data. The memory map is organized as 1024 lines (the number of display lines). The first field holds lines 0-511. The second field holds lines 512-1023. The left column of the table is the bit position in the COD shift register. There are 0 through 4095 bit positions. The table is incremented by sixty four bits. The top of the table shows the shift register number with each COD having 1 6 shift registers which are each 4K bits long. The first 64 bits come from shift register 0 with the next 64 bits coming from shift register 1. Each of the remaining shift registers are loaded in a similar manner.There are 91 characters per line and at the occurrence of that count the signal EOL resets the character counter. Line counters 53, 54 and 55 (Fig. 3) count the number of lines per field. The line counter and the character counter provide the inputs to the field programmable logic array 70 (Figs. 7A and 7C). The signal on line L51 2 appearing at the output of counter 55 when divided by two provides the even or odd field signal FR. The circuit for providing this dividing function is shown in Figs. 7C and 7D as elements 75 and 76. The signal ENP is a result of logically ANDing the end of page signal EOP with the end of line signal EOL. The ENP signal is utilized to reset the line counter. As previously mentioned, the character counter resets on the count of 91.

Referring to Figs. 1 5A and 1 5C, six shift registers 106 through 111 comprise the serializer 20.

The twenty bits of output data are formed into two streams of data appearing at the outputs of shift registers 108 and 111. In Fig. 1 6 the dot clock generator is shown comprised of a crystal oscillator 22 utilizing a pair of inverters 1 27 and 128 coupled in circuit to a 30.24 MHz. crystal 129. An inverter 130 buffers the output from the inverters and couples its output to the inputs of Exclusive OR gates 131 and 132. The output from the OR gates are the dot clock signal DCLK, and DCLK.

Referring now to Fig. 1 SB, wherein the video combiner 24 comprised of inverters 121, 122 and ANDing gates 120,123, 124, 125 and 126 are logically interconnected so as to form a serial stream of video and blanking information which stream appears at the output of AND gate 1 26 and is identified as the signal VID. This stream of video data is fed to a composite video generate circuit 26 shown in Fig. 1 7. Circuit 26 synchronizes the stream of data with a vertical sync and horizontal sync.

signal. The video data appears at the input of an inverter 141 and the sync. data appears at the input of AND gate 140. The NPN transistors 142 and 143 are collector coupled so as to combine the sync. data with the video data. The composite signal is the video output signal that is directed to the input of the CRT display 28 (Fig. 1).

Referring to Fig. 1 8 in conjunction with the Table of Figs. 1 9A and 19B. Within the FPLA 70 (Figs.

7A and 7C) package there are forty-eight AND gates each having 1 6 inputs. For simplicity of explanation only two are shown-AND gate 150 and AND gate 151. There are also eight OR gates 1 52. The gates and interconnects used for one function, the VSYNC set, are shown the other functions set out in the table of Figs. 1 9A and 1 9B are implemented in a similar manner. Each input line to an AND gate has, in the unprogrammed mode, three inputs. The first is a direct connection between an FPLA pin and an input to an AND gate (designated "H" in the table of Figs. 1 9A and 19B).The second is an open connection, indicated by two X's with the respective AND gate input connected to a high potential +V (designated with a "-" in Figs. 1 9A and 19B). The third is a path from the FPLA pin which includes an inverter 1 53 (designated "L" in Figs. 1 9A and 19B). Programming of the FPLA requires selection of these three types of inputs. The outputs from the forty-eight AND gates can, programmably, be connected to the inputs of the OR gates 1 52. For the VSYNC set function, the OR gate input terminals 2-47 are inactivated by connecting them to ground. The input, labeled P-term 0, is connected to receive the output of AND gate 1 50. The input, labeled P-term 1, is connected to receive the output of AND gate 1 51.The output of OR gate 1 52 is connected to the FPLA 70's pin 18, shown in Fig. 70. The seven remaining OR gate outputs are connected to the FPLA pins 1 7, 1 6, 1 5, 1 3, 12, 11 and 10. The sixteen AND gate inputs are connected to the FPLA pins designated in Fig.18, with each pin assigned an associated input variable from 0 through 1 5.

In the table of Figs. 1 9A and 1 9B the output functions (output of OR gates 1 52) are active when shown encoded with an "A". In the preferred embodiment of the invention an output is active when high and inactive when low. The inactive state is shown in the table as a " . ". With two fields of scan comprising one display of data it is necessary to have two VSYNC set signals, one occurring after each field. In the table the first line of coding shows which signals should be high, "H", which should be low "L" and which are in a don't care "-" state for the times VSYNC is to be active "A". For field 0, C4, FR, C32, C16, L32, L16, and L8 are low. "L"-C8, L512, C64, L4, L2 and L1 and high "H". All remaining terms are in the don't care state "-". When the states of the signals are as indicated the output signal on pin 18 of the FPLA 70 will be high. In a like manner when the signals are in the state indicated by line 2 (P-term=1) of the Table the signal on pin 18 will be high. The Table thus sets forth the coding for all eight outputs of the FPLA 70. In operation then: P terms 0, 1 are used to set VSYNC P terms 2,3 are used to reset VSYNC P term 4 is used to set HSYNC P term 5 is used to reset HSYNC P terms 6, 7 are used to set EOP Output functions 5, 6, 7 are used to select one of eight masks for the clock.

P term 8 selects ROM DO (let ail clocks through) normal scan P term 9 selects ROM D1 (let no clocks through) horizontal blank P terms 1 0, 11, 1 2, 13 select combinations of the eight clocks on the vertical blank interval of field 0 to get exactly 2048 clocks.

P terms 14, 1 5, 1 6 select combinations of the eight clocks on the vertical blank interval of field 1 to get exactly 2048 clocks.

P term 1 7 changes the vertical blank interval of field one so that 2032 clocks are generated. This causes a scroll down by 1/4 of the screen height.

P term 18 changes the vertical blank interval of field 1 so that 2064 clocks are generated. This causes a scroll up by 1/4 of the screen height.

Fig. 20 illustrates the truth table for the PROM 73. The Address column corresponds to the state of the signals on the PROM inputs labeled C8, C4, C2 and 01. The outputs are labeled DO through D7.

The bottom row indicates the number of clocks per line that will be passed for each D selected.

The logic coding to arrive at the number of clocks per field is as follows: Table 12 Field 0. L512 O64D0 Normal L512.C64#D1 L512 L32D2 32x46=1472 L512 L32 L16.L8D2 8x46= 368 L512#L32#L16#L8#L4#L2#D3 2x69= 138 L512#L32#L16#L8#L4#L2#L1#D4 1x70= 70 2048 Field 1 L512#C64#D0 Normal L512 O64D1 L512 L32D2 32x46=1472 L512 .L32 L16.'t8D5 8x56= 448 L512.L32.L16 L8.L2D6 2x64= 128 2048 Field 1 Same except L512 L32 L16 L8 .72D5 2x56= 112 SCD 448 1476 2032 Field 1 Same except L512 L32 L16 L8D7 8x58= 464 SCU 1472 128 2064 The following signals are labeled in the drawings but do not play a major role in the invention.

Because they are shown, the following usage definitions are provided.

QBLANK is "quarter screen blank" so that 1/4 increments of the screen can be blanked while images are built underneath. WBLANK (write blank) is a mask used to time the data strobes to the bus that supplies data to the system.

S/L1 (shift-load 1) S/L2 (shift-load 2) are used to control the loading and shifting of the two interleaved shift registers for video output.

KBVID is "keyboard video". This is character data from other systems that is overlayed on the image data of the present system.

DBLANK is "delayed blank". The actual screen blanking must be delayed slightly to allow time for the data to emerge and stabilize from the CCD's.

TOB 1 is "time out blank". If the system is not used for fifteen minutes a timer automatically blanks the screen to protect the CRT screen from a burn-in of the image.

PRI is "priority". The keyboard character data that overlays the image can be logically OR'ed or if "priority" is set, the character cells will lay on top of the image and obliterate it.

In summary, in the present embodiment recirculation of the volatile memory is stopped during periods of horizontal blanking of the CRT display and during vertical blanking the volatile memory is recirculated. In the preferred embodiment of the invention interlaced scanning is used. Interlaced scanning creates an image by scanning first along even-numbered lines and then along odd-numbered lines to form one field of data. The volatile memory was therefore recirculated one-half of the way on the first vertical retrace and the remaining one-half during the second vertical retrace. For each image field there are thus two vertical blanking intervals. By adding or deleting clock pulses from the recirculating operation a scrolling effect either up, or down can be accomplished.If full field scanning is used the memory is completely recirculated during each vertical blank period.

Thus, it will be appreciated that there is provided a volatile re-circulating memory coupled to a CRT display for storing data bits and to a source of clock pulses for clocking the volatile memory at a rate adequate to maintain the refreshed status of the memory. Means are provided for deleting the application of clock pulses to the volatile memory during periods of horizontal retrace. During vertical retrace the number of clock pulses applied to the volatile memory is modified so as to re-circulate the memory from the last displayed data bit to the next to be displayed data bit. For interlaced scan the volatile memory would be clocked approximately through one-half of its storage capability and for normal scan the volatile memory would be completely recirculated. Thus for one field of data the volatile memory is completely recirculated. Means are also provided for inserting additional clocks during a vertical retrace for purposes of moving the commencement of a line scan either one up or one down. Visually this creates a scrolling effect either upward or downward on the screen.

Claims (9)

Claims

1. A display control system for a cathode ray tube display device, including a recirculating memory adapted to store data to be displayed, timing signal generating means adapted to generate timing signals for controlling said recirculating memory, and control means coupled to said timing signal generating means and to said recirculating memory and adapted to stop the recirculation of said recirculating memory during periods of horizontal retrace of said display device and to operate said recirculating memory during periods of vertical retrace of said display device.

2. A display control system according to claim 1, wherein said display device operates with interlaced scanning and wherein said control means is effective to recirculate said recirculating memory one-half way through a recirculation cycle during each said period of vertical retrace.

3. A display control system according to claim 1, wherein said display device operates with full field scanning and wherein said control means is effective to recirculate said recirculating memory through a full recirculation cycle during each said period of vertical retrace.

4. A display control system according to any one of the preceding claims, wherein said control means includes masking means adapted to mask selected ones of said timing signals thereby providing clocking signals for use in clocking said recirculating memory.

5. A display control system according to claim 4, wherein said timing signal generating means is adapted to generate character clock signals corresponding to respective character positions formed on said display device and wherein said masking means includes logic means responsive to logic control signals provided by said timing signal generating means to mask selected ones of said character clock signals.

6. A display control system according to clalm 5, wherein said logic means is responsive to scrolling control signals to modify the masking of said character signals so as to scroll the image displayed by said display device in an upward or downward direction.

7. A display control system according to any one of the preceding claims, wherein said recirculating memory is a memory having a refresh period within which refreshing is needed, said refresh period being greater than the horizontal retrace period and less than the vertical retrace period of said display device.

8. A display control system according to claim 7, wherein said recirculating memory is a charge coupled device memory.

9. A display control system substantially as hereinbefore described with reference to the accompanying drawings.