GB2148078A - Scrolling display circuit - Google Patents

Abstract

A display circuit for a personal computer comprises a display memory for storing display data, a display for displaying the display data, an interrupt circuit for interrupting the display data only when a vertical synchronization signal is generated in the display, a window circuit for windowing the displayed data in the display, the window circuit being operable in response to the interrupt circuit. The scrolling may be carried out either by reading from different memory addresses or by entering new data from buffer memories during the frame blanking periods. <IMAGE>

Description

SPECIFICATION Scrolling Circuit for Computer Display Background of the Invention The present invention relates to a computer display and, more particularly, to a scroll circuit for a display of a personal computer with a window feature.

Conventionally, in a personal computer of the bit map display, the scrolling of a display on a display device such as a cathode-ray tube (CRT) is carried out by renewing the total contents of a display memory such as a random access memory (RAM) by a single frame, so that the renewed contents of the display memory are displayed on the CRT display. Therefore, a considerably long time is needed to scroll the display.

Summary of the invention Accordingly, it is an object of the present invention to provide an improved scroll circuit for a computer display.

It is another object of the present invention to provide an improved scroll circuit of a personal computer display using a window feature for displaying any partial contents of a display memory on a cathode-ray tube (CRT) display, so that a rapid scroll can be performed without renewing the total contents of the display memory.

It is a further object of the present invention to provide an improved scroll circuit for a personal computer display to prevent a displayed picture from flickering when windows are scrolled.

Briefly described, in accordance with the present invention, a display circuit for a computer comprises display memory means for storing display data, display means responsive to the display memory means for displaying the display data, interrupt means for interrupting the display data only when a vertical synchronization signal is generated in the display means, window means for windowing the displayed data in the display means, the window means being operable in response to the interrupt means.

Brief Description of the Drawings The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: Figures 1(A) and 1(B) are schematic illustrations of a display scroll method according to the present invention; Figures 2 through 5 are flow charts of the operation of the display scroll in the present invention; Figure 6 is a block diagram of an interrupt circuit for the display scrolling of the present invention; and Figure 7 is a block diagram of a circuit of a personal computer according to the present invention.

Description of the Invention Figures 1(A) and 1(B) are schematic illustrations of a display scroll method according to the present invention. Figure 1(A) relates to a display prior to the scroll operation while Figure 1(B) relates to another display posterior to the scroll operation.

The display scroll according to the present invention is carried out with a window feature between a display memory such as a random access memory (RAM) and a display such as a cathode-ray tube (CRT).

Referring to Figures 1(A) and 1(B), a display memory such as a V-RAM (Video RAM) is provided including a plurality of lines A-E the alignment of which indicates a condition of storing the display data. A CRT display 2 is provided for receiving the display data from the V-RAM 1 with a window feature. The window feature is that any partial contents (ones of lines A-E) of the V-RAM 1 are displayed on the CRT display 2. As shown in Figure 1(A), prior to the display scroll operation, the display data of the lines A and B are displayed on a window "0" positioned at the upper portion of the CRT display 2 while the display data of the lines C-E are displayed on another window "1" positioned at the lower portion of the CRT display 2. Figure 1(B) shows a condition of the V-RAM 1 and the CRT display 2 after a single-line scroll has been carried out.

The contents of the V-RAM 1 are divided into any desired portions. Using the window feature, any desired partial contents of the V-RAM 1 are displayed on any desired portions of the CRT display 2. By modifying the arrangements of the windows "0" and "1", a line scroll per single line, or a raster or smooth scroll per raster is performed.

Some rasters are contained in a single line. If the sizes and the display positions of the window "0" and "1" are changed, a rapid scroll can be enabled without renewing the total contents of the V-RAM 1.

Since the gist of the present invention is not directed to the window feature, any further description of the window feature is omitted.

Figure 6 is a block diagram of an interrupt circuit for preventing the display from flickering upon changing the window. This interrupt circuit is to cause an external or hardware interrupt.

The interrupt circuit of Figure 6 comprises a CRT controller 3, an interrupt controller 4, and a central processing unit (CPU) 5. The CRT controller 3 provides a vertical synchronization signal (VSYNC) to an input terminal of the interrupt controller 4. The controller 4 provides an interrupt signal from an output terminal thereof to an input terminal of the CPU 5. The CPU 5 is responsive to the interrupt signal for executing an interrupt routine. That is, to prevent the display on the CRT display 2 from flickering upon changing the window, an interrupt to the CPU 5 is made in response to the VSYNC from the CRTcontroller3to enable the scrolling of the display.

For example, the CRT controller 3 is MPD 7220, the interrupt controller 4 is 8259A, and the CPU 5 is 8086, all produced by Sharp Corporation, Japan.

Figures 2 through 5 are fiow charts of the operation of the display scroll according to the present invention.

(1) Data Input Flow of Figure2 Step n1: This step is selected to reset a flag FST at a predetermined location of a memory such as a RAM (basic RAM).

Step n2: A character code is inputted into a buffer means as data. The buffer means is formed at a predetermined location of the (basic) RAM. The buffer means is two buffers "alpha" and "beta".

Depending on the inputted character code, a character generator is accessed to enter a generated pattern into one of the two buffers. The provision of the two buffers is for the advantage that when, in an interrupt routine (step t3 of Figure 5), the display data are transferred from the buffer into the V-RAM 1 per raster, a next display data is entered into another buffer so as to shorten the processing time.

Then, any break of the display lines on the CRT display 2 cannot be recognized, so that a smooth scroll is performed.

Step n3: This step is selected to detect whether it is necessary to conduct scrolling.

Step n4: When a data by a single line or a line feed code is present, this step n4 is selected to execute a scroll subroutine of Figure 3.

(2) Scroll Subroutine of Figure 3 Step ml: This step is selected to detect whether scrolling is conducted first or not.

Step m2: When scrolling is not first, this step is selected to cause a window operation by enabling the interrupt with the VSYNC from the CRT controller 3.

Step m3: When scrolling is first, this step is executed to renew a pointerforthe CRT display by a single line. This pointer is provided for directing the top of the display. The reason why the pointer for directing the display on the CRT display 2 is renewed by the single line instead of the window operation is that, in view of the provision of the two buffers, the next display data by the single line is entered into a buffer so as to smooth cause scrolling without any break of the display lines being recognized.

(3) Window Operation of Figure 4 Step s1: While step m3 of Figure 3 has been executed to renew the pointer by the single line, step s1 is selected to renew the pointer per single raster with reference to the previous pointer, so that the windows are shifted per single raster as shown in Figure 1(B).

Step s2: This step is selected to calculate the map position and the size of the window with reference to the pointer.

Step s3: This step is selected to enable an interrupt with the VSYNC from the CRT controller 3.

(4) Interrupt Routine of Figure 5 Since the display of the CRT display 2 is performed with the scanning of the electron beams called the raster scanning, the windows should be changed in synchronization with the timing of the raster scanning to prevent the display from flickering upon the momentary break of the raster scanning. According to the present invention, the interrupt operation of Figure 5 is carried out while the VSYNC or the vertical blanking is generated, so that the changing of the windows is performed during the generation of the VSYNC or the vertical blanking. No flickering of the display is thereby caused. The interrupt operation is the scroll operation.

Step t1: All the registers as contained in the CPU 5 are saved and sheltered to prohibit every interrupt.

Step t2: The windows are shifted based on the parameters calculated at step s2 of Figure 4.

Step t3: The character data entered into the inner buffer at step t3 is transferred in the V-RAM 1 by a single raster. Therefore, a single-raster scroll of the display on the CRT display 2 is performed.

Step t4: This step is executed to detect whether the single-line display data has been completely transferred from one inner buffer into the V-RAM 1.

Step t5: If the transference has not been completed, the pointer is further renewed by a single raster.

Step t6: This step is executed to calculate the window parameters.

Steps t7 and t8: These steps are executed to enable all interrupt including the VSYNC from the CRT controller 3.

Step t9: All of the registers are made re-operable.

Step t10: The previous routine is returned.

When the single-line scrolling has been completed, step t8 is selected to enable the interrupt operation except the interrupt operation with the VSYNC from the CRT controller 3 by masking the interrupt operation with the VSYNC. Steps t9 and t10 are selected thereafter.

Figure 7 is a block diagram of a circuit of a personal computer according to the present invention. The circuit of Figure 7 includes the interrupt circuit of Figure 6.

Circuit elements of Figure 7 as related to the interrupt operation are as follows: PIC: the interrupt controller 4 of Figure 6 IPL-ROM (Initial Program Loader)-ROM: ROM storing initially operated program Basic RAM: RAM comprising two buffers and the flag FST DMAC: Direct Memory Access Controller FDC: Floppy Disc Controller VFO: Voltage-Frequency Oscillator PIO: Peripheral I/O Controller SIO: Serial I/O Controller GDC: Graphic Display Controller, the CRT controller 3 of Figure 6 WDC: Window Controller V-RAM: Video RAM According to the above-described logic, the changing of the windows is carried out during the generation of the vertical blanking, so that the flickering of the CRT display 2 cannot be caused and the interrupt operation is performed, in which the display data are smooth transferred so as to smooth scroll the displayed data.

Further, since the renewal of the pointer at step s1 of Figure 4 permits the number of rasters scrolled at once to be freely selected, the line scroll and the smooth scroll per raster can be performed in terms of the same logic.

According to the present invention, the scrolling of the displayed picture can be performed without renewing the total contents of the display memory by a single display frame, thereby enabling rapid scrolling.

While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the present invention as claimed.

Claims (6)

1. A display circuit for a computer comprising: display memory means for storing display data; display means responsive to said display memory means for displaying the display data; interrupt means for interrupting the display data only when a vertical synchronization signal is generated in said display means; and window means for windowing the displayed data in said display means, said window means being operable in response to said interrupt means.

2. The circuit of claim 1, wherein said interrupt circuit means operates to enable the scrolling of the display data.

3. The circuit of claim 1, wherein said window means comprises two buffers for receiving a first set and a second set of display data, respectively.

4. The circuit of claim 2, wherein said scrolling of the display data is a line scroll or a raster scroll.

5. A display circuit for producing a signal to display an image on a raster-scanned display screen, the image comprising respective window regions each displaying the contents of respective memory locations, wherein the display circuit is operable to scroll the image by altering the correspondence between the window regions and the memory locations whose contents are displayed therein during a vertical blank interval between successive scans of the display screen.

6. A display circuit substantially as herein described with reference to the accompanying drawings.