GB2103406A - Improvements in or relating to microprocessor alarm systems - Google Patents

Abstract

A microprocessor alarm system comprises an electroacoustic transducer 107 and a microprocessor 101. The microprocessor responds to reception by the transducer of sound above a threshold level by timing an interval and a set of delays whenever the sound is above the threshold level, and entering an alarm mode if a predetermined number of delays is produced within the interval. Such a system is sensitive to the breaking of glass or splintering of wood, but is substantially immune to other noises such as background noise. <IMAGE>

Description

SPECIFICATION Improvements in or relating to microprocessor alarm systems The present invention relates to microprocessor alarm systems. Such systems may, for instance, be used to detect intruders or attempted breaking into a property.

According to the invention there is provided a microprocessor alarm system, comprising an electroacoustic transducer and a microprocessor, the microprocessor being arranged, in response to the reception by the electroacoustic transducer of a sound level above a threshold level, to time a predetermined interval and to time a delay, to time a further delay after each preceding delay whenever the transducer receives a sound level above the threshold level, to time a further predetermined interval after each preceding predetermind interval whenever the transducer receives a sound level above the threshold level, and to enter an alarm mode if the number of timed delays exceeds a predetermined number within any one of the predetermind intervals.

Preferably the electroacoustic transducer is connected via an envelope detector and a comparator to an interrupt input of the microprocessor.

Preferably each timed predetermined interval is 2 to 3 second, the predetermined number is 4, and each delay is about 30 milliseconds.

According to another aspect of the invention, there is provided a microprocessor alarm system, comprising an electroacoustic transducer, a microprocessor arranged to control the production of alarm signals, and a circuit arrangement arranged to prevent the supply of power to the microprocessor during standby operation and to permit the supply of power to the microprocessor for a predetermined period after reception by the transducer of a sound level above a threshold level.

Preferably, the microprocessor is provided with a random access memory, the microprocessor being arranged to check correct operation of the memory by storing therein a chequer pattern of 0's and 1's, by reading the contents of the memory, and by checking the contents of the memory as read.

Preferably, the microprocessor is arranged to perform a subsequent further memory checking operation by storing in the memory a pattern of 0's and 1's, complementary to the chequer pattern, by reading the contents of the memory, and by checking the contents of the memory as read.

Preferably, the microprocessor is provided with a read only memory, the microprocessor being arranged to check the memory by calculating one or more sums of the contents of the memory and checking the one or more sums against the known correct sum or sums.

Preferably, the microprocessor is arranged to form a plurality of sums, each comprising the sum of 16 nibbles where each nibble is four bits, and to compare each sum with the known value which is stored in the memory.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic circuit diagram of a microprocessor alarm system constituting a preferred embodiment of the invention; Figure 2 is a circuit diagram of a power supply of the system of Figure 1; Figure 3 is a circuit diagram of an input section of the system of Figure 1; Figure 4 is a circuit diagram of a clock of the system of Figure 1; Figure 5 is a circuit diagram of an output section of the system of Figure 1; Figure 6 is a circuit diagram of a microprocessor section of the system of Figure 1; and Figures 7a - fare a flow diagram illustrating operation of the system of Figure 1.

The microprocessor alarm system shown in Figure 1 comprises a microprocessor section 101 which, as shown in Figure 6, comprises an integrated circuit microprocessor 102 of the Z80 type, an electrically programmable read only memory 103, and a random access memory 104. The microprocessor section 101 has an interrupt input connected via a resistor R45 and a gate 105 wired as an inverter to the output of an input section 106. The input section 106 includes an electroacoustictransducer 107 which functions both as a microphone and as an audible alarm or hooter.

The output of the input section 106 is connected to one input of a NOR gate 108 whose other input is connected to an input of a NAND gate 109 and via a resistor R36 to a connection between a capacitor C27 and a resistor R35. The other side of the capacitor C27 is connected to a "shunt" terminal H22, which is also connected to the connection between a capacitor C28, a resistor R37 and a resistor R38. Another shunt terminal H25 is connected to the common line, to which the other terminals of the capacitor C28 and the resistor R35 are connected.The other side of the resistor R37 is connected to a supply line whereas the other side of the resistor R38 is connected to the base of a transistor TR16, whose emitter is connected to the supply line and whose collector is connected via a resistor R34to the common line, The collector of the transistor TRi 6 is also connected to one input of a NOR gate 110, whose other input is connected to the output of the gate 108.

A power supply of the system comprises a battery or accumulator 111 connected to the output of a current-limited regulator 112 supplied by the mains and to the input of a 5v regulator 113 which supplies power to the power supply line of the microprocessor section 101. The battery 111 supplies power to the input section 106 and to the circuit containing the transistorTR16. The 5v regulator 113 has an ENABLE input connected to the output of a NOR gate 114 which, together with another NOR gate 115, is connected as a set-reset bistable. The set input of this bistable is connected to the input of the gate 110 whereas the set output is connected to the ENABLE input of the regulator 113. The reset input of the bistable is connected to an address line A13 of the microprocessor section 101, whereas the reset output is connected to an input of a NOR gate 116.

The other input of the gate 116 is connected to the output of a NAND gate 117 which has a first input connected via a resistor R28 to a power switch-on reset circuit comprising a resistor R27 and a capacitor C25. The other input of the gate 117 is connected via a resistor R30 to another power switch-on resetting circuit comprising a resistor R29 and a capacitor C26, and is connected via a resistor R31 to the output of the gate 116. The output of the gate 116 is further connected to a reset line, via a resistor R32 to the reset input of the microprocessor section 101, via a gate 118 connected as an inverter to to a restart line, and to one input of a NAND gate 119. The gate 119 together with another NAND gate 120 is connected as a "negative-logic" bistable with an output connected to a line AA.The other input of the gate 120 is connected to the output of the gate 109, which is also connected via a resistor R39 to a on maskable interrupt terminal of the microprocessor section 101.

The second input of the gate 109 is connected via a resistor R33 to ground and direct to an address output A15 of the microprocessor section 101.

Another address output A11 of the microprocessor section 101 is connected via the parallel combination of a resistor R42 and a capacitor C29 to one side of an "entry delay" section switch SW2, whose other side of an "entry delay" selection switch SW2, whose other side is connected to the base of a transistor TR3 and via a resistor R41 to the common line. The emitter of the transistor TR3 is connected to the common line whereas the collector thereof is connected to a line Do and via a resistor R40 to the 5v supply line from the regulator 113.

The microprocessor section 101 has a clock input connected to a clock 121 and outputs A12 and A14 connected to a horn driver 122 and a relay driver 123 which, together, constitute an output section. The outputs A12 and A14 are further connected to the 5v supply line via respective resistors R75 and R76.

Aterminal H16 is connected via a resistor R80 to the input of a NOR gate 124. The input of the gate 124 is connected via a parallel combination of a resistor R81 and a capacitor C41 to ground. The output of the gate 124 is connected via a diode D25 to the connection between a resistor R79 and one input of the gate 110.

Figure 2 shows in more detail the power supply of the microprocessor alarm system. The power supply comprises a mains transformer T1 whose primary winding is connected to mains input terminals via fuses with a mains spike suppression device connected thereacross. The secondary winding of the transformer T1 has a center tap connected to the common line and two end connections connected to rectifier diodes D14 and D15. The cathodes of the rectifier diodes D14 and D15 are connected to a decoupling capacitor C37 which serves to reduce interference and maintains stability of an integrated circuit voltage regulator 125 of the "723" type. The capacitor C37 does not function as a reservoir capacitor. Indeed, no such reservoir capacitor is provided in the regulator 112 as this is unnecessary for charging the battery 111.

The capacitor C37 is also connected via a fuse FS3 and via a parallel combination of a resistor R74 and a diode D23 to a terminal to which an external direct current supply may be connected, for instance an accumulator. The cathodes of the diodes D14 and D15 are connected via a resistor R45 to the collector of a power transistor To12, whose base is connected to the integrated circuit regulator 125 and whose emitter is connected via a resistor R66 and a diode D18 to the battery 111. Both sides of the resistor R66 are connected to the integrated circuit regulator 125 so as to provide a current limiting function. The collector of the transistor It 12 is connected to the base of a transistor TR1 1 whose collector is connected via a diode D16 to the emitter of the transistor TR12.The emitter of the transistor TRI 1 is connected via a resistor R64 to the capacitor C37. A capacitor C38 is connected between the collector of the transistor TR1 2 and the common line to provide decoupling and stabilityforthe regulator 125.

The control input of the regulator 125, also provided with a decoupling capacitor C29, is connected to the slider of a potentiometer VR2 whose track is connected in series with a resistor R68 across the output of the regulator 112.

The positive terminal of the battery 111 is connected via an ON-OFF switch SW1 to the 6v power supply line and to the 5v regulator 113. The 5v regulator 113 comprises a series regulating power transistor TR1 5 whose emitter is connected to the switch SW1 and whose collector is connected to the regulated 5v supply line. The base of the transistor TR15 is connected to the collector of a transistor TR14, whose emitter is connected to the common line. The base ofthetransistorTR14 is connected via a capacitor C40 to the collector thereof and via a diode D21 to a connection between a resistor R73, a diode D20, and the collector of a transistor TR13. The other side of the diode D20 is connected to the input ENABLE line of the power supply section.The emitter of the transistor TRI 3 is connected via a resistor R69 to the input of the regulator 113, via a zener diode D19 to the common line, and via a series combination of a resistor R70, a variable resistor VR3 and a diode D22 to the regulated 5v line. The base of the transistor TR13 is connected to the tapping point of a potential divider formed by resistors R71 and R72 across the output of the voltage regulator 113.

Figure 3 shows in more detail the input section 106 of the microprocessor alarm system. The electroacoustic transducer 107 in the form of a hooter also capable of functioning as a microphone is connected to an input of the input section 106 and, via capacitors C3 and C4, to the common line. The input section comprises a differential amplifier 130 whose inputs are connected via respective series arrangements comprising resistor R5 and capacitor C6 and resistor R4 and capacitor C5 to either side of the hooter t07. The inverting input of the operational amplifier 130 is connected via a parallel arrangement of a resistor R6 and a capacitor C7 to the output thereof, whereas the non-inverting input of the amplifier 130 is connected via the resistor R3 to a potential midway between the 6v supply line and the common line as defined by the potential divider comprising resistors R1 and R2 with the decoupling capacitors C1 and C2.

The output of the amplifier 130 is connected via a capacitor C8 and a resistor R10 to one end of the track of a variable resistor VR1 for setting the sensitivity of the alarm system. The other end of the track of the variable resistor VR1 is connected via a resistor R11 to the output of an operational amplifier 131 whereas the slider of the potentiometer is connected to the inverting input of the amplifier 131.

The inverting input is further connected to the output of the amplifier via a parallel circuit comprising a resistor R9 and a capacitor C9. The non-inverting input of the amplifier 131 is connected to a voltage divider comprising resistors R7, R8 and R46 and a decoupling capacitor C11.

The output of the amplifer 131 is connected via a capacitor C10 and a resistor R12 to the inverting input of another amplifier 132 provided with a feedback network comprising resistor R13 and capacitor C12. The non-inverting input of the amplifier 132 is connected to the connection between the resistor R7 and the resistor R8. The output of the amplifier 132 is connected via a capacitor C13 and a resistor R14 to the inverting input of yet another amplifier 133 also provided with a feedback network comprising a resistor R15 and a capacitor C14. The non-inverting input of the amplifier 133 is connected to the connection between the resistor R8 and the resistor R46. The amplifiers 130 to 133, together with their coupling and feedback networks, form a high pass filter for removing frequencies below 1KHz.

The output of the amplifier 133 is connected via a diode D5 and a resistor R20 to the output terminal of the input section 106. The output terminal is further connected via a parallel circuit comprising a capacitor C18 and a resistor R21 to the common line and directly to the cathode of a diode D2 at one side of a resistor R16. The other side of the resistor R16 is connected via a diode D26 to a terminal H16 for connection via a "panic circuit" to the 6v supply line at terminal H20. The anode of the diode D2 is connected via a resistor R19 and a diode D3 to the common line and to one side of a capacitor C16.The other side of the capacitor C16 is connected via a resistor R 8 to the 6v supply line, via a capacitor C15 to the common line, via a resistor R82 and a diode D1 to a terminal H13 and via a resistor R17 to a terminal H14. A closed loop circuit can be arranged between the terminal H14 and the terminal H15, which is connected to the common line, whereas an open loop circuit can be connected between the terminals H13 and H20.

Figure 4 shows the clock 121, which comprises an astable multivibrator circuit including transistors TR1 and TR2. The emitters of these transistors are connected to the common line whereas the collectors thereof are connected via resistors R22 and R26 to the 5v supply line, which is decoupled by a capacitor C21. The base of the transistor TR2 is connected via a resistor R23 to the 5v supply line and via a capacitor C19 to the collector of the transistor TRI. The base of the transistor TR1 is connected via a resistor R24 to the 5v supply line and to one side of a capacitor C20.The other side of the capacitor C20 is connected via a resistor R25 to the 5v supply line and via a diode D6 to the collector of the transistor TR2, which collector is connected to the output terminal of the clock. The values chosen for the components of the clock are such as to provide a 1MHz clock signal for the microprocessor section 101.

Figure 5 shows the horn driver 122 and the relay driver in more detail. The output terminals X and Y of the horn driver are connected across the horn 107.

The terminal Xis connected via a diode D12 to the common line, to the collector of a TR10 whose emitter is connected to the 6v supply line, and via a resistor R83 to the 6v supply line. The base of the transistor TR10 is connected to the tapping point of a potential divider comprising resistors R62 and R63 which are connected between the 6v supply line and the collectors of transistors TR6 and TR7. The terminal Y is connected via a diode D13 to the 6v supply line and to the collectors of transistors TR8 and TR9. The emitter of the transistor TR9 is connected to the common line whereas the emitter of the transistor TR8 is connected to the base of the transistor TR9 and via a resistor R61 to the common line. A decoupling capacitor C42 is connected between the common line and the 6v supply line.

The base of the transistor TR8 is connected via a resistor R58 to the data input and inverted output of a D-type bistable IC9, which are also connected via a resistor R59 to the base of the transistor TR6. The base of the transistor TR6 is connected via a diode D4 to the line AA. The collector of the transistor TR6 is connected to the collector of the transistor TR7 whereas the emitter is connected to the base of the transistor TR7 and via a resistor R60 to the common line. The emitter of the transistor TR7 is connected to the common line whereas the collector thereof is connected to a terminal H21 and via a diode D11 to the terminal H20. The terminals H20 and H21 are provided for connection to a remote audible alarm device.

The bistable IC9 has a clock input connected to the output A12 of the microprocessor section 101 and a set input connected to the collector of a transistor TR5 and via a resistor R57 to the 6v supply line. The emitter of the transistor TR5 is connected to the common line whereas the base thereof is connected to the cathode of a diode D24 and via a resistor to the common line. The anode of the diode D24 is connected to the anode of a diode D10 and via a resistor R55 to the connection between a capacitor C36 and a resistor R56. The resistor R56 is connected via a diode D8 to the output Q of the bistable 109. The anode of the diode D10 is connected to the reset line and to the cathode of a diode D27 whose anode is connected to the base of the transistor TR8.

The relay driver 123 comprises another D-type bistable forming part of the integrated circuit IC9 and having a reset input connected to the restart line and a clock input connected to the output A14 of the microprocessor section 101. The inverted output of this bistable element is connected to the data input thereof whereas the non-inverted output is connected via a resistor R51 to the base of a transistor TR4 which is connected via a resistor R52 to the common line. The emitter of the transistor TR4 is connected to the common line whereas the collector thereof is connected via the parallel combination of a relay RLA/1 and a diode D7 to the 6v supply line. The relay has a single changeover contact RLA1 connected as a normally open contact between the line input and line output terminals of a mains supply line.A switch SW3 is connected in parallel with the relay contact RLA1.

The operation of the microprocessor alarm system is as foilows. The regulator 112 receives power either from the mains or from a low voltage DC supply and provides a 6.8v output for correct trickle charging of the battery 111 which is a 6v sealed lead acid battery. The regulator includes a current limit to limit the current to 200 mA so as to prevent overcharging. The 5v regulator 113 is supplied by the battery 111 when the system is switched on by the switch SW1 and is capable of being switched ON or OFF in approximately 100 uS by a signal supplied to its enable input.

The hooter 107 is arranged so as to receive sound from within a room or the like to be protected by the alarm system. The signals from the hooter are amplified by the amplifiers 130 and 133 and signals of frequencies below approximately 1 KHz are removed. The sensitivity is set by means of the potentiometer VR1. The diode D5, the resistors R20 and R21, and the capacitor C18 constitute a peak detector for the envelope of the signal and the output thereof is supplied via the gate 105, which functions as a comparator, to the interrupt input of the microprocessor section 101. Thus, when sound of a sufficient level is received by the hooter 107 an interrupt signal is supplied to the microprocessor section 101.

A closed loop circuit is provided between the terminals H14and H15. If this loop is opened, for instance by tampering or by normally closed intruder detection switches, the charge normally held in the capacitor C16 is transferred to the capacitor C18 so that an interrupt signal is supplied to the microprocessor section. An open loop circuit is provided between the terminals H13 and H20. Normally open switches for intruder detection may be connected between these two terminals. When these terminals are shorted together, the charge on the capacitor C16 is similarly transferred to the capacitor C18 so that an interrupt signal is supplied to the microprocessor section, even when there is a short circuit between the terminals H14 and H15.

A "panic" circuit is connected between the terminals H16 and H20. This allows a "panic" button to be connected to the alarm system to allow manual operation thereof. This panic button is a latching device and causes a permanent interrupt signal to be supplied to the microprocessor section by shorting the terminals together. A shunt circuit is connected between the pins H15 and H22 in the form of a normally open switch. When the switch is closed, transistorTR16 is held on and this, via the gates 108, 110, 114, and 115, prevents switching on of the 5v supply so as to inhibit the alarm except in the case of operation of the panic circuit.In this case, when the terminals H16 and H20 are shorted together, this produces an interrupt signal but also prevents the shunt circuit from inhibiting switch on by means of the resistor R80, the gate 124, and the diode D25.

When the shunt is released, a non maskable interrupt is allowed as will be described hereinafter.

A remote audible alarm device connected to the terminals H20 and H21 can be inhibited by a signal on the line AA. The restart and preset lines are provided to ensure that no erroneous operation of the bistables in the output section can occur when the microprocessor is switched on and off. The transistor TR5 ensures that, when the 6v power supply is first switched on, the bistable controlling the hooter sets with the hooter driver switched off.

The microprocessor alarm system is such that it is capable of being actuated by the sounds of breaking glass, wood or other materials whilst being insensitive to the sounds of passing traffic or people outside the building. Figures 7a to fare a flow diagram of the operation of the microprocessor in accordance with its stored program. This is such that the system does not produce false alarms caused by sound such as hard knocks on glass which may simulate the sound of breaking wood or glass. In order to achieve this, the microprocessor is arranged to time the duration of the output signal from the input section corresponding to sound received by the hooter 107. Upon receiving the first sound, this is timed and, assuming it lasts for 30 ms, a pulse is produced. If the duration of the sound exceeds 30 ms, a second pulse is produced, and so on.This continues until four pulses have been produced, which is considered to be an alarm condition. However, the microprocessor also performs a timing function so that four pulses must be produced within a time window of approximately 2 to 3 secs in order for an alarm condition to be recognised. A single tap on glass would normally produce one pulse whilst the action of breaking glass would produce several, thus activating the alarm system.

The system has essentially three modes of operation, namely self test function, set up and escape function, and armed function. These modes of operation will be described hereinafter.

In the self test function, when the system is first switched on, power is supplied from the 6v battery to the 6v supply line and via the 5v regulator to the microprocessor section and associated circuits. The CR networks comprising resistors R27 and R28 and the capacitors C25 and C26, together with the gate 117, ensure that the microprocessor is reset until all switch bounce has gone and the power supplies have settled. A non maskable interrupt is then enabled externally by the output A15 of the microprocessor, which causes the microprocessor section to enter the self test routine. The random access memory is filled with a chequer pattern of l's and 0's, read back, and then the procedure reversed i.e.

the complement of the pattern is stored and read back. The microprocessor checks to see whether the correct pattern in each case is read back from the memory. The contents of the read only memory are then checked against check sums contained therein by adding up sets of 16 nibbles (each of four bits) at a time and comparing with the stored results. Different tones are produced by the hooter to indicate correct orfaultyoperation of the random access memory and read only memory. In particular, a single tone lasting one second is given to indicate correct operation of both memories and is also used to check correct operation of the hooter and the input section. If the operation is correct, an interrupt signal is supplied to the microprocessor to indicate that the system is working correctly.A further tone is then produced to indicate the setting of the delay switch, which will be described hereinafter. The absence of this tone indicates that the input section, particularly the audio circuits thereof, are faulty. The relay RW1 is also operated for 1 second at this time to enable the user to check correct operation, for instance, of a warning light connected thereto. Once this operation has been completed, the system then enters the set up and escape mode.

At the beginning of the set up and escape mode, a 1 minute timer is started. If nothing occurs during this time interval, then the timer finishes and a tone lasting 1 second is produced followed by a 2 second period to ensure that the system is not accidently triggered by the tone. The microprocessor then switches off the 5v supply regulator 113 by a signal on the output line A15 which sets the bistable comprising the gates 114 and 115, thus supplying a disable signal to the enable input of the regulator 113. If a signal is provided as a result of the reception of sound by the hooter or by actuation of the panic input, the system becomes fully armed. The 1 minute time interval may therefore be used as an escape period to allow people to leave the building safety before the alarm is armed.

The one minute period may be used to provide an indefinite setting up period. In particular, if an audio input is detected during the 1 minute period, then the microprocessor will cause the hooter to produce a series of tones equivalent to the number of effective pulses produced up to a maximum of 9.

This enables the audio sensitivity to be set by tapping on windows in the protection premises so that only one or two pulses are produced. Each time this occurs, the 1 minute timer is restarted and the process may be continued indefinitely. Actuating the various loops will also cause groups of 9 pulses for the duration of the discharge of the capacitor C16, which is about 20 seconds, above the interrupt threshold as determined by the gate 105 operating as a comparator.

Whenever the 1 minute interval finishes, a 1 second tone is produced to indicate the end of the escape period followed by a 2 second reset. The microprocessor then switches off and enters the armed mode. The remote sounder when connected to the terminals H20 and H21 is inhibited during the self test mode and the set up and escape mode by the line AA. Also, the tones produced during the test and set-up and escape modes are of reduced level because the resistor R83 is effectiveiy in series with the hooter.

In the armed mode, the microprocessor is normally switched off because the retulators 113 is disabled, although the other circuits of the alarm system continue to be supplied by the battery 111.

Switching on and off of the microprocessor in this way reduces power consumption greatly and enables long stand-by-times, for instance of the order of one week, to be achieved. This allows the system to be used where no mains power is available and also when a power failure has occurred.

When the 5v regulator is to be switched on because of signals produced by the input section as a result of the receiving of audio signals or the switching of the loop circuits, the 5v supply line comes on quickly, for instance 100 uS, and only a short reset time of 1 ms is provided in order to prevent the loss of any audio information. The non maskable interrupt is also inhibited externally by the capacitors C27, C28 and the resistors R35 and R37, the capacitors having charged up during the initial switch on if no shunt signal was present. When the microprocessor is switched on, it carries out the alarm sensing function as described herein before.

However, there are two types of armed operation, namely delayed and non delayed. In both cases, if the microprocessor is switched on but no alarm condition is detected, the microprocessor remains on for approximately one minute waiting for further inputs. During this period, the relay RW1 is operated so that any warning lights are on.

In the armed mode without entry delay, then, if up to three pulses are produced by the input section as a result of sound detected by the hooter, the microprocessor switches on and, after a three second delay, energises the relay for one minute. If nothing further happens, then the microprocessor switches off. If, during the one minute period, further pulses are produced then, if three or less occur in any three second period, the relay remains energised for one minute from the last pulse received.

However, if four or more pulses occur in any three second period, the system them goes into the alarm state as described hereinafter. Alternatively, if four or more pulses are produced within the initial three second period, the microprocessor switches on and this is followed by an immediate alarm condition, which causes the relay to cycle once every 2 seconds and the hooter to emit a warble tone for four minutes, after which it switches off.

If the system is operating in the armed mode with entry delay, then when up to three pulses are produced within any three second period, the microprocessor switches on to provide the 3 second delay and then energises the relay for 1 minute, after which the microprocessor switches off. If during this 1 minute period further pulses are produced then, provided three or less pulses are produced in any 3 second period, the microprocessor operates as in the case of the armed mode without entry delay. If four or more pulses are produced in any 3 second period during the 1 minute interval, then the microprocessor waits for a 30 second period before entering the alarm condition. Alternatively, if four or more pulses are produced in the initial 3 second interval, the microprocessor switches on and after a 30 second delay with the relay energised, enters the alarm condition. The 30 second delay period thus allows an authorised person to enter the building and to disarm the alarm system before an alarm is raised.

In the case where a shunt switch is connected between the terminals H15 and H22, the main ON-OFF switch may be left on and the system may be remotely armed and disarmed by means of the shunt switch. When the shunt switch is closed and the set up mode is finished, the system cannot be activated except when a panic signal is provided.

When the shunt switch is released, the alarm automatically enters the test and set up mode as the shunt signal enables the non maskable interrupt by the capacitor C27 and the resisters R35 and R36 which forces the microprocessor into the test program. The armed mode then follows until the switch is closed agan. Detailed operation of the microprocessor is given in the flow diagram of Figure 7a to f.

Various modifications may be made within the scope of the invention. For instance, the loop inputs, panic inputs, and shunt inputs may be supplied to the microprocessor data bus via a set of latches which remain powered at all times. This arrangement provides the microprocessor with information as to the previous and current states of these inputs.

Although the microprocessor is switched off during normal operation of the system, the monitoring circuitry remains active at all times to provide a continuous tamper facility. Thus, instead of on ON/OFF switch, there is provided a key switch which acts as an integral shunt.

Whenever there is change of state of any of the inputs, power is supplied to the mocroprocessor, which also receives a non-maskable interrupt causing the microprocessor to enter a checking program to analyse the change. The microprocessor thus decides whether to enter a a test routine or an alarm routine, and switches itself off again if no action is required. Also, the audio part of the system is active only when the system is armed.

According to another modification, the system is made sensitive to the number of time windows generated by the microprocessor in a predetermined time interval. Thus, when the system is in its armed mode, an alarm is produced whenever more than a predetermined number of pulses is received within a time window which is generated upon receipt of an initial pulse, as described herein before. However, the microprocessor also counts the number of time windows generated within a particular time interval, which may conveniently be made identical to the minimum on-time of the microprocessor, for instance one minute. If more than a predetermined number, for instance 12, time windows are produced within the interval of one minute, then the microprocessor determines an alarm condition and subsequent operation of the system is as described herein before.

This additional mode of operation allows the system to detect an unforced entry by an intruder, for instance by means of a duplicate key. In the absence of a break-in by the intruder, it is possible for an insufficient number of pulses to be produced within each time window in order to trigger an alarm. However, as the intruder wanders around opening drawers and the like, various noises will be received by the system which are insufficient to generate the required number of pulses during each time window, but which nevertheless generates a series of time windows. When the number of time windows thus produced exceeds the predetermined number within the timed interval, an alarm is again triggered.

Claims (17)

1. A microprocessor alarm system, comprising an electroacoustic transducer and a microprocessor, the microprocessor being arranged in response to the reception by the electroacoustic transducer of a sound level above a threshold level,to time a predetermined interval and to time a delay, to time a further delay after each preceding delay whenever the transducer receives a sound level above the threshold level, to time a further predetermined interval after each preceding predetermined interval whenever the transducer receives a sound level above the threshold level, and to enter an alarm mode if the number of timed delays exceeds a predetermined number within any one of the predetermined intervals.

2. A system as claimed in claim 1, in which the electroacoustic transducer is connected via an envelope detector and a comparator to an interrupt input of the microprocessor.

3. A system as claimed in claim 1 or 2, in which each predetermined interval is 2 to 3 seconds, the predetermined number is 4, and each delay is substantially equal to 30 milliseconds.

4. A system as claimed in any one of the preceding claims, including a circuit arrangement arranged to supply power to the microprocessor only for a predetermined period after reception by the transducer of a sound level above the threshold level.

5. A system as claimed in claim 4, in which the predetermined period is one minute.

6. A system as claimed in any one of the preceding claims, in which the microprocessor is arranged to enter the alarm mode whenever a predefined number of predetermined intervals is timed within a predetermined time.

7. A system as claimed in claim 6 when dependent on claim 4 or 5, in which the predetermined time is equal to the predetermined period.

8. A system as claimed in claim 7 when dependent on claim 5, in which the predefined number is 12.

9. A system as claimed in any one of the preceding claims, in which the microprocessor is arranged to supply a signal for raising an alarm after a predefined delay from entering the alarm mode.

10. A system as claimed in claim 9, in which the predefined delay is 30 seconds.

11. A system as claimed in any one of the preceding claims, including an intruder detection circuit for connection to a normally closed intruder detection circuitandlortoa normally open intruder detection circuit, the microprocessor being arranged to respond to opening of the normally closed circuit and/or to closing of the normally open circuit in the same way as to reception by the transducer of a sound level above the threshold level.

12. A system as claimed in any one of the preceding claims, in which the microprocessor is provided with a random access memory, the microprocessor being arranged to check correct operation of the random access memory by storing therein a chequer pattern of 0's and l's, by reading the contents of the memory, and by checking the contents of the memory as read.

13. A system as claimed in claim 12, in which the microprocessor is arranged to perform a subsequent further memory checking operation by storing in the memory a pattern of 0's and 1 's complementary to the chequer pattern, by reading the contents of the memory, and by checking the contents of the memory as read.

14. A system as claimed in any one of the preceding claims, in which the microprocessor is provided with a read only memory and is arranged to check the read only memory by calculating one or more sums of the contents of the memory and checking the one or more sums against the known correct sum or sums.

15. A system as claimed in claim 14, in which the microprocessor is arranged to form a plurality of sums, each comprising the sum of 16 nibbles where each nibble is four bits, and to compare each sum with the known value which is stored in the memory.

16. A microprocessor alarm system substantially as herein before described with reference to and as illustrated in the accompanying drawings.

17. A microprocessor alarm system, comprising an electroacoustic transducer, a microprocessor arranged to control the production of alarm signals and a circuit arrangement arranged to prevent the supply of power to the microprocessor during standby operation and to permit the supply of power to the microprocessor after reception by the transducer of a sound level above the threshold level.