GB2101852A - Data transmission - Google Patents

Abstract

In data transmission systems in which data is sent in binary bit streams (eg using HDLC format) and the clock at the receiver is derive from, or synchronised to, the change, eg from 0 to 1, in logic state in the incoming bit stream, the bits as they go out also go into a n bit shift register (SR) whose contents are monitored by an OR gate (01) detecting n 0 bits (eg n is between 2 and 8). When such a condition is detected, sending is delayed while a 1 bit is inserted after the nth 0 bit. At the receiver, the incoming bits go into an (n + 1) bit shift register whose contents are monitored by gating means for the combination of n 0 bits followed by a 1 bit. When this condition is detected, that 1 bit is detected. The added 1 bit, used in conjunction with HDLC code driving a phase locked loop oscillator (PLO), ensures that sync. is not lost because of a long string of 0 bits. At the receiver there is a further monitoring for (n + 1) successive 0 bits: if this is detected, an error indication is given. <IMAGE>

Description

SPECIFICATION Data transmission This invention relates to data transmission, and especially to the coding of an HDLC data stream for direct transmission, together with the decoding of the data stream back into an HDLC format.

HDLC, which stands for High Level Data Link Control is a data transmission protocol for link access procedures in a telecommunication system. It involves the transmission of signalling or other messages encoded in digital form in successive bit frames. An information-conveying bit frame starts with an eight-bitflag (01111110), then an eight bit address code, then eight or sixteen bits for control bits, then the information to be conveyed, which may be a number of eight-bit words, and then sixteen bits of parity checking information. It is desirable on reception to be able to derive a clock from an incoming bit stream as this facilitates synchronisation between the stations. However, if a long stream of 0 bits occur in the data stream, the local clock may drift out of synchronisation before the next one bit.An object of the invention is to obviate this difficulty.

According to the invention there is provided a data transmission system, in which data is transmitted as a binary bit stream with the clock at the receiving station derived from or synchronised by the change to one defined logic state in the incoming binary bit stream, in which when the original bit stream includes a number n (where n is an integer at least equal to 2) of successive bits in the other logic stage an additional bit of said one defined logic state is inserted into the bit stream, in which on reception the bit stream is monitored in search of a number n of successive bits in said other logic state, and in which if a received bit stream is found as a result of said monitoring to include n successive bits in said other logic state a bit of said one defined logic state immediately following said n successive bits in said other logic state is deleted.

An embodiment of the invention will now be described with reference to the accompanying drawing, in which Figure 1 is as much of an encoder as is necessary to explain the invention and Figure 2 is as much of a decoder as is necessary to understand the invention.

In a system embodying the present invention, there is an encoder at the sending end whch inserts a logic "one" into the bit stream, which in the present case is an HDLC data stream, wherein a series of n consecutive "zeros" is detected. At the receiving end there is a decoder whose function is to remove a logic "one" following n consecutive "zeros", thus returning the data to its original format. Note that although we have described the invention as applied to a system using HDLC data streams, it is applicable to other forms of data transmission. The input to the encoder is an HDLC data stream with the constraints that only one "abort" command is allowed per data packet, and only synchronising frames or bytes are used as the inter-frame fillers.The latter arises because it is usual when no actual messages are being sent to send "filler" frames to maintain synchronisation and to enable such faults on line breaks to be detected.

The numbern referred to above is an integer between two and eight, the actual value chosen being dependent on the characteristics of the system in which it is used.

The decoder detects any received error arising from more than n zeros received consecutively, such a condition being detected as a fault condition.

Where such a condition occurs in the messages its detection is used to cause some corrective action, usually a request for retransmission of the message.

The coding scheme gives a data stream which is code transparent, ensures a minimum frequency with which the encoded bit pattern changes state to facilitate clock recovery at the receiver, provides an additional cover error check facility, and does not significantly increase the bandwidth requirement as compared with that of the original HDLC data rate.

We now refer to Figure 1,which includes a data source DS connected to an HDLC transmitter, which has an output TD over which the HDLC bit stream passes to the encoder and an output TXC over which the transmitter's clock is applied to the encoder in its "not" or inverse form. The bit stream is applied via an inverter 11 and a NAND gate N1 to the D input of an n-bit shift register SR1,which register stress the current bit of the incoming data stream, plus the previous (n-1) bits. The stages of the register SR1 are respectively designated Q1 -Qn, the the output of the stage Q1 being the output of the shift register SR1.

This goes via an output stage OS to the transmission line.

When the outputs Q1-Qn from the shift register SR1 are all at logic "zero", the output of the OR gate 01 appears as logic zero, which disables the AND gate Al. This forces the transmitter clock TXC to stay at logic "zero" during the next logic one period the system clock. In addition, the NAND gate N1 is disabled, which forces the D input to the shift register SR1 to logic "one". Hence on the logic one-logic transition of the system clock, a logic one is clocked into Q1 of the shift register. This in turn causes a one bit to be sent to OS, and also the output from the OR gate Q1 to go to logic one, enabling both the AND and the NAND gates Al and N1.

The next logic zero-logic one transition of the system clock then appears at TXC of the HDLC transmitter, and shifts the next bit of the data stream out from TD to the encoder. This bit of data is then clocked into the shift register SR1 during the logic one logic zero transition of the system clock.

Figure 2 shows a decoder to complement the encoder of Figure 1.

The incoming bit stream is applied via a line receiver LR to the D input of an (n + 1) stage shift register SR2, whose clock CL is locked in frequency and phase to that defined by the incoming bit stream by a phase locked loop oscillator PLO. The output from this oscillator is the system clock of the encoder and also the HDLC receiver via the latter's input RXC, and has its logic one-logic zero transition occurring during the transition of the output of the line receiver. During normal operation the bit stream passes from Q0 of the register SR2 to the input RD of the HDLC receiver, from which it goes to the data receiver DR.

The OR gate 02 monitors the Q1 -Qn outputs of the shift register SR2 and its output feeds NOR gates N2 and N3. N2 has a second input from QO of SR2, and N3 has as its second input the inverse of that Q0, via the inverter 12. Thus the output of N2 goes to logic one if all of the outputs Q0 to Qn of the shift register SR2 are at zero, which indicates an error condition in the received bit pattern.

In the correct condition in which Q0 is at logic one and Ol to Qn are all at zero, the output from the NAND gate N3 describes the OR gate 03, so that RXC stays at logic one for the low period of the receiver clock. Hence the input of one bit, the inserted logic one following n degrees, is removed from the bit stream as received by the HDLC receiver.

The arrangements described herein were specifically designed for use in a data transmission system in which the transmission line between the stations served is an optical fibre cable. Hence the output circuit OS in Figure 1 is an electrical-optical conversion circuit, e.g. one in which light is launched by a laser or a light-emitting diode. The line receiver LR is then an optical-electrical conversion circuit, in which the light from the line is incident, for instance, on a photo-transistor. However, the invention is also applicable to systems in which the transmission line is electrical.

Claims (8)

1. A data transmission system, in which data is transmitted as a binary bit stream with the clock at the receiving station derived from or synchronised by the change to one defined logic state in the incoming binary bit stream, in which when the original bit stream includes a number n (where n is an integer at least equal to 2) of successive bits in the other logic state an additional bit of said one defined logic state is inserted into the bit stream, in which on reception the bit stream is monitored in search of a number n of successive bits in said other logic state, and in which when a received bit stream is found as a result of said monitoring to include n successive bits in said other logic state a bit of said one defined logic state immediately following said n successive bits in said other logic state is deleted.

2. A data transmission system, in which data is transmitted as a binary bit stream with the clock at the receiving station derived from or synchronised by the change in logic state in the incoming binary bit stream to the logic one state, in which when the bit stream includes a number n (where n is an integer in the range 2 to 8) of successive bits in the logic zero state an additional bit in the logic one state is inserted into the bit stream, in which on reception the bit stream is monitored in search of a number of successive bits in said logic zero state, and in which if a received bit stream is found as a result of said monitoring to include n successive bits in said logic zero tate followed by a bit in said logic one state said last-mentioned bit in said logic one state said last-mentioned bit in said logic one state which immediately follows said n successive bits in said logic zero state is deleted.

3. A data transmission system as claimed in claim 1 or 2, in which at a transmitting station the bits of the bit stream as they are sent out are also stored in an n shift register, in which the contents of said shift register are checked by an ninput OR gate whose output is only effective when the shift register contains n bits in said other logic state or said zero state, and in which said output from said OR gate causes the insertion into the bit stream of said one defined logic state or said one state.

4. A data transmission system as claimed in claim 1, 2 or 3, in which at a receiving station the bits of the bit stream as they are received are also stored in an (n + 1) bit shift register, in which the contents of said (n + 1) bit shift register are checked by gating means which responds to the coincidence of a bit of said one logic state preceded by n bits of said other logic state or a logic one bit preceded by n logic zero bits, and in which the response of said gating means causes the deletion of that one bit.

5. A data transmission system as claimed in claim 4, and in which the receiving station has further gating means which checks for the presence of (n + 1) bits of said other state or (n + 1) bits of said zero state in the shift register, and in which if said further gating means detects such a condition it gives an error indication.

6. A data transmission system substantially as described with reference to the accompanying drawing.

7. A transmitter for use in a data transmission system, substantially as described with reference to Figure 1 of the accompanying drawing.

8. A receiver for use in a data transmission system, substantially as described with reference to Figure 2 of the accompanying drawing.